Hardware Abstraction Layer (HAL)
HAL API Reference
The following provides a list of HAL API documentation
[detail level 1234]
 HAL General Types/MacrosThis section documents the basic types and macros that are used by multiple HAL drivers
 Result Type
 General TypesThis section documents the basic types that are used by multiple HAL drivers
 Overrideable MacrosThese macros can be defined to a custom value globally to modify the behavior of the HAL
 Implementation Specific TypesThe following types are used by the HAL, but are defined by the implementation
 HAL Driver AvailabilityThis section documents the macros that can be used to check if a specific driver is available for the current device
 HAL DriversThis section documents the drivers which form the stable API of the ModusToolbox™ HAL
 ADC (Analog to Digital Converter)High level interface for interacting with the analog to digital converter (ADC)
 ClockInterface for getting and changing clock configuration
 COMP (Analog Comparator)High level interface for interacting with an analog Comparator
 CRC (Cyclic Redundancy Check)High level interface for interacting with the CRC, which provides hardware accelerated CRC computations
 DAC (Digital to Analog Converter)High level interface for interacting with the digital to analog converter (DAC)
 DMA (Direct Memory Access)High level interface for interacting with the direct memory access (DMA)
 EZI2C (Inter-Integrated Circuit)High level interface for interacting with the Cypress EZ Inter-Integrated Circuit (EZI2C)
 System Power ManagementInterface for changing power states and restricting when they are allowed
 GPIO (General Purpose Input Output)High level interface for configuring and interacting with general purpose input/outputs (GPIO)
 HWMGR (Hardware Manager)High level interface to the Hardware Manager
 I2C (Inter-Integrated Circuit)High level interface for interacting with the I2C resource
 I2S (Inter-IC Sound)High level interface for interacting with the Inter-IC Sound (I2S)
 Interconnect (Internal Digital Routing)High level interface to the Infineon digital routing
 IPC (Inter-Processor Communication)High level interface for communicating between processors on a multi-core device
 KeyscanHigh level interface for interacting with the KeyScan
 LPTimer (Low-Power Timer)High level interface for interacting with the low-power timer (LPTimer)
 NVM (Onboard Non-Volatile Memory)High level interface to the onboard Non-Volatile memory (Internal Flash, RRAM, OTP region)
 Opamp (Operational Amplifier)High level interface for interacting with the Operational Amplifier (Opamp)
 PDM/PCM (Pulse-Density Modulation to Pulse-Code Modulation Converter)High level interface for interacting with the pulse-density modulation to pulse-code modulation (PDM/PCM) converter
 PWM (Pulse Width Modulator)High level interface for interacting with the pulse width modulator (PWM) hardware resource
 QSPI (Quad Serial Peripheral Interface)High level interface for interacting with the Quad-SPI interface
 Quadrature DecoderHigh level interface for interacting with the Quadrature Decoder hardware resource
 RTC (Real-Time Clock)High level interface for interacting with the real-time clock (RTC)
 SDHC (SD Host Controller)High level interface to the Secure Digital Host Controller (SDHC)
 SDIO (Secure Digital Input Output)High level interface to the Secure Digital Input Output (SDIO)
 SPI (Serial Peripheral Interface)High level interface for interacting with the Serial Peripheral Interface (SPI)
 SystemHigh level interface for interacting with reset and delays
 TDM (Time Division Multiplexed)High level interface for interacting with the Time Division Multiplexed controller (TDM)
 Timer (Timer/Counter)High level interface for interacting with the Timer/Counter hardware resource
 TRNG (True Random Number Generator)High level interface to the True Random Number Generator (TRNG)
 UART (Universal Asynchronous Receiver-Transmitter)High level interface for interacting with the Universal Asynchronous Receiver-Transmitter (UART)
 USB DeviceHigh level interface for interacting with the USB Device
 WDT (Watchdog Timer)High level interface to the Watchdog Timer (WDT)
 CAT1 Implementation SpecificThis section provides details about the CAT1 implementation of the Cypress HAL
 ClocksImplementation specific interface for using the Clock driver
 DMA (Direct Memory Access)DW (DataWire) is one of two DMA hardware implementations for CAT1 (PSoC™ 6)
 GPIO
 HAL Driver Availability Macros
 CAT1 Specific Hardware TypesAliases for types which are part of the public HAL interface but whose representations need to vary per HAL implementation
 Interconnect (Internal Digital Routing)The interconnect system connects the various hardware peripherals using trigger signals
 PinsDefinitions for the pinout for each supported device
 System Power ManagementOn CAT1 devices, the Pin based Hibernate wakeup sources (CYHAL_SYSPM_HIBERNATE_PINA_LOW, CYHAL_SYSPM_HIBERNATE_PINA_HIGH, CYHAL_SYSPM_HIBERNATE_PINB_LOW, and CYHAL_SYSPM_HIBERNATE_PINB_HIGH) are mapped to datsheet capabilities as follows:
PINA = hibernate_wakeup[0]
PINB = hibernate_wakeup[1]
 Timer (Timer/Counter)
 WDT (Watchdog Timer)The CAT1 WDT is only capable of supporting certain timeout ranges below its maximum timeout
 ADC (Analog Digital Converter)
 ADC (Analog Digital Converter)
 COMP (Analog Comparator)On CAT1 & CAT2, the comparator driver can use either of two underlying hardware blocks:
 DAC (Digital to Analog Converter)
 I2S (Inter-IC Sound)The CAT1 (PSoC™ 6) I2S Supports the following values for word lengths:
 IRQ Muxing (Interrupt muxing)There are two situations where system interrupts do not correlate 1:1 to CPU interrupts
 KeyScanOn CAT1 devices, the KeyScan peripheral is clocked from the shared source CLK_MF
 LPTimer (Low-Power Timer)The maximum number of ticks that can set to an LPTimer is 0xFFF0FFFF for non MCWDT-B devices
 Opamp (Operational Amplifier)
 PDM/PCM (Pulse Density Modulation to Pulse Code Modulation Converter)The CAT1A PDM/PCM Supports the following conversion parameters:
 PWM (Pulse Width Modulator)
 QSPI (Quad Serial Peripheral Interface)
 QuadDec (Quadrature Decoder)
 RTC (Real Time Clock)Internally the CAT1 RTC only stores the year as a two digit BCD value (0-99); no century information is stored
 SDHC (SD Host Controller)The SHDC HAL implemenation for CAT1 provides implementations for the following weak functions specified by the PDL to make their usage in SDHC HAL driver more flexible by providing user ability to use card detect, write protect, pwr en, and io select signals on custom pins instead of dedicated SDHC block pins
 SPI (Serial Peripheral Interface)
 TDM (Time Division Multiplexing)The CAT1 (PSoC™ 6) TDM Supports the following values for word lengths:
 UDB SDIO (Secure Digital Input Output)The UDB based SDIO interface allows for communicating between a CAT1 and a Cypress wireless device such as the CYW4343W, CYW43438, or CYW43012