Hardware Abstraction Layer (HAL)
UDB SDIO (Secure Digital Input Output)

The UDB based SDIO interface allows for communicating between a CAT1 and a Cypress wireless device such as the CYW4343W, CYW43438, or CYW43012.

This library allows CAT1 devices that do not have a dedicated SDHC hardware block, but do have UDBs, to work with the Wi-Fi Host Driver (WHD) library.

Warning
This library does not provide a complete SDIO implementation. It is only intended for use with a Infineon wireless device. Additionally, using this driver imposes a few system wide requirements, described below, that must be met to work properly.

Restrictions

The optimal configuration is to have ClkSlow & ClkPeri running at 100 MHz and for the SDIO to run at 25 MHz. For Infineon provided Board Support Packages (BSPs) that use this driver the necessary configuration is done automatically.

To use this library, the following must be true:

  1. ClkSlow & ClkPeri must both run at the same speed
  2. ClkSlow & ClkPeri must run at 4x the desired SDIO speed
  3. The first 8-bit peripheral clock divider must be reserved for use by this driver
  4. The following DMA channels must be reserved for use by this driver
    • DataWire 0 channel 0
    • DataWire 0 channel 1
    • DataWire 1 channel 1
    • DataWire 1 channel 3