The CAT1 (PSoC™ 6) TDM Supports the following values for word lengths:

8 bits
10 bits (CAT1B only)
12 bits (CAT1B only)
14 bits (CAT1B only)
16 bits
18 bits
20 bits
24 bits
32 bits

On CAT1A devices, the only supported channel length is 32 bits. On CAT1B devices, the channel length may be any value greater than or equal to the word length and less than or equal to 32 bits.

On CAT1A devices, up to 8 channels are supported. On CAT1B devices, the number of supported channels is specified by the TDM_NR<n>_CH_NR macros. Disabling channels (so that they are included in the sequencing but ignored) is only supported on CAT1B devices.

The sclk signal is formed by integer division of the input clock source (either internally provided or from the mclk pin). The CAT1A TDM supports sclk divider values from 1 to 64. On CAT1B devices, the TDM supports sclk divider values from 2 to 256. On CAT1A devices, if both RX and TX are used, the same GPIO must be specified for mclk in both directions. See the device datasheet for more details on valid pin selections.

The following events are not supported on CAT1B:

Note: If the TDM hardware is initialized with a configurator-generated configuration via the cyhal_tdm_init_cfg function, the CYHAL_TDM_TX_HALF_EMPTY and CYHAL_TDM_RX_HALF_FULL events will be raised at the configurator defined TX and RX FIFO trigger levels, respectively, instead of their usual trigger level of half the FIFO depth.