PSOC6_01

General Description

Trigger connections for psoc6_01.

PSoC™ 6S1 Triggers:

Macros
#define	CYHAL_TRIGGER_CPUSS_ZERO   (CYHAL_TRIGGER_CPUSS_ZERO_LEVEL)
	Deprecated defines for signals that can be either level or edge. More...
#define	CYHAL_TRIGGER_CSD_DSI_SENSE_OUT   (CYHAL_TRIGGER_CSD_DSI_SENSE_OUT_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_CSD_TR_ADC_DONE   (CYHAL_TRIGGER_CSD_TR_ADC_DONE_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_PASS_DSI_CTB_CMP0   (CYHAL_TRIGGER_PASS_DSI_CTB_CMP0_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_PASS_DSI_CTB_CMP1   (CYHAL_TRIGGER_PASS_DSI_CTB_CMP1_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_PERI_TR_IO_INPUT0   (CYHAL_TRIGGER_PERI_TR_IO_INPUT0_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_PERI_TR_IO_INPUT1   (CYHAL_TRIGGER_PERI_TR_IO_INPUT1_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_PERI_TR_IO_INPUT2   (CYHAL_TRIGGER_PERI_TR_IO_INPUT2_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_PERI_TR_IO_INPUT3   (CYHAL_TRIGGER_PERI_TR_IO_INPUT3_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_PERI_TR_IO_INPUT4   (CYHAL_TRIGGER_PERI_TR_IO_INPUT4_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_PERI_TR_IO_INPUT5   (CYHAL_TRIGGER_PERI_TR_IO_INPUT5_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_PERI_TR_IO_INPUT6   (CYHAL_TRIGGER_PERI_TR_IO_INPUT6_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_PERI_TR_IO_INPUT7   (CYHAL_TRIGGER_PERI_TR_IO_INPUT7_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_PERI_TR_IO_INPUT8   (CYHAL_TRIGGER_PERI_TR_IO_INPUT8_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_PERI_TR_IO_INPUT9   (CYHAL_TRIGGER_PERI_TR_IO_INPUT9_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_PERI_TR_IO_INPUT10   (CYHAL_TRIGGER_PERI_TR_IO_INPUT10_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_PERI_TR_IO_INPUT11   (CYHAL_TRIGGER_PERI_TR_IO_INPUT11_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_PERI_TR_IO_INPUT12   (CYHAL_TRIGGER_PERI_TR_IO_INPUT12_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_PERI_TR_IO_INPUT13   (CYHAL_TRIGGER_PERI_TR_IO_INPUT13_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_PERI_TR_IO_INPUT14   (CYHAL_TRIGGER_PERI_TR_IO_INPUT14_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_PERI_TR_IO_INPUT15   (CYHAL_TRIGGER_PERI_TR_IO_INPUT15_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_PERI_TR_IO_INPUT16   (CYHAL_TRIGGER_PERI_TR_IO_INPUT16_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_PERI_TR_IO_INPUT17   (CYHAL_TRIGGER_PERI_TR_IO_INPUT17_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_PERI_TR_IO_INPUT18   (CYHAL_TRIGGER_PERI_TR_IO_INPUT18_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_PERI_TR_IO_INPUT19   (CYHAL_TRIGGER_PERI_TR_IO_INPUT19_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_PERI_TR_IO_INPUT20   (CYHAL_TRIGGER_PERI_TR_IO_INPUT20_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_PERI_TR_IO_INPUT21   (CYHAL_TRIGGER_PERI_TR_IO_INPUT21_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_PERI_TR_IO_INPUT22   (CYHAL_TRIGGER_PERI_TR_IO_INPUT22_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_PERI_TR_IO_INPUT23   (CYHAL_TRIGGER_PERI_TR_IO_INPUT23_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_PERI_TR_IO_INPUT24   (CYHAL_TRIGGER_PERI_TR_IO_INPUT24_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_PERI_TR_IO_INPUT25   (CYHAL_TRIGGER_PERI_TR_IO_INPUT25_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_PERI_TR_IO_INPUT26   (CYHAL_TRIGGER_PERI_TR_IO_INPUT26_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_PERI_TR_IO_INPUT27   (CYHAL_TRIGGER_PERI_TR_IO_INPUT27_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_TR_GROUP10_OUTPUT0   (CYHAL_TRIGGER_TR_GROUP10_OUTPUT0_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_TR_GROUP10_OUTPUT1   (CYHAL_TRIGGER_TR_GROUP10_OUTPUT1_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_TR_GROUP10_OUTPUT2   (CYHAL_TRIGGER_TR_GROUP10_OUTPUT2_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_TR_GROUP10_OUTPUT3   (CYHAL_TRIGGER_TR_GROUP10_OUTPUT3_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_TR_GROUP10_OUTPUT4   (CYHAL_TRIGGER_TR_GROUP10_OUTPUT4_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_TR_GROUP10_OUTPUT5   (CYHAL_TRIGGER_TR_GROUP10_OUTPUT5_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_TR_GROUP10_OUTPUT6   (CYHAL_TRIGGER_TR_GROUP10_OUTPUT6_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_TR_GROUP10_OUTPUT7   (CYHAL_TRIGGER_TR_GROUP10_OUTPUT7_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_TR_GROUP11_OUTPUT0   (CYHAL_TRIGGER_TR_GROUP11_OUTPUT0_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_TR_GROUP11_OUTPUT1   (CYHAL_TRIGGER_TR_GROUP11_OUTPUT1_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_TR_GROUP11_OUTPUT2   (CYHAL_TRIGGER_TR_GROUP11_OUTPUT2_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_TR_GROUP11_OUTPUT3   (CYHAL_TRIGGER_TR_GROUP11_OUTPUT3_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_TR_GROUP11_OUTPUT4   (CYHAL_TRIGGER_TR_GROUP11_OUTPUT4_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_TR_GROUP11_OUTPUT5   (CYHAL_TRIGGER_TR_GROUP11_OUTPUT5_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_TR_GROUP11_OUTPUT6   (CYHAL_TRIGGER_TR_GROUP11_OUTPUT6_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_TR_GROUP11_OUTPUT7   (CYHAL_TRIGGER_TR_GROUP11_OUTPUT7_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_TR_GROUP11_OUTPUT8   (CYHAL_TRIGGER_TR_GROUP11_OUTPUT8_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_TR_GROUP11_OUTPUT9   (CYHAL_TRIGGER_TR_GROUP11_OUTPUT9_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_TR_GROUP11_OUTPUT10   (CYHAL_TRIGGER_TR_GROUP11_OUTPUT10_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_TR_GROUP11_OUTPUT11   (CYHAL_TRIGGER_TR_GROUP11_OUTPUT11_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_TR_GROUP11_OUTPUT12   (CYHAL_TRIGGER_TR_GROUP11_OUTPUT12_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_TR_GROUP11_OUTPUT13   (CYHAL_TRIGGER_TR_GROUP11_OUTPUT13_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_TR_GROUP11_OUTPUT14   (CYHAL_TRIGGER_TR_GROUP11_OUTPUT14_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_TR_GROUP11_OUTPUT15   (CYHAL_TRIGGER_TR_GROUP11_OUTPUT15_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_TR_GROUP12_OUTPUT0   (CYHAL_TRIGGER_TR_GROUP12_OUTPUT0_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_TR_GROUP12_OUTPUT1   (CYHAL_TRIGGER_TR_GROUP12_OUTPUT1_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_TR_GROUP12_OUTPUT2   (CYHAL_TRIGGER_TR_GROUP12_OUTPUT2_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_TR_GROUP12_OUTPUT3   (CYHAL_TRIGGER_TR_GROUP12_OUTPUT3_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_TR_GROUP12_OUTPUT4   (CYHAL_TRIGGER_TR_GROUP12_OUTPUT4_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_TR_GROUP12_OUTPUT5   (CYHAL_TRIGGER_TR_GROUP12_OUTPUT5_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_TR_GROUP12_OUTPUT6   (CYHAL_TRIGGER_TR_GROUP12_OUTPUT6_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_TR_GROUP12_OUTPUT7   (CYHAL_TRIGGER_TR_GROUP12_OUTPUT7_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_TR_GROUP12_OUTPUT8   (CYHAL_TRIGGER_TR_GROUP12_OUTPUT8_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_TR_GROUP12_OUTPUT9   (CYHAL_TRIGGER_TR_GROUP12_OUTPUT9_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_TR_GROUP13_OUTPUT0   (CYHAL_TRIGGER_TR_GROUP13_OUTPUT0_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_TR_GROUP13_OUTPUT1   (CYHAL_TRIGGER_TR_GROUP13_OUTPUT1_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_TR_GROUP13_OUTPUT2   (CYHAL_TRIGGER_TR_GROUP13_OUTPUT2_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_TR_GROUP13_OUTPUT3   (CYHAL_TRIGGER_TR_GROUP13_OUTPUT3_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_TR_GROUP13_OUTPUT4   (CYHAL_TRIGGER_TR_GROUP13_OUTPUT4_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_TR_GROUP13_OUTPUT5   (CYHAL_TRIGGER_TR_GROUP13_OUTPUT5_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_TR_GROUP13_OUTPUT6   (CYHAL_TRIGGER_TR_GROUP13_OUTPUT6_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_TR_GROUP13_OUTPUT7   (CYHAL_TRIGGER_TR_GROUP13_OUTPUT7_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_TR_GROUP13_OUTPUT8   (CYHAL_TRIGGER_TR_GROUP13_OUTPUT8_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_TR_GROUP13_OUTPUT9   (CYHAL_TRIGGER_TR_GROUP13_OUTPUT9_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_TR_GROUP13_OUTPUT10   (CYHAL_TRIGGER_TR_GROUP13_OUTPUT10_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_TR_GROUP13_OUTPUT11   (CYHAL_TRIGGER_TR_GROUP13_OUTPUT11_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_TR_GROUP13_OUTPUT12   (CYHAL_TRIGGER_TR_GROUP13_OUTPUT12_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_TR_GROUP13_OUTPUT13   (CYHAL_TRIGGER_TR_GROUP13_OUTPUT13_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_TR_GROUP13_OUTPUT14   (CYHAL_TRIGGER_TR_GROUP13_OUTPUT14_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_TR_GROUP13_OUTPUT15   (CYHAL_TRIGGER_TR_GROUP13_OUTPUT15_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_TR_GROUP13_OUTPUT16   (CYHAL_TRIGGER_TR_GROUP13_OUTPUT16_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_TR_GROUP13_OUTPUT17   (CYHAL_TRIGGER_TR_GROUP13_OUTPUT17_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_TR_GROUP14_OUTPUT0   (CYHAL_TRIGGER_TR_GROUP14_OUTPUT0_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_TR_GROUP14_OUTPUT1   (CYHAL_TRIGGER_TR_GROUP14_OUTPUT1_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_TR_GROUP14_OUTPUT2   (CYHAL_TRIGGER_TR_GROUP14_OUTPUT2_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_TR_GROUP14_OUTPUT3   (CYHAL_TRIGGER_TR_GROUP14_OUTPUT3_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_TR_GROUP14_OUTPUT4   (CYHAL_TRIGGER_TR_GROUP14_OUTPUT4_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_TR_GROUP14_OUTPUT5   (CYHAL_TRIGGER_TR_GROUP14_OUTPUT5_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_TR_GROUP14_OUTPUT6   (CYHAL_TRIGGER_TR_GROUP14_OUTPUT6_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_TR_GROUP14_OUTPUT7   (CYHAL_TRIGGER_TR_GROUP14_OUTPUT7_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_TR_GROUP14_OUTPUT8   (CYHAL_TRIGGER_TR_GROUP14_OUTPUT8_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_TR_GROUP14_OUTPUT9   (CYHAL_TRIGGER_TR_GROUP14_OUTPUT9_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_TR_GROUP14_OUTPUT10   (CYHAL_TRIGGER_TR_GROUP14_OUTPUT10_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_TR_GROUP14_OUTPUT11   (CYHAL_TRIGGER_TR_GROUP14_OUTPUT11_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_TR_GROUP14_OUTPUT12   (CYHAL_TRIGGER_TR_GROUP14_OUTPUT12_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_TR_GROUP14_OUTPUT13   (CYHAL_TRIGGER_TR_GROUP14_OUTPUT13_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_TR_GROUP14_OUTPUT14   (CYHAL_TRIGGER_TR_GROUP14_OUTPUT14_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_TR_GROUP14_OUTPUT15   (CYHAL_TRIGGER_TR_GROUP14_OUTPUT15_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_UDB_DSI_OUT_TR0   (CYHAL_TRIGGER_UDB_DSI_OUT_TR0_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_UDB_DSI_OUT_TR1   (CYHAL_TRIGGER_UDB_DSI_OUT_TR1_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_UDB_TR_UDB0   (CYHAL_TRIGGER_UDB_TR_UDB0_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_UDB_TR_UDB1   (CYHAL_TRIGGER_UDB_TR_UDB1_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_UDB_TR_UDB2   (CYHAL_TRIGGER_UDB_TR_UDB2_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_UDB_TR_UDB3   (CYHAL_TRIGGER_UDB_TR_UDB3_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_UDB_TR_UDB4   (CYHAL_TRIGGER_UDB_TR_UDB4_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_UDB_TR_UDB5   (CYHAL_TRIGGER_UDB_TR_UDB5_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_UDB_TR_UDB6   (CYHAL_TRIGGER_UDB_TR_UDB6_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_UDB_TR_UDB7   (CYHAL_TRIGGER_UDB_TR_UDB7_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_UDB_TR_UDB8   (CYHAL_TRIGGER_UDB_TR_UDB8_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_UDB_TR_UDB9   (CYHAL_TRIGGER_UDB_TR_UDB9_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_UDB_TR_UDB10   (CYHAL_TRIGGER_UDB_TR_UDB10_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_UDB_TR_UDB11   (CYHAL_TRIGGER_UDB_TR_UDB11_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_UDB_TR_UDB12   (CYHAL_TRIGGER_UDB_TR_UDB12_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_UDB_TR_UDB13   (CYHAL_TRIGGER_UDB_TR_UDB13_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_UDB_TR_UDB14   (CYHAL_TRIGGER_UDB_TR_UDB14_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_UDB_TR_UDB15   (CYHAL_TRIGGER_UDB_TR_UDB15_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.

Typedefs
typedef cyhal_trigger_source_psoc6_01_t	cyhal_source_t
	Typedef from device family specific trigger source to generic trigger source.
typedef cyhal_trigger_dest_psoc6_01_t	cyhal_dest_t
	Typedef from device family specific trigger dest to generic trigger dest.

Enumerations
enum	cyhal_trigger_source_psoc6_01_t {   CYHAL_TRIGGER_CPUSS_ZERO_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_ZERO, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CPUSS_ZERO_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_ZERO, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_AUDIOSS_TR_I2S_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_AUDIOSS_TR_I2S_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_AUDIOSS_TR_I2S_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_AUDIOSS_TR_I2S_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_AUDIOSS_TR_PDM_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_AUDIOSS_TR_PDM_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_CPUSS_CTI_TR_OUT0 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_CTI_TR_OUT0, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CPUSS_CTI_TR_OUT1 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_CTI_TR_OUT1, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CPUSS_DW0_TR_OUT0 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT0, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CPUSS_DW0_TR_OUT1 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT1, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CPUSS_DW0_TR_OUT2 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT2, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CPUSS_DW0_TR_OUT3 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT3, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CPUSS_DW0_TR_OUT4 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT4, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CPUSS_DW0_TR_OUT5 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT5, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CPUSS_DW0_TR_OUT6 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT6, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CPUSS_DW0_TR_OUT7 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT7, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CPUSS_DW0_TR_OUT8 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT8, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CPUSS_DW0_TR_OUT9 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT9, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CPUSS_DW0_TR_OUT10 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT10, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CPUSS_DW0_TR_OUT11 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT11, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CPUSS_DW0_TR_OUT12 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT12, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CPUSS_DW0_TR_OUT13 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT13, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CPUSS_DW0_TR_OUT14 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT14, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CPUSS_DW0_TR_OUT15 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT15, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CPUSS_DW1_TR_OUT0 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT0, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CPUSS_DW1_TR_OUT1 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT1, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CPUSS_DW1_TR_OUT2 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT2, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CPUSS_DW1_TR_OUT3 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT3, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CPUSS_DW1_TR_OUT4 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT4, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CPUSS_DW1_TR_OUT5 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT5, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CPUSS_DW1_TR_OUT6 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT6, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CPUSS_DW1_TR_OUT7 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT7, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CPUSS_DW1_TR_OUT8 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT8, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CPUSS_DW1_TR_OUT9 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT9, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CPUSS_DW1_TR_OUT10 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT10, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CPUSS_DW1_TR_OUT11 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT11, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CPUSS_DW1_TR_OUT12 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT12, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CPUSS_DW1_TR_OUT13 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT13, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CPUSS_DW1_TR_OUT14 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT14, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CPUSS_DW1_TR_OUT15 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT15, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CPUSS_TR_FAULT0 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_TR_FAULT0, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CPUSS_TR_FAULT1 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_TR_FAULT1, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CSD_DSI_SENSE_OUT_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CSD_DSI_SENSE_OUT, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CSD_DSI_SENSE_OUT_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CSD_DSI_SENSE_OUT, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_CSD_TR_ADC_DONE_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CSD_TR_ADC_DONE, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CSD_TR_ADC_DONE_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CSD_TR_ADC_DONE, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_LPCOMP_DSI_COMP0 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_LPCOMP_DSI_COMP0, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_LPCOMP_DSI_COMP1 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_LPCOMP_DSI_COMP1, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_PASS_DSI_CTB_CMP0_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS_DSI_CTB_CMP0, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_PASS_DSI_CTB_CMP0_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS_DSI_CTB_CMP0, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_PASS_DSI_CTB_CMP1_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS_DSI_CTB_CMP1, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_PASS_DSI_CTB_CMP1_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS_DSI_CTB_CMP1, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_PASS_TR_CTDAC_EMPTY = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS_TR_CTDAC_EMPTY, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_PASS_TR_SAR_OUT = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS_TR_SAR_OUT, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_PERI_TR_IO_INPUT0_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT0, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_PERI_TR_IO_INPUT0_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT0, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_PERI_TR_IO_INPUT1_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT1, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_PERI_TR_IO_INPUT1_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT1, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_PERI_TR_IO_INPUT2_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT2, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_PERI_TR_IO_INPUT2_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT2, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_PERI_TR_IO_INPUT3_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT3, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_PERI_TR_IO_INPUT3_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT3, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_PERI_TR_IO_INPUT4_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT4, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_PERI_TR_IO_INPUT4_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT4, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_PERI_TR_IO_INPUT5_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT5, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_PERI_TR_IO_INPUT5_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT5, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_PERI_TR_IO_INPUT6_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT6, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_PERI_TR_IO_INPUT6_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT6, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_PERI_TR_IO_INPUT7_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT7, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_PERI_TR_IO_INPUT7_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT7, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_PERI_TR_IO_INPUT8_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT8, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_PERI_TR_IO_INPUT8_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT8, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_PERI_TR_IO_INPUT9_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT9, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_PERI_TR_IO_INPUT9_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT9, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_PERI_TR_IO_INPUT10_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT10, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_PERI_TR_IO_INPUT10_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT10, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_PERI_TR_IO_INPUT11_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT11, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_PERI_TR_IO_INPUT11_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT11, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_PERI_TR_IO_INPUT12_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT12, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_PERI_TR_IO_INPUT12_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT12, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_PERI_TR_IO_INPUT13_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT13, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_PERI_TR_IO_INPUT13_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT13, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_PERI_TR_IO_INPUT14_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT14, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_PERI_TR_IO_INPUT14_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT14, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_PERI_TR_IO_INPUT15_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT15, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_PERI_TR_IO_INPUT15_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT15, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_PERI_TR_IO_INPUT16_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT16, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_PERI_TR_IO_INPUT16_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT16, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_PERI_TR_IO_INPUT17_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT17, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_PERI_TR_IO_INPUT17_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT17, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_PERI_TR_IO_INPUT18_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT18, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_PERI_TR_IO_INPUT18_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT18, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_PERI_TR_IO_INPUT19_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT19, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_PERI_TR_IO_INPUT19_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT19, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_PERI_TR_IO_INPUT20_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT20, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_PERI_TR_IO_INPUT20_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT20, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_PERI_TR_IO_INPUT21_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT21, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_PERI_TR_IO_INPUT21_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT21, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_PERI_TR_IO_INPUT22_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT22, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_PERI_TR_IO_INPUT22_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT22, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_PERI_TR_IO_INPUT23_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT23, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_PERI_TR_IO_INPUT23_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT23, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_PERI_TR_IO_INPUT24_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT24, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_PERI_TR_IO_INPUT24_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT24, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_PERI_TR_IO_INPUT25_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT25, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_PERI_TR_IO_INPUT25_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT25, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_PERI_TR_IO_INPUT26_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT26, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_PERI_TR_IO_INPUT26_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT26, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_PERI_TR_IO_INPUT27_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT27, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_PERI_TR_IO_INPUT27_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT27, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_SCB0_TR_I2C_SCL_FILTERED = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB0_TR_I2C_SCL_FILTERED, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_SCB1_TR_I2C_SCL_FILTERED = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB1_TR_I2C_SCL_FILTERED, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_SCB2_TR_I2C_SCL_FILTERED = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB2_TR_I2C_SCL_FILTERED, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_SCB3_TR_I2C_SCL_FILTERED = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB3_TR_I2C_SCL_FILTERED, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_SCB4_TR_I2C_SCL_FILTERED = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB4_TR_I2C_SCL_FILTERED, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_SCB5_TR_I2C_SCL_FILTERED = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB5_TR_I2C_SCL_FILTERED, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_SCB6_TR_I2C_SCL_FILTERED = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB6_TR_I2C_SCL_FILTERED, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_SCB7_TR_I2C_SCL_FILTERED = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB7_TR_I2C_SCL_FILTERED, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_SCB8_TR_I2C_SCL_FILTERED = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB8_TR_I2C_SCL_FILTERED, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_SCB0_TR_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB0_TR_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_SCB1_TR_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB1_TR_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_SCB2_TR_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB2_TR_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_SCB3_TR_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB3_TR_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_SCB4_TR_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB4_TR_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_SCB5_TR_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB5_TR_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_SCB6_TR_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB6_TR_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_SCB7_TR_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB7_TR_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_SCB8_TR_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB8_TR_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_SCB0_TR_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB0_TR_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_SCB1_TR_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB1_TR_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_SCB2_TR_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB2_TR_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_SCB3_TR_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB3_TR_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_SCB4_TR_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB4_TR_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_SCB5_TR_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB5_TR_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_SCB6_TR_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB6_TR_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_SCB7_TR_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB7_TR_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_SCB8_TR_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB8_TR_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_SMIF_TR_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SMIF_TR_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_SMIF_TR_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SMIF_TR_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_TCPWM0_TR_COMPARE_MATCH0 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_COMPARE_MATCH0, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM0_TR_COMPARE_MATCH1 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_COMPARE_MATCH1, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM0_TR_COMPARE_MATCH2 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_COMPARE_MATCH2, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM0_TR_COMPARE_MATCH3 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_COMPARE_MATCH3, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM0_TR_COMPARE_MATCH4 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_COMPARE_MATCH4, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM0_TR_COMPARE_MATCH5 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_COMPARE_MATCH5, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM0_TR_COMPARE_MATCH6 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_COMPARE_MATCH6, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM0_TR_COMPARE_MATCH7 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_COMPARE_MATCH7, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH0 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH0, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH1 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH1, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH2 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH2, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH3 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH3, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH4 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH4, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH5 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH5, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH6 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH6, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH7 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH7, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH8 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH8, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH9 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH9, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH10 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH10, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH11 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH11, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH12 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH12, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH13 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH13, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH14 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH14, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH15 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH15, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH16 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH16, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH17 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH17, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH18 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH18, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH19 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH19, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH20 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH20, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH21 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH21, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH22 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH22, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH23 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH23, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM0_TR_OVERFLOW0 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OVERFLOW0, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM0_TR_OVERFLOW1 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OVERFLOW1, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM0_TR_OVERFLOW2 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OVERFLOW2, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM0_TR_OVERFLOW3 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OVERFLOW3, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM0_TR_OVERFLOW4 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OVERFLOW4, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM0_TR_OVERFLOW5 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OVERFLOW5, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM0_TR_OVERFLOW6 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OVERFLOW6, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM0_TR_OVERFLOW7 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OVERFLOW7, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW0 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW0, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW1 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW1, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW2 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW2, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW3 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW3, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW4 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW4, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW5 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW5, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW6 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW6, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW7 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW7, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW8 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW8, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW9 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW9, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW10 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW10, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW11 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW11, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW12 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW12, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW13 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW13, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW14 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW14, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW15 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW15, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW16 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW16, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW17 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW17, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW18 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW18, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW19 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW19, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW20 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW20, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW21 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW21, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW22 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW22, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW23 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW23, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM0_TR_UNDERFLOW0 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_UNDERFLOW0, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM0_TR_UNDERFLOW1 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_UNDERFLOW1, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM0_TR_UNDERFLOW2 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_UNDERFLOW2, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM0_TR_UNDERFLOW3 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_UNDERFLOW3, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM0_TR_UNDERFLOW4 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_UNDERFLOW4, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM0_TR_UNDERFLOW5 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_UNDERFLOW5, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM0_TR_UNDERFLOW6 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_UNDERFLOW6, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM0_TR_UNDERFLOW7 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_UNDERFLOW7, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW0 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW0, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW1 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW1, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW2 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW2, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW3 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW3, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW4 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW4, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW5 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW5, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW6 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW6, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW7 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW7, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW8 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW8, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW9 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW9, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW10 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW10, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW11 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW11, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW12 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW12, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW13 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW13, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW14 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW14, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW15 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW15, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW16 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW16, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW17 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW17, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW18 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW18, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW19 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW19, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW20 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW20, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW21 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW21, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW22 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW22, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW23 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW23, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TR_GROUP10_OUTPUT0_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP10_OUTPUT0, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TR_GROUP10_OUTPUT0_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP10_OUTPUT0, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_TR_GROUP10_OUTPUT1_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP10_OUTPUT1, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TR_GROUP10_OUTPUT1_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP10_OUTPUT1, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_TR_GROUP10_OUTPUT2_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP10_OUTPUT2, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TR_GROUP10_OUTPUT2_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP10_OUTPUT2, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_TR_GROUP10_OUTPUT3_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP10_OUTPUT3, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TR_GROUP10_OUTPUT3_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP10_OUTPUT3, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_TR_GROUP10_OUTPUT4_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP10_OUTPUT4, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TR_GROUP10_OUTPUT4_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP10_OUTPUT4, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_TR_GROUP10_OUTPUT5_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP10_OUTPUT5, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TR_GROUP10_OUTPUT5_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP10_OUTPUT5, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_TR_GROUP10_OUTPUT6_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP10_OUTPUT6, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TR_GROUP10_OUTPUT6_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP10_OUTPUT6, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_TR_GROUP10_OUTPUT7_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP10_OUTPUT7, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TR_GROUP10_OUTPUT7_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP10_OUTPUT7, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_TR_GROUP11_OUTPUT0_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP11_OUTPUT0, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TR_GROUP11_OUTPUT0_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP11_OUTPUT0, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_TR_GROUP11_OUTPUT1_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP11_OUTPUT1, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TR_GROUP11_OUTPUT1_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP11_OUTPUT1, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_TR_GROUP11_OUTPUT2_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP11_OUTPUT2, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TR_GROUP11_OUTPUT2_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP11_OUTPUT2, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_TR_GROUP11_OUTPUT3_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP11_OUTPUT3, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TR_GROUP11_OUTPUT3_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP11_OUTPUT3, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_TR_GROUP11_OUTPUT4_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP11_OUTPUT4, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TR_GROUP11_OUTPUT4_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP11_OUTPUT4, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_TR_GROUP11_OUTPUT5_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP11_OUTPUT5, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TR_GROUP11_OUTPUT5_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP11_OUTPUT5, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_TR_GROUP11_OUTPUT6_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP11_OUTPUT6, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TR_GROUP11_OUTPUT6_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP11_OUTPUT6, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_TR_GROUP11_OUTPUT7_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP11_OUTPUT7, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TR_GROUP11_OUTPUT7_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP11_OUTPUT7, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_TR_GROUP11_OUTPUT8_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP11_OUTPUT8, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TR_GROUP11_OUTPUT8_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP11_OUTPUT8, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_TR_GROUP11_OUTPUT9_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP11_OUTPUT9, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TR_GROUP11_OUTPUT9_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP11_OUTPUT9, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_TR_GROUP11_OUTPUT10_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP11_OUTPUT10, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TR_GROUP11_OUTPUT10_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP11_OUTPUT10, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_TR_GROUP11_OUTPUT11_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP11_OUTPUT11, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TR_GROUP11_OUTPUT11_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP11_OUTPUT11, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_TR_GROUP11_OUTPUT12_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP11_OUTPUT12, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TR_GROUP11_OUTPUT12_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP11_OUTPUT12, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_TR_GROUP11_OUTPUT13_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP11_OUTPUT13, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TR_GROUP11_OUTPUT13_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP11_OUTPUT13, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_TR_GROUP11_OUTPUT14_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP11_OUTPUT14, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TR_GROUP11_OUTPUT14_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP11_OUTPUT14, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_TR_GROUP11_OUTPUT15_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP11_OUTPUT15, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TR_GROUP11_OUTPUT15_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP11_OUTPUT15, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_TR_GROUP12_OUTPUT0_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP12_OUTPUT0, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TR_GROUP12_OUTPUT0_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP12_OUTPUT0, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_TR_GROUP12_OUTPUT1_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP12_OUTPUT1, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TR_GROUP12_OUTPUT1_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP12_OUTPUT1, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_TR_GROUP12_OUTPUT2_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP12_OUTPUT2, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TR_GROUP12_OUTPUT2_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP12_OUTPUT2, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_TR_GROUP12_OUTPUT3_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP12_OUTPUT3, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TR_GROUP12_OUTPUT3_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP12_OUTPUT3, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_TR_GROUP12_OUTPUT4_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP12_OUTPUT4, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TR_GROUP12_OUTPUT4_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP12_OUTPUT4, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_TR_GROUP12_OUTPUT5_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP12_OUTPUT5, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TR_GROUP12_OUTPUT5_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP12_OUTPUT5, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_TR_GROUP12_OUTPUT6_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP12_OUTPUT6, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TR_GROUP12_OUTPUT6_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP12_OUTPUT6, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_TR_GROUP12_OUTPUT7_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP12_OUTPUT7, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TR_GROUP12_OUTPUT7_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP12_OUTPUT7, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_TR_GROUP12_OUTPUT8_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP12_OUTPUT8, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TR_GROUP12_OUTPUT8_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP12_OUTPUT8, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_TR_GROUP12_OUTPUT9_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP12_OUTPUT9, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TR_GROUP12_OUTPUT9_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP12_OUTPUT9, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_TR_GROUP13_OUTPUT0_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP13_OUTPUT0, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TR_GROUP13_OUTPUT0_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP13_OUTPUT0, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_TR_GROUP13_OUTPUT1_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP13_OUTPUT1, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TR_GROUP13_OUTPUT1_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP13_OUTPUT1, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_TR_GROUP13_OUTPUT2_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP13_OUTPUT2, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TR_GROUP13_OUTPUT2_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP13_OUTPUT2, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_TR_GROUP13_OUTPUT3_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP13_OUTPUT3, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TR_GROUP13_OUTPUT3_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP13_OUTPUT3, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_TR_GROUP13_OUTPUT4_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP13_OUTPUT4, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TR_GROUP13_OUTPUT4_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP13_OUTPUT4, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_TR_GROUP13_OUTPUT5_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP13_OUTPUT5, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TR_GROUP13_OUTPUT5_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP13_OUTPUT5, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_TR_GROUP13_OUTPUT6_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP13_OUTPUT6, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TR_GROUP13_OUTPUT6_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP13_OUTPUT6, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_TR_GROUP13_OUTPUT7_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP13_OUTPUT7, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TR_GROUP13_OUTPUT7_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP13_OUTPUT7, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_TR_GROUP13_OUTPUT8_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP13_OUTPUT8, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TR_GROUP13_OUTPUT8_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP13_OUTPUT8, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_TR_GROUP13_OUTPUT9_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP13_OUTPUT9, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TR_GROUP13_OUTPUT9_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP13_OUTPUT9, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_TR_GROUP13_OUTPUT10_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP13_OUTPUT10, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TR_GROUP13_OUTPUT10_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP13_OUTPUT10, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_TR_GROUP13_OUTPUT11_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP13_OUTPUT11, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TR_GROUP13_OUTPUT11_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP13_OUTPUT11, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_TR_GROUP13_OUTPUT12_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP13_OUTPUT12, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TR_GROUP13_OUTPUT12_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP13_OUTPUT12, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_TR_GROUP13_OUTPUT13_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP13_OUTPUT13, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TR_GROUP13_OUTPUT13_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP13_OUTPUT13, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_TR_GROUP13_OUTPUT14_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP13_OUTPUT14, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TR_GROUP13_OUTPUT14_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP13_OUTPUT14, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_TR_GROUP13_OUTPUT15_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP13_OUTPUT15, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TR_GROUP13_OUTPUT15_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP13_OUTPUT15, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_TR_GROUP13_OUTPUT16_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP13_OUTPUT16, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TR_GROUP13_OUTPUT16_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP13_OUTPUT16, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_TR_GROUP13_OUTPUT17_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP13_OUTPUT17, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TR_GROUP13_OUTPUT17_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP13_OUTPUT17, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_TR_GROUP14_OUTPUT0_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP14_OUTPUT0, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TR_GROUP14_OUTPUT0_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP14_OUTPUT0, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_TR_GROUP14_OUTPUT1_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP14_OUTPUT1, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TR_GROUP14_OUTPUT1_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP14_OUTPUT1, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_TR_GROUP14_OUTPUT2_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP14_OUTPUT2, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TR_GROUP14_OUTPUT2_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP14_OUTPUT2, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_TR_GROUP14_OUTPUT3_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP14_OUTPUT3, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TR_GROUP14_OUTPUT3_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP14_OUTPUT3, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_TR_GROUP14_OUTPUT4_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP14_OUTPUT4, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TR_GROUP14_OUTPUT4_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP14_OUTPUT4, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_TR_GROUP14_OUTPUT5_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP14_OUTPUT5, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TR_GROUP14_OUTPUT5_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP14_OUTPUT5, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_TR_GROUP14_OUTPUT6_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP14_OUTPUT6, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TR_GROUP14_OUTPUT6_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP14_OUTPUT6, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_TR_GROUP14_OUTPUT7_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP14_OUTPUT7, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TR_GROUP14_OUTPUT7_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP14_OUTPUT7, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_TR_GROUP14_OUTPUT8_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP14_OUTPUT8, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TR_GROUP14_OUTPUT8_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP14_OUTPUT8, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_TR_GROUP14_OUTPUT9_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP14_OUTPUT9, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TR_GROUP14_OUTPUT9_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP14_OUTPUT9, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_TR_GROUP14_OUTPUT10_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP14_OUTPUT10, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TR_GROUP14_OUTPUT10_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP14_OUTPUT10, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_TR_GROUP14_OUTPUT11_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP14_OUTPUT11, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TR_GROUP14_OUTPUT11_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP14_OUTPUT11, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_TR_GROUP14_OUTPUT12_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP14_OUTPUT12, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TR_GROUP14_OUTPUT12_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP14_OUTPUT12, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_TR_GROUP14_OUTPUT13_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP14_OUTPUT13, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TR_GROUP14_OUTPUT13_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP14_OUTPUT13, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_TR_GROUP14_OUTPUT14_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP14_OUTPUT14, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TR_GROUP14_OUTPUT14_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP14_OUTPUT14, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_TR_GROUP14_OUTPUT15_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP14_OUTPUT15, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TR_GROUP14_OUTPUT15_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP14_OUTPUT15, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_UDB_DSI_OUT_TR0_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_UDB_DSI_OUT_TR0, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_UDB_DSI_OUT_TR0_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_UDB_DSI_OUT_TR0, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_UDB_DSI_OUT_TR1_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_UDB_DSI_OUT_TR1, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_UDB_DSI_OUT_TR1_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_UDB_DSI_OUT_TR1, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_UDB_TR_UDB0_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_UDB_TR_UDB0, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_UDB_TR_UDB0_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_UDB_TR_UDB0, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_UDB_TR_UDB1_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_UDB_TR_UDB1, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_UDB_TR_UDB1_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_UDB_TR_UDB1, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_UDB_TR_UDB2_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_UDB_TR_UDB2, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_UDB_TR_UDB2_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_UDB_TR_UDB2, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_UDB_TR_UDB3_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_UDB_TR_UDB3, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_UDB_TR_UDB3_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_UDB_TR_UDB3, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_UDB_TR_UDB4_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_UDB_TR_UDB4, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_UDB_TR_UDB4_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_UDB_TR_UDB4, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_UDB_TR_UDB5_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_UDB_TR_UDB5, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_UDB_TR_UDB5_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_UDB_TR_UDB5, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_UDB_TR_UDB6_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_UDB_TR_UDB6, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_UDB_TR_UDB6_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_UDB_TR_UDB6, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_UDB_TR_UDB7_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_UDB_TR_UDB7, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_UDB_TR_UDB7_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_UDB_TR_UDB7, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_UDB_TR_UDB8_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_UDB_TR_UDB8, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_UDB_TR_UDB8_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_UDB_TR_UDB8, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_UDB_TR_UDB9_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_UDB_TR_UDB9, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_UDB_TR_UDB9_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_UDB_TR_UDB9, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_UDB_TR_UDB10_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_UDB_TR_UDB10, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_UDB_TR_UDB10_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_UDB_TR_UDB10, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_UDB_TR_UDB11_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_UDB_TR_UDB11, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_UDB_TR_UDB11_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_UDB_TR_UDB11, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_UDB_TR_UDB12_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_UDB_TR_UDB12, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_UDB_TR_UDB12_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_UDB_TR_UDB12, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_UDB_TR_UDB13_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_UDB_TR_UDB13, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_UDB_TR_UDB13_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_UDB_TR_UDB13, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_UDB_TR_UDB14_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_UDB_TR_UDB14, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_UDB_TR_UDB14_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_UDB_TR_UDB14, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_UDB_TR_UDB15_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_UDB_TR_UDB15, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_UDB_TR_UDB15_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_UDB_TR_UDB15, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_USB_DMA_REQ0 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_USB_DMA_REQ0, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_USB_DMA_REQ1 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_USB_DMA_REQ1, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_USB_DMA_REQ2 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_USB_DMA_REQ2, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_USB_DMA_REQ3 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_USB_DMA_REQ3, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_USB_DMA_REQ4 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_USB_DMA_REQ4, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_USB_DMA_REQ5 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_USB_DMA_REQ5, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_USB_DMA_REQ6 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_USB_DMA_REQ6, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_USB_DMA_REQ7 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_USB_DMA_REQ7, CYHAL_SIGNAL_TYPE_EDGE) }
	Name of each input trigger. More...
enum	cyhal_trigger_dest_psoc6_01_t {   CYHAL_TRIGGER_CPUSS_CTI_TR_IN0 = 0 ,   CYHAL_TRIGGER_CPUSS_CTI_TR_IN1 = 1 ,   CYHAL_TRIGGER_CPUSS_DW0_TR_IN0 = 2 ,   CYHAL_TRIGGER_CPUSS_DW0_TR_IN1 = 3 ,   CYHAL_TRIGGER_CPUSS_DW0_TR_IN2 = 4 ,   CYHAL_TRIGGER_CPUSS_DW0_TR_IN3 = 5 ,   CYHAL_TRIGGER_CPUSS_DW0_TR_IN4 = 6 ,   CYHAL_TRIGGER_CPUSS_DW0_TR_IN5 = 7 ,   CYHAL_TRIGGER_CPUSS_DW0_TR_IN6 = 8 ,   CYHAL_TRIGGER_CPUSS_DW0_TR_IN7 = 9 ,   CYHAL_TRIGGER_CPUSS_DW0_TR_IN8 = 10 ,   CYHAL_TRIGGER_CPUSS_DW0_TR_IN9 = 11 ,   CYHAL_TRIGGER_CPUSS_DW0_TR_IN10 = 12 ,   CYHAL_TRIGGER_CPUSS_DW0_TR_IN11 = 13 ,   CYHAL_TRIGGER_CPUSS_DW0_TR_IN12 = 14 ,   CYHAL_TRIGGER_CPUSS_DW0_TR_IN13 = 15 ,   CYHAL_TRIGGER_CPUSS_DW0_TR_IN14 = 16 ,   CYHAL_TRIGGER_CPUSS_DW0_TR_IN15 = 17 ,   CYHAL_TRIGGER_CPUSS_DW1_TR_IN0 = 18 ,   CYHAL_TRIGGER_CPUSS_DW1_TR_IN1 = 19 ,   CYHAL_TRIGGER_CPUSS_DW1_TR_IN2 = 20 ,   CYHAL_TRIGGER_CPUSS_DW1_TR_IN3 = 21 ,   CYHAL_TRIGGER_CPUSS_DW1_TR_IN4 = 22 ,   CYHAL_TRIGGER_CPUSS_DW1_TR_IN5 = 23 ,   CYHAL_TRIGGER_CPUSS_DW1_TR_IN6 = 24 ,   CYHAL_TRIGGER_CPUSS_DW1_TR_IN7 = 25 ,   CYHAL_TRIGGER_CPUSS_DW1_TR_IN8 = 26 ,   CYHAL_TRIGGER_CPUSS_DW1_TR_IN9 = 27 ,   CYHAL_TRIGGER_CPUSS_DW1_TR_IN10 = 28 ,   CYHAL_TRIGGER_CPUSS_DW1_TR_IN11 = 29 ,   CYHAL_TRIGGER_CPUSS_DW1_TR_IN12 = 30 ,   CYHAL_TRIGGER_CPUSS_DW1_TR_IN13 = 31 ,   CYHAL_TRIGGER_CPUSS_DW1_TR_IN14 = 32 ,   CYHAL_TRIGGER_CPUSS_DW1_TR_IN15 = 33 ,   CYHAL_TRIGGER_PASS_TR_SAR_IN = 34 ,   CYHAL_TRIGGER_PERI_TR_IO_OUTPUT0 = 35 ,   CYHAL_TRIGGER_PERI_TR_IO_OUTPUT1 = 36 ,   CYHAL_TRIGGER_PROFILE_TR_START = 37 ,   CYHAL_TRIGGER_PROFILE_TR_STOP = 38 ,   CYHAL_TRIGGER_TCPWM0_TR_IN0 = 39 ,   CYHAL_TRIGGER_TCPWM0_TR_IN1 = 40 ,   CYHAL_TRIGGER_TCPWM0_TR_IN2 = 41 ,   CYHAL_TRIGGER_TCPWM0_TR_IN3 = 42 ,   CYHAL_TRIGGER_TCPWM0_TR_IN4 = 43 ,   CYHAL_TRIGGER_TCPWM0_TR_IN5 = 44 ,   CYHAL_TRIGGER_TCPWM0_TR_IN6 = 45 ,   CYHAL_TRIGGER_TCPWM0_TR_IN7 = 46 ,   CYHAL_TRIGGER_TCPWM0_TR_IN8 = 47 ,   CYHAL_TRIGGER_TCPWM0_TR_IN9 = 48 ,   CYHAL_TRIGGER_TCPWM0_TR_IN10 = 49 ,   CYHAL_TRIGGER_TCPWM0_TR_IN11 = 50 ,   CYHAL_TRIGGER_TCPWM0_TR_IN12 = 51 ,   CYHAL_TRIGGER_TCPWM0_TR_IN13 = 52 ,   CYHAL_TRIGGER_TCPWM1_TR_IN0 = 53 ,   CYHAL_TRIGGER_TCPWM1_TR_IN1 = 54 ,   CYHAL_TRIGGER_TCPWM1_TR_IN2 = 55 ,   CYHAL_TRIGGER_TCPWM1_TR_IN3 = 56 ,   CYHAL_TRIGGER_TCPWM1_TR_IN4 = 57 ,   CYHAL_TRIGGER_TCPWM1_TR_IN5 = 58 ,   CYHAL_TRIGGER_TCPWM1_TR_IN6 = 59 ,   CYHAL_TRIGGER_TCPWM1_TR_IN7 = 60 ,   CYHAL_TRIGGER_TCPWM1_TR_IN8 = 61 ,   CYHAL_TRIGGER_TCPWM1_TR_IN9 = 62 ,   CYHAL_TRIGGER_TCPWM1_TR_IN10 = 63 ,   CYHAL_TRIGGER_TCPWM1_TR_IN11 = 64 ,   CYHAL_TRIGGER_TCPWM1_TR_IN12 = 65 ,   CYHAL_TRIGGER_TCPWM1_TR_IN13 = 66 ,   CYHAL_TRIGGER_TR_GROUP0_INPUT1 = 67 ,   CYHAL_TRIGGER_TR_GROUP0_INPUT2 = 68 ,   CYHAL_TRIGGER_TR_GROUP0_INPUT3 = 69 ,   CYHAL_TRIGGER_TR_GROUP0_INPUT4 = 70 ,   CYHAL_TRIGGER_TR_GROUP0_INPUT5 = 71 ,   CYHAL_TRIGGER_TR_GROUP0_INPUT6 = 72 ,   CYHAL_TRIGGER_TR_GROUP0_INPUT7 = 73 ,   CYHAL_TRIGGER_TR_GROUP0_INPUT8 = 74 ,   CYHAL_TRIGGER_TR_GROUP0_INPUT9 = 75 ,   CYHAL_TRIGGER_TR_GROUP0_INPUT10 = 76 ,   CYHAL_TRIGGER_TR_GROUP0_INPUT11 = 77 ,   CYHAL_TRIGGER_TR_GROUP0_INPUT12 = 78 ,   CYHAL_TRIGGER_TR_GROUP0_INPUT13 = 79 ,   CYHAL_TRIGGER_TR_GROUP0_INPUT14 = 80 ,   CYHAL_TRIGGER_TR_GROUP0_INPUT15 = 81 ,   CYHAL_TRIGGER_TR_GROUP0_INPUT16 = 82 ,   CYHAL_TRIGGER_TR_GROUP0_INPUT17 = 83 ,   CYHAL_TRIGGER_TR_GROUP0_INPUT18 = 84 ,   CYHAL_TRIGGER_TR_GROUP0_INPUT19 = 85 ,   CYHAL_TRIGGER_TR_GROUP0_INPUT20 = 86 ,   CYHAL_TRIGGER_TR_GROUP0_INPUT21 = 87 ,   CYHAL_TRIGGER_TR_GROUP0_INPUT22 = 88 ,   CYHAL_TRIGGER_TR_GROUP0_INPUT23 = 89 ,   CYHAL_TRIGGER_TR_GROUP0_INPUT24 = 90 ,   CYHAL_TRIGGER_TR_GROUP0_INPUT25 = 91 ,   CYHAL_TRIGGER_TR_GROUP0_INPUT26 = 92 ,   CYHAL_TRIGGER_TR_GROUP0_INPUT27 = 93 ,   CYHAL_TRIGGER_TR_GROUP0_INPUT28 = 94 ,   CYHAL_TRIGGER_TR_GROUP0_INPUT29 = 95 ,   CYHAL_TRIGGER_TR_GROUP0_INPUT30 = 96 ,   CYHAL_TRIGGER_TR_GROUP0_INPUT31 = 97 ,   CYHAL_TRIGGER_TR_GROUP0_INPUT32 = 98 ,   CYHAL_TRIGGER_TR_GROUP0_INPUT33 = 99 ,   CYHAL_TRIGGER_TR_GROUP0_INPUT34 = 100 ,   CYHAL_TRIGGER_TR_GROUP0_INPUT35 = 101 ,   CYHAL_TRIGGER_TR_GROUP0_INPUT36 = 102 ,   CYHAL_TRIGGER_TR_GROUP0_INPUT37 = 103 ,   CYHAL_TRIGGER_TR_GROUP0_INPUT38 = 104 ,   CYHAL_TRIGGER_TR_GROUP0_INPUT39 = 105 ,   CYHAL_TRIGGER_TR_GROUP0_INPUT40 = 106 ,   CYHAL_TRIGGER_TR_GROUP0_INPUT41 = 107 ,   CYHAL_TRIGGER_TR_GROUP0_INPUT42 = 108 ,   CYHAL_TRIGGER_TR_GROUP0_INPUT43 = 109 ,   CYHAL_TRIGGER_TR_GROUP0_INPUT44 = 110 ,   CYHAL_TRIGGER_TR_GROUP0_INPUT45 = 111 ,   CYHAL_TRIGGER_TR_GROUP0_INPUT46 = 112 ,   CYHAL_TRIGGER_TR_GROUP0_INPUT47 = 113 ,   CYHAL_TRIGGER_TR_GROUP0_INPUT48 = 114 ,   CYHAL_TRIGGER_TR_GROUP0_INPUT49 = 115 ,   CYHAL_TRIGGER_TR_GROUP0_INPUT50 = 116 ,   CYHAL_TRIGGER_TR_GROUP1_INPUT1 = 117 ,   CYHAL_TRIGGER_TR_GROUP1_INPUT2 = 118 ,   CYHAL_TRIGGER_TR_GROUP1_INPUT3 = 119 ,   CYHAL_TRIGGER_TR_GROUP1_INPUT4 = 120 ,   CYHAL_TRIGGER_TR_GROUP1_INPUT5 = 121 ,   CYHAL_TRIGGER_TR_GROUP1_INPUT6 = 122 ,   CYHAL_TRIGGER_TR_GROUP1_INPUT7 = 123 ,   CYHAL_TRIGGER_TR_GROUP1_INPUT8 = 124 ,   CYHAL_TRIGGER_TR_GROUP1_INPUT9 = 125 ,   CYHAL_TRIGGER_TR_GROUP1_INPUT10 = 126 ,   CYHAL_TRIGGER_TR_GROUP1_INPUT11 = 127 ,   CYHAL_TRIGGER_TR_GROUP1_INPUT12 = 128 ,   CYHAL_TRIGGER_TR_GROUP1_INPUT13 = 129 ,   CYHAL_TRIGGER_TR_GROUP1_INPUT14 = 130 ,   CYHAL_TRIGGER_TR_GROUP1_INPUT15 = 131 ,   CYHAL_TRIGGER_TR_GROUP1_INPUT16 = 132 ,   CYHAL_TRIGGER_TR_GROUP1_INPUT17 = 133 ,   CYHAL_TRIGGER_TR_GROUP1_INPUT18 = 134 ,   CYHAL_TRIGGER_TR_GROUP1_INPUT19 = 135 ,   CYHAL_TRIGGER_TR_GROUP1_INPUT20 = 136 ,   CYHAL_TRIGGER_TR_GROUP1_INPUT21 = 137 ,   CYHAL_TRIGGER_TR_GROUP1_INPUT22 = 138 ,   CYHAL_TRIGGER_TR_GROUP1_INPUT23 = 139 ,   CYHAL_TRIGGER_TR_GROUP1_INPUT24 = 140 ,   CYHAL_TRIGGER_TR_GROUP1_INPUT25 = 141 ,   CYHAL_TRIGGER_TR_GROUP1_INPUT26 = 142 ,   CYHAL_TRIGGER_TR_GROUP1_INPUT27 = 143 ,   CYHAL_TRIGGER_TR_GROUP1_INPUT28 = 144 ,   CYHAL_TRIGGER_TR_GROUP1_INPUT29 = 145 ,   CYHAL_TRIGGER_TR_GROUP1_INPUT30 = 146 ,   CYHAL_TRIGGER_TR_GROUP1_INPUT31 = 147 ,   CYHAL_TRIGGER_TR_GROUP1_INPUT32 = 148 ,   CYHAL_TRIGGER_TR_GROUP1_INPUT33 = 149 ,   CYHAL_TRIGGER_TR_GROUP1_INPUT34 = 150 ,   CYHAL_TRIGGER_TR_GROUP1_INPUT35 = 151 ,   CYHAL_TRIGGER_TR_GROUP1_INPUT36 = 152 ,   CYHAL_TRIGGER_TR_GROUP1_INPUT37 = 153 ,   CYHAL_TRIGGER_TR_GROUP1_INPUT38 = 154 ,   CYHAL_TRIGGER_TR_GROUP1_INPUT39 = 155 ,   CYHAL_TRIGGER_TR_GROUP1_INPUT40 = 156 ,   CYHAL_TRIGGER_TR_GROUP1_INPUT41 = 157 ,   CYHAL_TRIGGER_TR_GROUP1_INPUT42 = 158 ,   CYHAL_TRIGGER_TR_GROUP1_INPUT43 = 159 ,   CYHAL_TRIGGER_TR_GROUP1_INPUT44 = 160 ,   CYHAL_TRIGGER_TR_GROUP1_INPUT45 = 161 ,   CYHAL_TRIGGER_TR_GROUP1_INPUT46 = 162 ,   CYHAL_TRIGGER_TR_GROUP1_INPUT47 = 163 ,   CYHAL_TRIGGER_TR_GROUP1_INPUT48 = 164 ,   CYHAL_TRIGGER_TR_GROUP1_INPUT49 = 165 ,   CYHAL_TRIGGER_TR_GROUP1_INPUT50 = 166 ,   CYHAL_TRIGGER_TR_GROUP2_INPUT1 = 167 ,   CYHAL_TRIGGER_TR_GROUP2_INPUT2 = 168 ,   CYHAL_TRIGGER_TR_GROUP2_INPUT3 = 169 ,   CYHAL_TRIGGER_TR_GROUP2_INPUT4 = 170 ,   CYHAL_TRIGGER_TR_GROUP2_INPUT5 = 171 ,   CYHAL_TRIGGER_TR_GROUP2_INPUT6 = 172 ,   CYHAL_TRIGGER_TR_GROUP2_INPUT7 = 173 ,   CYHAL_TRIGGER_TR_GROUP2_INPUT8 = 174 ,   CYHAL_TRIGGER_TR_GROUP2_INPUT9 = 175 ,   CYHAL_TRIGGER_TR_GROUP2_INPUT10 = 176 ,   CYHAL_TRIGGER_TR_GROUP2_INPUT11 = 177 ,   CYHAL_TRIGGER_TR_GROUP2_INPUT12 = 178 ,   CYHAL_TRIGGER_TR_GROUP2_INPUT13 = 179 ,   CYHAL_TRIGGER_TR_GROUP2_INPUT14 = 180 ,   CYHAL_TRIGGER_TR_GROUP2_INPUT15 = 181 ,   CYHAL_TRIGGER_TR_GROUP2_INPUT16 = 182 ,   CYHAL_TRIGGER_TR_GROUP2_INPUT17 = 183 ,   CYHAL_TRIGGER_TR_GROUP2_INPUT18 = 184 ,   CYHAL_TRIGGER_TR_GROUP2_INPUT19 = 185 ,   CYHAL_TRIGGER_TR_GROUP2_INPUT20 = 186 ,   CYHAL_TRIGGER_TR_GROUP2_INPUT21 = 187 ,   CYHAL_TRIGGER_TR_GROUP2_INPUT22 = 188 ,   CYHAL_TRIGGER_TR_GROUP2_INPUT23 = 189 ,   CYHAL_TRIGGER_TR_GROUP2_INPUT24 = 190 ,   CYHAL_TRIGGER_TR_GROUP2_INPUT25 = 191 ,   CYHAL_TRIGGER_TR_GROUP2_INPUT26 = 192 ,   CYHAL_TRIGGER_TR_GROUP2_INPUT27 = 193 ,   CYHAL_TRIGGER_TR_GROUP2_INPUT28 = 194 ,   CYHAL_TRIGGER_TR_GROUP2_INPUT29 = 195 ,   CYHAL_TRIGGER_TR_GROUP2_INPUT30 = 196 ,   CYHAL_TRIGGER_TR_GROUP2_INPUT31 = 197 ,   CYHAL_TRIGGER_TR_GROUP2_INPUT32 = 198 ,   CYHAL_TRIGGER_TR_GROUP2_INPUT33 = 199 ,   CYHAL_TRIGGER_TR_GROUP2_INPUT34 = 200 ,   CYHAL_TRIGGER_TR_GROUP2_INPUT35 = 201 ,   CYHAL_TRIGGER_TR_GROUP2_INPUT36 = 202 ,   CYHAL_TRIGGER_TR_GROUP2_INPUT37 = 203 ,   CYHAL_TRIGGER_TR_GROUP2_INPUT38 = 204 ,   CYHAL_TRIGGER_TR_GROUP2_INPUT39 = 205 ,   CYHAL_TRIGGER_TR_GROUP2_INPUT40 = 206 ,   CYHAL_TRIGGER_TR_GROUP2_INPUT41 = 207 ,   CYHAL_TRIGGER_TR_GROUP2_INPUT42 = 208 ,   CYHAL_TRIGGER_TR_GROUP3_INPUT1 = 209 ,   CYHAL_TRIGGER_TR_GROUP3_INPUT2 = 210 ,   CYHAL_TRIGGER_TR_GROUP3_INPUT3 = 211 ,   CYHAL_TRIGGER_TR_GROUP3_INPUT4 = 212 ,   CYHAL_TRIGGER_TR_GROUP3_INPUT5 = 213 ,   CYHAL_TRIGGER_TR_GROUP3_INPUT6 = 214 ,   CYHAL_TRIGGER_TR_GROUP3_INPUT7 = 215 ,   CYHAL_TRIGGER_TR_GROUP3_INPUT8 = 216 ,   CYHAL_TRIGGER_TR_GROUP3_INPUT9 = 217 ,   CYHAL_TRIGGER_TR_GROUP3_INPUT10 = 218 ,   CYHAL_TRIGGER_TR_GROUP3_INPUT11 = 219 ,   CYHAL_TRIGGER_TR_GROUP3_INPUT12 = 220 ,   CYHAL_TRIGGER_TR_GROUP3_INPUT13 = 221 ,   CYHAL_TRIGGER_TR_GROUP3_INPUT14 = 222 ,   CYHAL_TRIGGER_TR_GROUP3_INPUT15 = 223 ,   CYHAL_TRIGGER_TR_GROUP3_INPUT16 = 224 ,   CYHAL_TRIGGER_TR_GROUP3_INPUT17 = 225 ,   CYHAL_TRIGGER_TR_GROUP3_INPUT18 = 226 ,   CYHAL_TRIGGER_TR_GROUP3_INPUT19 = 227 ,   CYHAL_TRIGGER_TR_GROUP3_INPUT20 = 228 ,   CYHAL_TRIGGER_TR_GROUP3_INPUT21 = 229 ,   CYHAL_TRIGGER_TR_GROUP3_INPUT22 = 230 ,   CYHAL_TRIGGER_TR_GROUP3_INPUT23 = 231 ,   CYHAL_TRIGGER_TR_GROUP3_INPUT24 = 232 ,   CYHAL_TRIGGER_TR_GROUP3_INPUT25 = 233 ,   CYHAL_TRIGGER_TR_GROUP3_INPUT26 = 234 ,   CYHAL_TRIGGER_TR_GROUP3_INPUT27 = 235 ,   CYHAL_TRIGGER_TR_GROUP3_INPUT28 = 236 ,   CYHAL_TRIGGER_TR_GROUP3_INPUT29 = 237 ,   CYHAL_TRIGGER_TR_GROUP3_INPUT30 = 238 ,   CYHAL_TRIGGER_TR_GROUP3_INPUT31 = 239 ,   CYHAL_TRIGGER_TR_GROUP3_INPUT32 = 240 ,   CYHAL_TRIGGER_TR_GROUP3_INPUT33 = 241 ,   CYHAL_TRIGGER_TR_GROUP3_INPUT34 = 242 ,   CYHAL_TRIGGER_TR_GROUP3_INPUT35 = 243 ,   CYHAL_TRIGGER_TR_GROUP3_INPUT36 = 244 ,   CYHAL_TRIGGER_TR_GROUP3_INPUT37 = 245 ,   CYHAL_TRIGGER_TR_GROUP3_INPUT38 = 246 ,   CYHAL_TRIGGER_TR_GROUP3_INPUT39 = 247 ,   CYHAL_TRIGGER_TR_GROUP3_INPUT40 = 248 ,   CYHAL_TRIGGER_TR_GROUP3_INPUT41 = 249 ,   CYHAL_TRIGGER_TR_GROUP3_INPUT42 = 250 ,   CYHAL_TRIGGER_TR_GROUP4_INPUT1 = 251 ,   CYHAL_TRIGGER_TR_GROUP4_INPUT2 = 252 ,   CYHAL_TRIGGER_TR_GROUP4_INPUT3 = 253 ,   CYHAL_TRIGGER_TR_GROUP4_INPUT4 = 254 ,   CYHAL_TRIGGER_TR_GROUP4_INPUT5 = 255 ,   CYHAL_TRIGGER_TR_GROUP4_INPUT6 = 256 ,   CYHAL_TRIGGER_TR_GROUP4_INPUT7 = 257 ,   CYHAL_TRIGGER_TR_GROUP4_INPUT8 = 258 ,   CYHAL_TRIGGER_TR_GROUP4_INPUT9 = 259 ,   CYHAL_TRIGGER_TR_GROUP4_INPUT10 = 260 ,   CYHAL_TRIGGER_TR_GROUP4_INPUT11 = 261 ,   CYHAL_TRIGGER_TR_GROUP4_INPUT12 = 262 ,   CYHAL_TRIGGER_TR_GROUP4_INPUT13 = 263 ,   CYHAL_TRIGGER_TR_GROUP4_INPUT14 = 264 ,   CYHAL_TRIGGER_TR_GROUP4_INPUT15 = 265 ,   CYHAL_TRIGGER_TR_GROUP4_INPUT16 = 266 ,   CYHAL_TRIGGER_TR_GROUP4_INPUT17 = 267 ,   CYHAL_TRIGGER_TR_GROUP4_INPUT18 = 268 ,   CYHAL_TRIGGER_TR_GROUP4_INPUT19 = 269 ,   CYHAL_TRIGGER_TR_GROUP4_INPUT20 = 270 ,   CYHAL_TRIGGER_TR_GROUP4_INPUT21 = 271 ,   CYHAL_TRIGGER_TR_GROUP4_INPUT22 = 272 ,   CYHAL_TRIGGER_TR_GROUP4_INPUT23 = 273 ,   CYHAL_TRIGGER_TR_GROUP4_INPUT24 = 274 ,   CYHAL_TRIGGER_TR_GROUP4_INPUT25 = 275 ,   CYHAL_TRIGGER_TR_GROUP4_INPUT26 = 276 ,   CYHAL_TRIGGER_TR_GROUP4_INPUT27 = 277 ,   CYHAL_TRIGGER_TR_GROUP4_INPUT28 = 278 ,   CYHAL_TRIGGER_TR_GROUP4_INPUT29 = 279 ,   CYHAL_TRIGGER_TR_GROUP4_INPUT30 = 280 ,   CYHAL_TRIGGER_TR_GROUP4_INPUT31 = 281 ,   CYHAL_TRIGGER_TR_GROUP4_INPUT32 = 282 ,   CYHAL_TRIGGER_TR_GROUP4_INPUT33 = 283 ,   CYHAL_TRIGGER_TR_GROUP4_INPUT34 = 284 ,   CYHAL_TRIGGER_TR_GROUP4_INPUT35 = 285 ,   CYHAL_TRIGGER_TR_GROUP4_INPUT36 = 286 ,   CYHAL_TRIGGER_TR_GROUP4_INPUT37 = 287 ,   CYHAL_TRIGGER_TR_GROUP4_INPUT38 = 288 ,   CYHAL_TRIGGER_TR_GROUP4_INPUT39 = 289 ,   CYHAL_TRIGGER_TR_GROUP4_INPUT40 = 290 ,   CYHAL_TRIGGER_TR_GROUP4_INPUT41 = 291 ,   CYHAL_TRIGGER_TR_GROUP4_INPUT42 = 292 ,   CYHAL_TRIGGER_TR_GROUP5_INPUT1 = 293 ,   CYHAL_TRIGGER_TR_GROUP5_INPUT2 = 294 ,   CYHAL_TRIGGER_TR_GROUP5_INPUT3 = 295 ,   CYHAL_TRIGGER_TR_GROUP5_INPUT4 = 296 ,   CYHAL_TRIGGER_TR_GROUP5_INPUT5 = 297 ,   CYHAL_TRIGGER_TR_GROUP5_INPUT6 = 298 ,   CYHAL_TRIGGER_TR_GROUP5_INPUT7 = 299 ,   CYHAL_TRIGGER_TR_GROUP5_INPUT8 = 300 ,   CYHAL_TRIGGER_TR_GROUP5_INPUT9 = 301 ,   CYHAL_TRIGGER_TR_GROUP5_INPUT10 = 302 ,   CYHAL_TRIGGER_TR_GROUP5_INPUT11 = 303 ,   CYHAL_TRIGGER_TR_GROUP5_INPUT12 = 304 ,   CYHAL_TRIGGER_TR_GROUP5_INPUT13 = 305 ,   CYHAL_TRIGGER_TR_GROUP5_INPUT14 = 306 ,   CYHAL_TRIGGER_TR_GROUP5_INPUT15 = 307 ,   CYHAL_TRIGGER_TR_GROUP5_INPUT16 = 308 ,   CYHAL_TRIGGER_TR_GROUP5_INPUT17 = 309 ,   CYHAL_TRIGGER_TR_GROUP5_INPUT18 = 310 ,   CYHAL_TRIGGER_TR_GROUP5_INPUT19 = 311 ,   CYHAL_TRIGGER_TR_GROUP5_INPUT20 = 312 ,   CYHAL_TRIGGER_TR_GROUP5_INPUT21 = 313 ,   CYHAL_TRIGGER_TR_GROUP5_INPUT22 = 314 ,   CYHAL_TRIGGER_TR_GROUP5_INPUT23 = 315 ,   CYHAL_TRIGGER_TR_GROUP5_INPUT24 = 316 ,   CYHAL_TRIGGER_TR_GROUP5_INPUT25 = 317 ,   CYHAL_TRIGGER_TR_GROUP5_INPUT26 = 318 ,   CYHAL_TRIGGER_TR_GROUP5_INPUT27 = 319 ,   CYHAL_TRIGGER_TR_GROUP5_INPUT28 = 320 ,   CYHAL_TRIGGER_TR_GROUP5_INPUT29 = 321 ,   CYHAL_TRIGGER_TR_GROUP5_INPUT30 = 322 ,   CYHAL_TRIGGER_TR_GROUP5_INPUT31 = 323 ,   CYHAL_TRIGGER_TR_GROUP5_INPUT32 = 324 ,   CYHAL_TRIGGER_TR_GROUP5_INPUT33 = 325 ,   CYHAL_TRIGGER_TR_GROUP5_INPUT34 = 326 ,   CYHAL_TRIGGER_TR_GROUP5_INPUT35 = 327 ,   CYHAL_TRIGGER_TR_GROUP5_INPUT36 = 328 ,   CYHAL_TRIGGER_TR_GROUP5_INPUT37 = 329 ,   CYHAL_TRIGGER_TR_GROUP5_INPUT38 = 330 ,   CYHAL_TRIGGER_TR_GROUP5_INPUT39 = 331 ,   CYHAL_TRIGGER_TR_GROUP5_INPUT40 = 332 ,   CYHAL_TRIGGER_TR_GROUP5_INPUT41 = 333 ,   CYHAL_TRIGGER_TR_GROUP5_INPUT42 = 334 ,   CYHAL_TRIGGER_TR_GROUP6_INPUT1 = 335 ,   CYHAL_TRIGGER_TR_GROUP6_INPUT2 = 336 ,   CYHAL_TRIGGER_TR_GROUP6_INPUT3 = 337 ,   CYHAL_TRIGGER_TR_GROUP6_INPUT4 = 338 ,   CYHAL_TRIGGER_TR_GROUP6_INPUT5 = 339 ,   CYHAL_TRIGGER_TR_GROUP6_INPUT6 = 340 ,   CYHAL_TRIGGER_TR_GROUP6_INPUT7 = 341 ,   CYHAL_TRIGGER_TR_GROUP6_INPUT8 = 342 ,   CYHAL_TRIGGER_TR_GROUP6_INPUT9 = 343 ,   CYHAL_TRIGGER_TR_GROUP6_INPUT10 = 344 ,   CYHAL_TRIGGER_TR_GROUP6_INPUT11 = 345 ,   CYHAL_TRIGGER_TR_GROUP6_INPUT12 = 346 ,   CYHAL_TRIGGER_TR_GROUP6_INPUT13 = 347 ,   CYHAL_TRIGGER_TR_GROUP6_INPUT14 = 348 ,   CYHAL_TRIGGER_TR_GROUP6_INPUT15 = 349 ,   CYHAL_TRIGGER_TR_GROUP6_INPUT16 = 350 ,   CYHAL_TRIGGER_TR_GROUP6_INPUT17 = 351 ,   CYHAL_TRIGGER_TR_GROUP6_INPUT18 = 352 ,   CYHAL_TRIGGER_TR_GROUP6_INPUT19 = 353 ,   CYHAL_TRIGGER_TR_GROUP6_INPUT20 = 354 ,   CYHAL_TRIGGER_TR_GROUP6_INPUT21 = 355 ,   CYHAL_TRIGGER_TR_GROUP6_INPUT22 = 356 ,   CYHAL_TRIGGER_TR_GROUP6_INPUT23 = 357 ,   CYHAL_TRIGGER_TR_GROUP6_INPUT24 = 358 ,   CYHAL_TRIGGER_TR_GROUP6_INPUT25 = 359 ,   CYHAL_TRIGGER_TR_GROUP6_INPUT26 = 360 ,   CYHAL_TRIGGER_TR_GROUP6_INPUT27 = 361 ,   CYHAL_TRIGGER_TR_GROUP6_INPUT28 = 362 ,   CYHAL_TRIGGER_TR_GROUP6_INPUT29 = 363 ,   CYHAL_TRIGGER_TR_GROUP6_INPUT30 = 364 ,   CYHAL_TRIGGER_TR_GROUP6_INPUT31 = 365 ,   CYHAL_TRIGGER_TR_GROUP6_INPUT32 = 366 ,   CYHAL_TRIGGER_TR_GROUP6_INPUT33 = 367 ,   CYHAL_TRIGGER_TR_GROUP6_INPUT34 = 368 ,   CYHAL_TRIGGER_TR_GROUP6_INPUT35 = 369 ,   CYHAL_TRIGGER_TR_GROUP6_INPUT36 = 370 ,   CYHAL_TRIGGER_TR_GROUP6_INPUT37 = 371 ,   CYHAL_TRIGGER_TR_GROUP6_INPUT38 = 372 ,   CYHAL_TRIGGER_TR_GROUP6_INPUT39 = 373 ,   CYHAL_TRIGGER_TR_GROUP6_INPUT40 = 374 ,   CYHAL_TRIGGER_TR_GROUP6_INPUT41 = 375 ,   CYHAL_TRIGGER_TR_GROUP6_INPUT42 = 376 ,   CYHAL_TRIGGER_TR_GROUP7_INPUT1 = 377 ,   CYHAL_TRIGGER_TR_GROUP7_INPUT2 = 378 ,   CYHAL_TRIGGER_TR_GROUP7_INPUT3 = 379 ,   CYHAL_TRIGGER_TR_GROUP7_INPUT4 = 380 ,   CYHAL_TRIGGER_TR_GROUP7_INPUT5 = 381 ,   CYHAL_TRIGGER_TR_GROUP7_INPUT6 = 382 ,   CYHAL_TRIGGER_TR_GROUP7_INPUT7 = 383 ,   CYHAL_TRIGGER_TR_GROUP7_INPUT8 = 384 ,   CYHAL_TRIGGER_TR_GROUP7_INPUT9 = 385 ,   CYHAL_TRIGGER_TR_GROUP7_INPUT10 = 386 ,   CYHAL_TRIGGER_TR_GROUP7_INPUT11 = 387 ,   CYHAL_TRIGGER_TR_GROUP7_INPUT12 = 388 ,   CYHAL_TRIGGER_TR_GROUP7_INPUT13 = 389 ,   CYHAL_TRIGGER_TR_GROUP7_INPUT14 = 390 ,   CYHAL_TRIGGER_TR_GROUP7_INPUT15 = 391 ,   CYHAL_TRIGGER_TR_GROUP7_INPUT16 = 392 ,   CYHAL_TRIGGER_TR_GROUP7_INPUT17 = 393 ,   CYHAL_TRIGGER_TR_GROUP7_INPUT18 = 394 ,   CYHAL_TRIGGER_TR_GROUP7_INPUT19 = 395 ,   CYHAL_TRIGGER_TR_GROUP7_INPUT20 = 396 ,   CYHAL_TRIGGER_TR_GROUP7_INPUT21 = 397 ,   CYHAL_TRIGGER_TR_GROUP7_INPUT22 = 398 ,   CYHAL_TRIGGER_TR_GROUP7_INPUT23 = 399 ,   CYHAL_TRIGGER_TR_GROUP7_INPUT24 = 400 ,   CYHAL_TRIGGER_TR_GROUP7_INPUT25 = 401 ,   CYHAL_TRIGGER_TR_GROUP7_INPUT26 = 402 ,   CYHAL_TRIGGER_TR_GROUP7_INPUT27 = 403 ,   CYHAL_TRIGGER_TR_GROUP7_INPUT28 = 404 ,   CYHAL_TRIGGER_TR_GROUP7_INPUT29 = 405 ,   CYHAL_TRIGGER_TR_GROUP7_INPUT30 = 406 ,   CYHAL_TRIGGER_TR_GROUP7_INPUT31 = 407 ,   CYHAL_TRIGGER_TR_GROUP7_INPUT32 = 408 ,   CYHAL_TRIGGER_TR_GROUP7_INPUT33 = 409 ,   CYHAL_TRIGGER_TR_GROUP7_INPUT34 = 410 ,   CYHAL_TRIGGER_TR_GROUP7_INPUT35 = 411 ,   CYHAL_TRIGGER_TR_GROUP7_INPUT36 = 412 ,   CYHAL_TRIGGER_TR_GROUP7_INPUT37 = 413 ,   CYHAL_TRIGGER_TR_GROUP7_INPUT38 = 414 ,   CYHAL_TRIGGER_TR_GROUP7_INPUT39 = 415 ,   CYHAL_TRIGGER_TR_GROUP7_INPUT40 = 416 ,   CYHAL_TRIGGER_TR_GROUP7_INPUT41 = 417 ,   CYHAL_TRIGGER_TR_GROUP7_INPUT42 = 418 ,   CYHAL_TRIGGER_TR_GROUP8_INPUT1 = 419 ,   CYHAL_TRIGGER_TR_GROUP8_INPUT2 = 420 ,   CYHAL_TRIGGER_TR_GROUP8_INPUT3 = 421 ,   CYHAL_TRIGGER_TR_GROUP8_INPUT4 = 422 ,   CYHAL_TRIGGER_TR_GROUP8_INPUT5 = 423 ,   CYHAL_TRIGGER_TR_GROUP8_INPUT6 = 424 ,   CYHAL_TRIGGER_TR_GROUP8_INPUT7 = 425 ,   CYHAL_TRIGGER_TR_GROUP8_INPUT8 = 426 ,   CYHAL_TRIGGER_TR_GROUP8_INPUT9 = 427 ,   CYHAL_TRIGGER_TR_GROUP8_INPUT10 = 428 ,   CYHAL_TRIGGER_TR_GROUP8_INPUT11 = 429 ,   CYHAL_TRIGGER_TR_GROUP8_INPUT12 = 430 ,   CYHAL_TRIGGER_TR_GROUP8_INPUT13 = 431 ,   CYHAL_TRIGGER_TR_GROUP8_INPUT14 = 432 ,   CYHAL_TRIGGER_TR_GROUP8_INPUT15 = 433 ,   CYHAL_TRIGGER_TR_GROUP8_INPUT16 = 434 ,   CYHAL_TRIGGER_TR_GROUP8_INPUT17 = 435 ,   CYHAL_TRIGGER_TR_GROUP8_INPUT18 = 436 ,   CYHAL_TRIGGER_TR_GROUP8_INPUT19 = 437 ,   CYHAL_TRIGGER_TR_GROUP8_INPUT20 = 438 ,   CYHAL_TRIGGER_TR_GROUP8_INPUT21 = 439 ,   CYHAL_TRIGGER_TR_GROUP8_INPUT22 = 440 ,   CYHAL_TRIGGER_TR_GROUP8_INPUT23 = 441 ,   CYHAL_TRIGGER_TR_GROUP8_INPUT24 = 442 ,   CYHAL_TRIGGER_TR_GROUP8_INPUT25 = 443 ,   CYHAL_TRIGGER_TR_GROUP8_INPUT26 = 444 ,   CYHAL_TRIGGER_TR_GROUP8_INPUT27 = 445 ,   CYHAL_TRIGGER_TR_GROUP8_INPUT28 = 446 ,   CYHAL_TRIGGER_TR_GROUP8_INPUT29 = 447 ,   CYHAL_TRIGGER_TR_GROUP8_INPUT30 = 448 ,   CYHAL_TRIGGER_TR_GROUP8_INPUT31 = 449 ,   CYHAL_TRIGGER_TR_GROUP8_INPUT32 = 450 ,   CYHAL_TRIGGER_TR_GROUP8_INPUT33 = 451 ,   CYHAL_TRIGGER_TR_GROUP8_INPUT34 = 452 ,   CYHAL_TRIGGER_TR_GROUP8_INPUT35 = 453 ,   CYHAL_TRIGGER_TR_GROUP8_INPUT36 = 454 ,   CYHAL_TRIGGER_TR_GROUP8_INPUT37 = 455 ,   CYHAL_TRIGGER_TR_GROUP8_INPUT38 = 456 ,   CYHAL_TRIGGER_TR_GROUP8_INPUT39 = 457 ,   CYHAL_TRIGGER_TR_GROUP8_INPUT40 = 458 ,   CYHAL_TRIGGER_TR_GROUP8_INPUT41 = 459 ,   CYHAL_TRIGGER_TR_GROUP8_INPUT42 = 460 ,   CYHAL_TRIGGER_UDB_TR_DW_ACK0 = 461 ,   CYHAL_TRIGGER_UDB_TR_DW_ACK1 = 462 ,   CYHAL_TRIGGER_UDB_TR_DW_ACK2 = 463 ,   CYHAL_TRIGGER_UDB_TR_DW_ACK3 = 464 ,   CYHAL_TRIGGER_UDB_TR_DW_ACK4 = 465 ,   CYHAL_TRIGGER_UDB_TR_DW_ACK5 = 466 ,   CYHAL_TRIGGER_UDB_TR_DW_ACK6 = 467 ,   CYHAL_TRIGGER_UDB_TR_DW_ACK7 = 468 ,   CYHAL_TRIGGER_UDB_TR_IN0 = 469 ,   CYHAL_TRIGGER_UDB_TR_IN1 = 470 ,   CYHAL_TRIGGER_USB_DMA_BURSTEND0 = 471 ,   CYHAL_TRIGGER_USB_DMA_BURSTEND1 = 472 ,   CYHAL_TRIGGER_USB_DMA_BURSTEND2 = 473 ,   CYHAL_TRIGGER_USB_DMA_BURSTEND3 = 474 ,   CYHAL_TRIGGER_USB_DMA_BURSTEND4 = 475 ,   CYHAL_TRIGGER_USB_DMA_BURSTEND5 = 476 ,   CYHAL_TRIGGER_USB_DMA_BURSTEND6 = 477 ,   CYHAL_TRIGGER_USB_DMA_BURSTEND7 = 478 }
	Name of each output trigger. More...

Macro Definition Documentation

CYHAL_TRIGGER_CPUSS_ZERO

#define CYHAL_TRIGGER_CPUSS_ZERO   (CYHAL_TRIGGER_CPUSS_ZERO_LEVEL)

Deprecated defines for signals that can be either level or edge.

Legacy define. Instead, use the explicit _LEVEL or _EDGE version.

Enumeration Type Documentation

cyhal_trigger_source_psoc6_01_t

enum cyhal_trigger_source_psoc6_01_t

Name of each input trigger.

Enumerator
CYHAL_TRIGGER_CPUSS_ZERO_EDGE	cpuss.zero
CYHAL_TRIGGER_CPUSS_ZERO_LEVEL	cpuss.zero
CYHAL_TRIGGER_AUDIOSS_TR_I2S_RX_REQ	audioss.tr_i2s_rx_req
CYHAL_TRIGGER_AUDIOSS_TR_I2S_TX_REQ	audioss.tr_i2s_tx_req
CYHAL_TRIGGER_AUDIOSS_TR_PDM_RX_REQ	audioss.tr_pdm_rx_req
CYHAL_TRIGGER_CPUSS_CTI_TR_OUT0	cpuss.cti_tr_out[0]
CYHAL_TRIGGER_CPUSS_CTI_TR_OUT1	cpuss.cti_tr_out[1]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT0	cpuss.dw0_tr_out[0]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT1	cpuss.dw0_tr_out[1]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT2	cpuss.dw0_tr_out[2]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT3	cpuss.dw0_tr_out[3]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT4	cpuss.dw0_tr_out[4]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT5	cpuss.dw0_tr_out[5]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT6	cpuss.dw0_tr_out[6]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT7	cpuss.dw0_tr_out[7]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT8	cpuss.dw0_tr_out[8]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT9	cpuss.dw0_tr_out[9]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT10	cpuss.dw0_tr_out[10]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT11	cpuss.dw0_tr_out[11]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT12	cpuss.dw0_tr_out[12]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT13	cpuss.dw0_tr_out[13]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT14	cpuss.dw0_tr_out[14]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT15	cpuss.dw0_tr_out[15]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT0	cpuss.dw1_tr_out[0]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT1	cpuss.dw1_tr_out[1]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT2	cpuss.dw1_tr_out[2]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT3	cpuss.dw1_tr_out[3]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT4	cpuss.dw1_tr_out[4]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT5	cpuss.dw1_tr_out[5]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT6	cpuss.dw1_tr_out[6]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT7	cpuss.dw1_tr_out[7]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT8	cpuss.dw1_tr_out[8]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT9	cpuss.dw1_tr_out[9]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT10	cpuss.dw1_tr_out[10]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT11	cpuss.dw1_tr_out[11]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT12	cpuss.dw1_tr_out[12]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT13	cpuss.dw1_tr_out[13]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT14	cpuss.dw1_tr_out[14]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT15	cpuss.dw1_tr_out[15]
CYHAL_TRIGGER_CPUSS_TR_FAULT0	cpuss.tr_fault[0]
CYHAL_TRIGGER_CPUSS_TR_FAULT1	cpuss.tr_fault[1]
CYHAL_TRIGGER_CSD_DSI_SENSE_OUT_EDGE	csd.dsi_sense_out
CYHAL_TRIGGER_CSD_DSI_SENSE_OUT_LEVEL	csd.dsi_sense_out
CYHAL_TRIGGER_CSD_TR_ADC_DONE_EDGE	csd.tr_adc_done
CYHAL_TRIGGER_CSD_TR_ADC_DONE_LEVEL	csd.tr_adc_done
CYHAL_TRIGGER_LPCOMP_DSI_COMP0	lpcomp.dsi_comp0
CYHAL_TRIGGER_LPCOMP_DSI_COMP1	lpcomp.dsi_comp1
CYHAL_TRIGGER_PASS_DSI_CTB_CMP0_EDGE	pass.dsi_ctb_cmp0
CYHAL_TRIGGER_PASS_DSI_CTB_CMP0_LEVEL	pass.dsi_ctb_cmp0
CYHAL_TRIGGER_PASS_DSI_CTB_CMP1_EDGE	pass.dsi_ctb_cmp1
CYHAL_TRIGGER_PASS_DSI_CTB_CMP1_LEVEL	pass.dsi_ctb_cmp1
CYHAL_TRIGGER_PASS_TR_CTDAC_EMPTY	pass.tr_ctdac_empty
CYHAL_TRIGGER_PASS_TR_SAR_OUT	pass.tr_sar_out
CYHAL_TRIGGER_PERI_TR_IO_INPUT0_EDGE	peri.tr_io_input[0]
CYHAL_TRIGGER_PERI_TR_IO_INPUT0_LEVEL	peri.tr_io_input[0]
CYHAL_TRIGGER_PERI_TR_IO_INPUT1_EDGE	peri.tr_io_input[1]
CYHAL_TRIGGER_PERI_TR_IO_INPUT1_LEVEL	peri.tr_io_input[1]
CYHAL_TRIGGER_PERI_TR_IO_INPUT2_EDGE	peri.tr_io_input[2]
CYHAL_TRIGGER_PERI_TR_IO_INPUT2_LEVEL	peri.tr_io_input[2]
CYHAL_TRIGGER_PERI_TR_IO_INPUT3_EDGE	peri.tr_io_input[3]
CYHAL_TRIGGER_PERI_TR_IO_INPUT3_LEVEL	peri.tr_io_input[3]
CYHAL_TRIGGER_PERI_TR_IO_INPUT4_EDGE	peri.tr_io_input[4]
CYHAL_TRIGGER_PERI_TR_IO_INPUT4_LEVEL	peri.tr_io_input[4]
CYHAL_TRIGGER_PERI_TR_IO_INPUT5_EDGE	peri.tr_io_input[5]
CYHAL_TRIGGER_PERI_TR_IO_INPUT5_LEVEL	peri.tr_io_input[5]
CYHAL_TRIGGER_PERI_TR_IO_INPUT6_EDGE	peri.tr_io_input[6]
CYHAL_TRIGGER_PERI_TR_IO_INPUT6_LEVEL	peri.tr_io_input[6]
CYHAL_TRIGGER_PERI_TR_IO_INPUT7_EDGE	peri.tr_io_input[7]
CYHAL_TRIGGER_PERI_TR_IO_INPUT7_LEVEL	peri.tr_io_input[7]
CYHAL_TRIGGER_PERI_TR_IO_INPUT8_EDGE	peri.tr_io_input[8]
CYHAL_TRIGGER_PERI_TR_IO_INPUT8_LEVEL	peri.tr_io_input[8]
CYHAL_TRIGGER_PERI_TR_IO_INPUT9_EDGE	peri.tr_io_input[9]
CYHAL_TRIGGER_PERI_TR_IO_INPUT9_LEVEL	peri.tr_io_input[9]
CYHAL_TRIGGER_PERI_TR_IO_INPUT10_EDGE	peri.tr_io_input[10]
CYHAL_TRIGGER_PERI_TR_IO_INPUT10_LEVEL	peri.tr_io_input[10]
CYHAL_TRIGGER_PERI_TR_IO_INPUT11_EDGE	peri.tr_io_input[11]
CYHAL_TRIGGER_PERI_TR_IO_INPUT11_LEVEL	peri.tr_io_input[11]
CYHAL_TRIGGER_PERI_TR_IO_INPUT12_EDGE	peri.tr_io_input[12]
CYHAL_TRIGGER_PERI_TR_IO_INPUT12_LEVEL	peri.tr_io_input[12]
CYHAL_TRIGGER_PERI_TR_IO_INPUT13_EDGE	peri.tr_io_input[13]
CYHAL_TRIGGER_PERI_TR_IO_INPUT13_LEVEL	peri.tr_io_input[13]
CYHAL_TRIGGER_PERI_TR_IO_INPUT14_EDGE	peri.tr_io_input[14]
CYHAL_TRIGGER_PERI_TR_IO_INPUT14_LEVEL	peri.tr_io_input[14]
CYHAL_TRIGGER_PERI_TR_IO_INPUT15_EDGE	peri.tr_io_input[15]
CYHAL_TRIGGER_PERI_TR_IO_INPUT15_LEVEL	peri.tr_io_input[15]
CYHAL_TRIGGER_PERI_TR_IO_INPUT16_EDGE	peri.tr_io_input[16]
CYHAL_TRIGGER_PERI_TR_IO_INPUT16_LEVEL	peri.tr_io_input[16]
CYHAL_TRIGGER_PERI_TR_IO_INPUT17_EDGE	peri.tr_io_input[17]
CYHAL_TRIGGER_PERI_TR_IO_INPUT17_LEVEL	peri.tr_io_input[17]
CYHAL_TRIGGER_PERI_TR_IO_INPUT18_EDGE	peri.tr_io_input[18]
CYHAL_TRIGGER_PERI_TR_IO_INPUT18_LEVEL	peri.tr_io_input[18]
CYHAL_TRIGGER_PERI_TR_IO_INPUT19_EDGE	peri.tr_io_input[19]
CYHAL_TRIGGER_PERI_TR_IO_INPUT19_LEVEL	peri.tr_io_input[19]
CYHAL_TRIGGER_PERI_TR_IO_INPUT20_EDGE	peri.tr_io_input[20]
CYHAL_TRIGGER_PERI_TR_IO_INPUT20_LEVEL	peri.tr_io_input[20]
CYHAL_TRIGGER_PERI_TR_IO_INPUT21_EDGE	peri.tr_io_input[21]
CYHAL_TRIGGER_PERI_TR_IO_INPUT21_LEVEL	peri.tr_io_input[21]
CYHAL_TRIGGER_PERI_TR_IO_INPUT22_EDGE	peri.tr_io_input[22]
CYHAL_TRIGGER_PERI_TR_IO_INPUT22_LEVEL	peri.tr_io_input[22]
CYHAL_TRIGGER_PERI_TR_IO_INPUT23_EDGE	peri.tr_io_input[23]
CYHAL_TRIGGER_PERI_TR_IO_INPUT23_LEVEL	peri.tr_io_input[23]
CYHAL_TRIGGER_PERI_TR_IO_INPUT24_EDGE	peri.tr_io_input[24]
CYHAL_TRIGGER_PERI_TR_IO_INPUT24_LEVEL	peri.tr_io_input[24]
CYHAL_TRIGGER_PERI_TR_IO_INPUT25_EDGE	peri.tr_io_input[25]
CYHAL_TRIGGER_PERI_TR_IO_INPUT25_LEVEL	peri.tr_io_input[25]
CYHAL_TRIGGER_PERI_TR_IO_INPUT26_EDGE	peri.tr_io_input[26]
CYHAL_TRIGGER_PERI_TR_IO_INPUT26_LEVEL	peri.tr_io_input[26]
CYHAL_TRIGGER_PERI_TR_IO_INPUT27_EDGE	peri.tr_io_input[27]
CYHAL_TRIGGER_PERI_TR_IO_INPUT27_LEVEL	peri.tr_io_input[27]
CYHAL_TRIGGER_SCB0_TR_I2C_SCL_FILTERED	scb[0].tr_i2c_scl_filtered
CYHAL_TRIGGER_SCB1_TR_I2C_SCL_FILTERED	scb[1].tr_i2c_scl_filtered
CYHAL_TRIGGER_SCB2_TR_I2C_SCL_FILTERED	scb[2].tr_i2c_scl_filtered
CYHAL_TRIGGER_SCB3_TR_I2C_SCL_FILTERED	scb[3].tr_i2c_scl_filtered
CYHAL_TRIGGER_SCB4_TR_I2C_SCL_FILTERED	scb[4].tr_i2c_scl_filtered
CYHAL_TRIGGER_SCB5_TR_I2C_SCL_FILTERED	scb[5].tr_i2c_scl_filtered
CYHAL_TRIGGER_SCB6_TR_I2C_SCL_FILTERED	scb[6].tr_i2c_scl_filtered
CYHAL_TRIGGER_SCB7_TR_I2C_SCL_FILTERED	scb[7].tr_i2c_scl_filtered
CYHAL_TRIGGER_SCB8_TR_I2C_SCL_FILTERED	scb[8].tr_i2c_scl_filtered
CYHAL_TRIGGER_SCB0_TR_RX_REQ	scb[0].tr_rx_req
CYHAL_TRIGGER_SCB1_TR_RX_REQ	scb[1].tr_rx_req
CYHAL_TRIGGER_SCB2_TR_RX_REQ	scb[2].tr_rx_req
CYHAL_TRIGGER_SCB3_TR_RX_REQ	scb[3].tr_rx_req
CYHAL_TRIGGER_SCB4_TR_RX_REQ	scb[4].tr_rx_req
CYHAL_TRIGGER_SCB5_TR_RX_REQ	scb[5].tr_rx_req
CYHAL_TRIGGER_SCB6_TR_RX_REQ	scb[6].tr_rx_req
CYHAL_TRIGGER_SCB7_TR_RX_REQ	scb[7].tr_rx_req
CYHAL_TRIGGER_SCB8_TR_RX_REQ	scb[8].tr_rx_req
CYHAL_TRIGGER_SCB0_TR_TX_REQ	scb[0].tr_tx_req
CYHAL_TRIGGER_SCB1_TR_TX_REQ	scb[1].tr_tx_req
CYHAL_TRIGGER_SCB2_TR_TX_REQ	scb[2].tr_tx_req
CYHAL_TRIGGER_SCB3_TR_TX_REQ	scb[3].tr_tx_req
CYHAL_TRIGGER_SCB4_TR_TX_REQ	scb[4].tr_tx_req
CYHAL_TRIGGER_SCB5_TR_TX_REQ	scb[5].tr_tx_req
CYHAL_TRIGGER_SCB6_TR_TX_REQ	scb[6].tr_tx_req
CYHAL_TRIGGER_SCB7_TR_TX_REQ	scb[7].tr_tx_req
CYHAL_TRIGGER_SCB8_TR_TX_REQ	scb[8].tr_tx_req
CYHAL_TRIGGER_SMIF_TR_RX_REQ	smif.tr_rx_req
CYHAL_TRIGGER_SMIF_TR_TX_REQ	smif.tr_tx_req
CYHAL_TRIGGER_TCPWM0_TR_COMPARE_MATCH0	tcpwm[0].tr_compare_match[0]
CYHAL_TRIGGER_TCPWM0_TR_COMPARE_MATCH1	tcpwm[0].tr_compare_match[1]
CYHAL_TRIGGER_TCPWM0_TR_COMPARE_MATCH2	tcpwm[0].tr_compare_match[2]
CYHAL_TRIGGER_TCPWM0_TR_COMPARE_MATCH3	tcpwm[0].tr_compare_match[3]
CYHAL_TRIGGER_TCPWM0_TR_COMPARE_MATCH4	tcpwm[0].tr_compare_match[4]
CYHAL_TRIGGER_TCPWM0_TR_COMPARE_MATCH5	tcpwm[0].tr_compare_match[5]
CYHAL_TRIGGER_TCPWM0_TR_COMPARE_MATCH6	tcpwm[0].tr_compare_match[6]
CYHAL_TRIGGER_TCPWM0_TR_COMPARE_MATCH7	tcpwm[0].tr_compare_match[7]
CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH0	tcpwm[1].tr_compare_match[0]
CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH1	tcpwm[1].tr_compare_match[1]
CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH2	tcpwm[1].tr_compare_match[2]
CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH3	tcpwm[1].tr_compare_match[3]
CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH4	tcpwm[1].tr_compare_match[4]
CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH5	tcpwm[1].tr_compare_match[5]
CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH6	tcpwm[1].tr_compare_match[6]
CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH7	tcpwm[1].tr_compare_match[7]
CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH8	tcpwm[1].tr_compare_match[8]
CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH9	tcpwm[1].tr_compare_match[9]
CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH10	tcpwm[1].tr_compare_match[10]
CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH11	tcpwm[1].tr_compare_match[11]
CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH12	tcpwm[1].tr_compare_match[12]
CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH13	tcpwm[1].tr_compare_match[13]
CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH14	tcpwm[1].tr_compare_match[14]
CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH15	tcpwm[1].tr_compare_match[15]
CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH16	tcpwm[1].tr_compare_match[16]
CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH17	tcpwm[1].tr_compare_match[17]
CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH18	tcpwm[1].tr_compare_match[18]
CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH19	tcpwm[1].tr_compare_match[19]
CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH20	tcpwm[1].tr_compare_match[20]
CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH21	tcpwm[1].tr_compare_match[21]
CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH22	tcpwm[1].tr_compare_match[22]
CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH23	tcpwm[1].tr_compare_match[23]
CYHAL_TRIGGER_TCPWM0_TR_OVERFLOW0	tcpwm[0].tr_overflow[0]
CYHAL_TRIGGER_TCPWM0_TR_OVERFLOW1	tcpwm[0].tr_overflow[1]
CYHAL_TRIGGER_TCPWM0_TR_OVERFLOW2	tcpwm[0].tr_overflow[2]
CYHAL_TRIGGER_TCPWM0_TR_OVERFLOW3	tcpwm[0].tr_overflow[3]
CYHAL_TRIGGER_TCPWM0_TR_OVERFLOW4	tcpwm[0].tr_overflow[4]
CYHAL_TRIGGER_TCPWM0_TR_OVERFLOW5	tcpwm[0].tr_overflow[5]
CYHAL_TRIGGER_TCPWM0_TR_OVERFLOW6	tcpwm[0].tr_overflow[6]
CYHAL_TRIGGER_TCPWM0_TR_OVERFLOW7	tcpwm[0].tr_overflow[7]
CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW0	tcpwm[1].tr_overflow[0]
CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW1	tcpwm[1].tr_overflow[1]
CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW2	tcpwm[1].tr_overflow[2]
CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW3	tcpwm[1].tr_overflow[3]
CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW4	tcpwm[1].tr_overflow[4]
CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW5	tcpwm[1].tr_overflow[5]
CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW6	tcpwm[1].tr_overflow[6]
CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW7	tcpwm[1].tr_overflow[7]
CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW8	tcpwm[1].tr_overflow[8]
CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW9	tcpwm[1].tr_overflow[9]
CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW10	tcpwm[1].tr_overflow[10]
CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW11	tcpwm[1].tr_overflow[11]
CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW12	tcpwm[1].tr_overflow[12]
CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW13	tcpwm[1].tr_overflow[13]
CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW14	tcpwm[1].tr_overflow[14]
CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW15	tcpwm[1].tr_overflow[15]
CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW16	tcpwm[1].tr_overflow[16]
CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW17	tcpwm[1].tr_overflow[17]
CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW18	tcpwm[1].tr_overflow[18]
CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW19	tcpwm[1].tr_overflow[19]
CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW20	tcpwm[1].tr_overflow[20]
CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW21	tcpwm[1].tr_overflow[21]
CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW22	tcpwm[1].tr_overflow[22]
CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW23	tcpwm[1].tr_overflow[23]
CYHAL_TRIGGER_TCPWM0_TR_UNDERFLOW0	tcpwm[0].tr_underflow[0]
CYHAL_TRIGGER_TCPWM0_TR_UNDERFLOW1	tcpwm[0].tr_underflow[1]
CYHAL_TRIGGER_TCPWM0_TR_UNDERFLOW2	tcpwm[0].tr_underflow[2]
CYHAL_TRIGGER_TCPWM0_TR_UNDERFLOW3	tcpwm[0].tr_underflow[3]
CYHAL_TRIGGER_TCPWM0_TR_UNDERFLOW4	tcpwm[0].tr_underflow[4]
CYHAL_TRIGGER_TCPWM0_TR_UNDERFLOW5	tcpwm[0].tr_underflow[5]
CYHAL_TRIGGER_TCPWM0_TR_UNDERFLOW6	tcpwm[0].tr_underflow[6]
CYHAL_TRIGGER_TCPWM0_TR_UNDERFLOW7	tcpwm[0].tr_underflow[7]
CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW0	tcpwm[1].tr_underflow[0]
CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW1	tcpwm[1].tr_underflow[1]
CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW2	tcpwm[1].tr_underflow[2]
CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW3	tcpwm[1].tr_underflow[3]
CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW4	tcpwm[1].tr_underflow[4]
CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW5	tcpwm[1].tr_underflow[5]
CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW6	tcpwm[1].tr_underflow[6]
CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW7	tcpwm[1].tr_underflow[7]
CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW8	tcpwm[1].tr_underflow[8]
CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW9	tcpwm[1].tr_underflow[9]
CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW10	tcpwm[1].tr_underflow[10]
CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW11	tcpwm[1].tr_underflow[11]
CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW12	tcpwm[1].tr_underflow[12]
CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW13	tcpwm[1].tr_underflow[13]
CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW14	tcpwm[1].tr_underflow[14]
CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW15	tcpwm[1].tr_underflow[15]
CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW16	tcpwm[1].tr_underflow[16]
CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW17	tcpwm[1].tr_underflow[17]
CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW18	tcpwm[1].tr_underflow[18]
CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW19	tcpwm[1].tr_underflow[19]
CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW20	tcpwm[1].tr_underflow[20]
CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW21	tcpwm[1].tr_underflow[21]
CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW22	tcpwm[1].tr_underflow[22]
CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW23	tcpwm[1].tr_underflow[23]
CYHAL_TRIGGER_TR_GROUP10_OUTPUT0_EDGE	tr_group[10].output[0]
CYHAL_TRIGGER_TR_GROUP10_OUTPUT0_LEVEL	tr_group[10].output[0]
CYHAL_TRIGGER_TR_GROUP10_OUTPUT1_EDGE	tr_group[10].output[1]
CYHAL_TRIGGER_TR_GROUP10_OUTPUT1_LEVEL	tr_group[10].output[1]
CYHAL_TRIGGER_TR_GROUP10_OUTPUT2_EDGE	tr_group[10].output[2]
CYHAL_TRIGGER_TR_GROUP10_OUTPUT2_LEVEL	tr_group[10].output[2]
CYHAL_TRIGGER_TR_GROUP10_OUTPUT3_EDGE	tr_group[10].output[3]
CYHAL_TRIGGER_TR_GROUP10_OUTPUT3_LEVEL	tr_group[10].output[3]
CYHAL_TRIGGER_TR_GROUP10_OUTPUT4_EDGE	tr_group[10].output[4]
CYHAL_TRIGGER_TR_GROUP10_OUTPUT4_LEVEL	tr_group[10].output[4]
CYHAL_TRIGGER_TR_GROUP10_OUTPUT5_EDGE	tr_group[10].output[5]
CYHAL_TRIGGER_TR_GROUP10_OUTPUT5_LEVEL	tr_group[10].output[5]
CYHAL_TRIGGER_TR_GROUP10_OUTPUT6_EDGE	tr_group[10].output[6]
CYHAL_TRIGGER_TR_GROUP10_OUTPUT6_LEVEL	tr_group[10].output[6]
CYHAL_TRIGGER_TR_GROUP10_OUTPUT7_EDGE	tr_group[10].output[7]
CYHAL_TRIGGER_TR_GROUP10_OUTPUT7_LEVEL	tr_group[10].output[7]
CYHAL_TRIGGER_TR_GROUP11_OUTPUT0_EDGE	tr_group[11].output[0]
CYHAL_TRIGGER_TR_GROUP11_OUTPUT0_LEVEL	tr_group[11].output[0]
CYHAL_TRIGGER_TR_GROUP11_OUTPUT1_EDGE	tr_group[11].output[1]
CYHAL_TRIGGER_TR_GROUP11_OUTPUT1_LEVEL	tr_group[11].output[1]
CYHAL_TRIGGER_TR_GROUP11_OUTPUT2_EDGE	tr_group[11].output[2]
CYHAL_TRIGGER_TR_GROUP11_OUTPUT2_LEVEL	tr_group[11].output[2]
CYHAL_TRIGGER_TR_GROUP11_OUTPUT3_EDGE	tr_group[11].output[3]
CYHAL_TRIGGER_TR_GROUP11_OUTPUT3_LEVEL	tr_group[11].output[3]
CYHAL_TRIGGER_TR_GROUP11_OUTPUT4_EDGE	tr_group[11].output[4]
CYHAL_TRIGGER_TR_GROUP11_OUTPUT4_LEVEL	tr_group[11].output[4]
CYHAL_TRIGGER_TR_GROUP11_OUTPUT5_EDGE	tr_group[11].output[5]
CYHAL_TRIGGER_TR_GROUP11_OUTPUT5_LEVEL	tr_group[11].output[5]
CYHAL_TRIGGER_TR_GROUP11_OUTPUT6_EDGE	tr_group[11].output[6]
CYHAL_TRIGGER_TR_GROUP11_OUTPUT6_LEVEL	tr_group[11].output[6]
CYHAL_TRIGGER_TR_GROUP11_OUTPUT7_EDGE	tr_group[11].output[7]
CYHAL_TRIGGER_TR_GROUP11_OUTPUT7_LEVEL	tr_group[11].output[7]
CYHAL_TRIGGER_TR_GROUP11_OUTPUT8_EDGE	tr_group[11].output[8]
CYHAL_TRIGGER_TR_GROUP11_OUTPUT8_LEVEL	tr_group[11].output[8]
CYHAL_TRIGGER_TR_GROUP11_OUTPUT9_EDGE	tr_group[11].output[9]
CYHAL_TRIGGER_TR_GROUP11_OUTPUT9_LEVEL	tr_group[11].output[9]
CYHAL_TRIGGER_TR_GROUP11_OUTPUT10_EDGE	tr_group[11].output[10]
CYHAL_TRIGGER_TR_GROUP11_OUTPUT10_LEVEL	tr_group[11].output[10]
CYHAL_TRIGGER_TR_GROUP11_OUTPUT11_EDGE	tr_group[11].output[11]
CYHAL_TRIGGER_TR_GROUP11_OUTPUT11_LEVEL	tr_group[11].output[11]
CYHAL_TRIGGER_TR_GROUP11_OUTPUT12_EDGE	tr_group[11].output[12]
CYHAL_TRIGGER_TR_GROUP11_OUTPUT12_LEVEL	tr_group[11].output[12]
CYHAL_TRIGGER_TR_GROUP11_OUTPUT13_EDGE	tr_group[11].output[13]
CYHAL_TRIGGER_TR_GROUP11_OUTPUT13_LEVEL	tr_group[11].output[13]
CYHAL_TRIGGER_TR_GROUP11_OUTPUT14_EDGE	tr_group[11].output[14]
CYHAL_TRIGGER_TR_GROUP11_OUTPUT14_LEVEL	tr_group[11].output[14]
CYHAL_TRIGGER_TR_GROUP11_OUTPUT15_EDGE	tr_group[11].output[15]
CYHAL_TRIGGER_TR_GROUP11_OUTPUT15_LEVEL	tr_group[11].output[15]
CYHAL_TRIGGER_TR_GROUP12_OUTPUT0_EDGE	tr_group[12].output[0]
CYHAL_TRIGGER_TR_GROUP12_OUTPUT0_LEVEL	tr_group[12].output[0]
CYHAL_TRIGGER_TR_GROUP12_OUTPUT1_EDGE	tr_group[12].output[1]
CYHAL_TRIGGER_TR_GROUP12_OUTPUT1_LEVEL	tr_group[12].output[1]
CYHAL_TRIGGER_TR_GROUP12_OUTPUT2_EDGE	tr_group[12].output[2]
CYHAL_TRIGGER_TR_GROUP12_OUTPUT2_LEVEL	tr_group[12].output[2]
CYHAL_TRIGGER_TR_GROUP12_OUTPUT3_EDGE	tr_group[12].output[3]
CYHAL_TRIGGER_TR_GROUP12_OUTPUT3_LEVEL	tr_group[12].output[3]
CYHAL_TRIGGER_TR_GROUP12_OUTPUT4_EDGE	tr_group[12].output[4]
CYHAL_TRIGGER_TR_GROUP12_OUTPUT4_LEVEL	tr_group[12].output[4]
CYHAL_TRIGGER_TR_GROUP12_OUTPUT5_EDGE	tr_group[12].output[5]
CYHAL_TRIGGER_TR_GROUP12_OUTPUT5_LEVEL	tr_group[12].output[5]
CYHAL_TRIGGER_TR_GROUP12_OUTPUT6_EDGE	tr_group[12].output[6]
CYHAL_TRIGGER_TR_GROUP12_OUTPUT6_LEVEL	tr_group[12].output[6]
CYHAL_TRIGGER_TR_GROUP12_OUTPUT7_EDGE	tr_group[12].output[7]
CYHAL_TRIGGER_TR_GROUP12_OUTPUT7_LEVEL	tr_group[12].output[7]
CYHAL_TRIGGER_TR_GROUP12_OUTPUT8_EDGE	tr_group[12].output[8]
CYHAL_TRIGGER_TR_GROUP12_OUTPUT8_LEVEL	tr_group[12].output[8]
CYHAL_TRIGGER_TR_GROUP12_OUTPUT9_EDGE	tr_group[12].output[9]
CYHAL_TRIGGER_TR_GROUP12_OUTPUT9_LEVEL	tr_group[12].output[9]
CYHAL_TRIGGER_TR_GROUP13_OUTPUT0_EDGE	tr_group[13].output[0]
CYHAL_TRIGGER_TR_GROUP13_OUTPUT0_LEVEL	tr_group[13].output[0]
CYHAL_TRIGGER_TR_GROUP13_OUTPUT1_EDGE	tr_group[13].output[1]
CYHAL_TRIGGER_TR_GROUP13_OUTPUT1_LEVEL	tr_group[13].output[1]
CYHAL_TRIGGER_TR_GROUP13_OUTPUT2_EDGE	tr_group[13].output[2]
CYHAL_TRIGGER_TR_GROUP13_OUTPUT2_LEVEL	tr_group[13].output[2]
CYHAL_TRIGGER_TR_GROUP13_OUTPUT3_EDGE	tr_group[13].output[3]
CYHAL_TRIGGER_TR_GROUP13_OUTPUT3_LEVEL	tr_group[13].output[3]
CYHAL_TRIGGER_TR_GROUP13_OUTPUT4_EDGE	tr_group[13].output[4]
CYHAL_TRIGGER_TR_GROUP13_OUTPUT4_LEVEL	tr_group[13].output[4]
CYHAL_TRIGGER_TR_GROUP13_OUTPUT5_EDGE	tr_group[13].output[5]
CYHAL_TRIGGER_TR_GROUP13_OUTPUT5_LEVEL	tr_group[13].output[5]
CYHAL_TRIGGER_TR_GROUP13_OUTPUT6_EDGE	tr_group[13].output[6]
CYHAL_TRIGGER_TR_GROUP13_OUTPUT6_LEVEL	tr_group[13].output[6]
CYHAL_TRIGGER_TR_GROUP13_OUTPUT7_EDGE	tr_group[13].output[7]
CYHAL_TRIGGER_TR_GROUP13_OUTPUT7_LEVEL	tr_group[13].output[7]
CYHAL_TRIGGER_TR_GROUP13_OUTPUT8_EDGE	tr_group[13].output[8]
CYHAL_TRIGGER_TR_GROUP13_OUTPUT8_LEVEL	tr_group[13].output[8]
CYHAL_TRIGGER_TR_GROUP13_OUTPUT9_EDGE	tr_group[13].output[9]
CYHAL_TRIGGER_TR_GROUP13_OUTPUT9_LEVEL	tr_group[13].output[9]
CYHAL_TRIGGER_TR_GROUP13_OUTPUT10_EDGE	tr_group[13].output[10]
CYHAL_TRIGGER_TR_GROUP13_OUTPUT10_LEVEL	tr_group[13].output[10]
CYHAL_TRIGGER_TR_GROUP13_OUTPUT11_EDGE	tr_group[13].output[11]
CYHAL_TRIGGER_TR_GROUP13_OUTPUT11_LEVEL	tr_group[13].output[11]
CYHAL_TRIGGER_TR_GROUP13_OUTPUT12_EDGE	tr_group[13].output[12]
CYHAL_TRIGGER_TR_GROUP13_OUTPUT12_LEVEL	tr_group[13].output[12]
CYHAL_TRIGGER_TR_GROUP13_OUTPUT13_EDGE	tr_group[13].output[13]
CYHAL_TRIGGER_TR_GROUP13_OUTPUT13_LEVEL	tr_group[13].output[13]
CYHAL_TRIGGER_TR_GROUP13_OUTPUT14_EDGE	tr_group[13].output[14]
CYHAL_TRIGGER_TR_GROUP13_OUTPUT14_LEVEL	tr_group[13].output[14]
CYHAL_TRIGGER_TR_GROUP13_OUTPUT15_EDGE	tr_group[13].output[15]
CYHAL_TRIGGER_TR_GROUP13_OUTPUT15_LEVEL	tr_group[13].output[15]
CYHAL_TRIGGER_TR_GROUP13_OUTPUT16_EDGE	tr_group[13].output[16]
CYHAL_TRIGGER_TR_GROUP13_OUTPUT16_LEVEL	tr_group[13].output[16]
CYHAL_TRIGGER_TR_GROUP13_OUTPUT17_EDGE	tr_group[13].output[17]
CYHAL_TRIGGER_TR_GROUP13_OUTPUT17_LEVEL	tr_group[13].output[17]
CYHAL_TRIGGER_TR_GROUP14_OUTPUT0_EDGE	tr_group[14].output[0]
CYHAL_TRIGGER_TR_GROUP14_OUTPUT0_LEVEL	tr_group[14].output[0]
CYHAL_TRIGGER_TR_GROUP14_OUTPUT1_EDGE	tr_group[14].output[1]
CYHAL_TRIGGER_TR_GROUP14_OUTPUT1_LEVEL	tr_group[14].output[1]
CYHAL_TRIGGER_TR_GROUP14_OUTPUT2_EDGE	tr_group[14].output[2]
CYHAL_TRIGGER_TR_GROUP14_OUTPUT2_LEVEL	tr_group[14].output[2]
CYHAL_TRIGGER_TR_GROUP14_OUTPUT3_EDGE	tr_group[14].output[3]
CYHAL_TRIGGER_TR_GROUP14_OUTPUT3_LEVEL	tr_group[14].output[3]
CYHAL_TRIGGER_TR_GROUP14_OUTPUT4_EDGE	tr_group[14].output[4]
CYHAL_TRIGGER_TR_GROUP14_OUTPUT4_LEVEL	tr_group[14].output[4]
CYHAL_TRIGGER_TR_GROUP14_OUTPUT5_EDGE	tr_group[14].output[5]
CYHAL_TRIGGER_TR_GROUP14_OUTPUT5_LEVEL	tr_group[14].output[5]
CYHAL_TRIGGER_TR_GROUP14_OUTPUT6_EDGE	tr_group[14].output[6]
CYHAL_TRIGGER_TR_GROUP14_OUTPUT6_LEVEL	tr_group[14].output[6]
CYHAL_TRIGGER_TR_GROUP14_OUTPUT7_EDGE	tr_group[14].output[7]
CYHAL_TRIGGER_TR_GROUP14_OUTPUT7_LEVEL	tr_group[14].output[7]
CYHAL_TRIGGER_TR_GROUP14_OUTPUT8_EDGE	tr_group[14].output[8]
CYHAL_TRIGGER_TR_GROUP14_OUTPUT8_LEVEL	tr_group[14].output[8]
CYHAL_TRIGGER_TR_GROUP14_OUTPUT9_EDGE	tr_group[14].output[9]
CYHAL_TRIGGER_TR_GROUP14_OUTPUT9_LEVEL	tr_group[14].output[9]
CYHAL_TRIGGER_TR_GROUP14_OUTPUT10_EDGE	tr_group[14].output[10]
CYHAL_TRIGGER_TR_GROUP14_OUTPUT10_LEVEL	tr_group[14].output[10]
CYHAL_TRIGGER_TR_GROUP14_OUTPUT11_EDGE	tr_group[14].output[11]
CYHAL_TRIGGER_TR_GROUP14_OUTPUT11_LEVEL	tr_group[14].output[11]
CYHAL_TRIGGER_TR_GROUP14_OUTPUT12_EDGE	tr_group[14].output[12]
CYHAL_TRIGGER_TR_GROUP14_OUTPUT12_LEVEL	tr_group[14].output[12]
CYHAL_TRIGGER_TR_GROUP14_OUTPUT13_EDGE	tr_group[14].output[13]
CYHAL_TRIGGER_TR_GROUP14_OUTPUT13_LEVEL	tr_group[14].output[13]
CYHAL_TRIGGER_TR_GROUP14_OUTPUT14_EDGE	tr_group[14].output[14]
CYHAL_TRIGGER_TR_GROUP14_OUTPUT14_LEVEL	tr_group[14].output[14]
CYHAL_TRIGGER_TR_GROUP14_OUTPUT15_EDGE	tr_group[14].output[15]
CYHAL_TRIGGER_TR_GROUP14_OUTPUT15_LEVEL	tr_group[14].output[15]
CYHAL_TRIGGER_UDB_DSI_OUT_TR0_EDGE	udb.dsi_out_tr[0]
CYHAL_TRIGGER_UDB_DSI_OUT_TR0_LEVEL	udb.dsi_out_tr[0]
CYHAL_TRIGGER_UDB_DSI_OUT_TR1_EDGE	udb.dsi_out_tr[1]
CYHAL_TRIGGER_UDB_DSI_OUT_TR1_LEVEL	udb.dsi_out_tr[1]
CYHAL_TRIGGER_UDB_TR_UDB0_EDGE	udb.tr_udb[0]
CYHAL_TRIGGER_UDB_TR_UDB0_LEVEL	udb.tr_udb[0]
CYHAL_TRIGGER_UDB_TR_UDB1_EDGE	udb.tr_udb[1]
CYHAL_TRIGGER_UDB_TR_UDB1_LEVEL	udb.tr_udb[1]
CYHAL_TRIGGER_UDB_TR_UDB2_EDGE	udb.tr_udb[2]
CYHAL_TRIGGER_UDB_TR_UDB2_LEVEL	udb.tr_udb[2]
CYHAL_TRIGGER_UDB_TR_UDB3_EDGE	udb.tr_udb[3]
CYHAL_TRIGGER_UDB_TR_UDB3_LEVEL	udb.tr_udb[3]
CYHAL_TRIGGER_UDB_TR_UDB4_EDGE	udb.tr_udb[4]
CYHAL_TRIGGER_UDB_TR_UDB4_LEVEL	udb.tr_udb[4]
CYHAL_TRIGGER_UDB_TR_UDB5_EDGE	udb.tr_udb[5]
CYHAL_TRIGGER_UDB_TR_UDB5_LEVEL	udb.tr_udb[5]
CYHAL_TRIGGER_UDB_TR_UDB6_EDGE	udb.tr_udb[6]
CYHAL_TRIGGER_UDB_TR_UDB6_LEVEL	udb.tr_udb[6]
CYHAL_TRIGGER_UDB_TR_UDB7_EDGE	udb.tr_udb[7]
CYHAL_TRIGGER_UDB_TR_UDB7_LEVEL	udb.tr_udb[7]
CYHAL_TRIGGER_UDB_TR_UDB8_EDGE	udb.tr_udb[8]
CYHAL_TRIGGER_UDB_TR_UDB8_LEVEL	udb.tr_udb[8]
CYHAL_TRIGGER_UDB_TR_UDB9_EDGE	udb.tr_udb[9]
CYHAL_TRIGGER_UDB_TR_UDB9_LEVEL	udb.tr_udb[9]
CYHAL_TRIGGER_UDB_TR_UDB10_EDGE	udb.tr_udb[10]
CYHAL_TRIGGER_UDB_TR_UDB10_LEVEL	udb.tr_udb[10]
CYHAL_TRIGGER_UDB_TR_UDB11_EDGE	udb.tr_udb[11]
CYHAL_TRIGGER_UDB_TR_UDB11_LEVEL	udb.tr_udb[11]
CYHAL_TRIGGER_UDB_TR_UDB12_EDGE	udb.tr_udb[12]
CYHAL_TRIGGER_UDB_TR_UDB12_LEVEL	udb.tr_udb[12]
CYHAL_TRIGGER_UDB_TR_UDB13_EDGE	udb.tr_udb[13]
CYHAL_TRIGGER_UDB_TR_UDB13_LEVEL	udb.tr_udb[13]
CYHAL_TRIGGER_UDB_TR_UDB14_EDGE	udb.tr_udb[14]
CYHAL_TRIGGER_UDB_TR_UDB14_LEVEL	udb.tr_udb[14]
CYHAL_TRIGGER_UDB_TR_UDB15_EDGE	udb.tr_udb[15]
CYHAL_TRIGGER_UDB_TR_UDB15_LEVEL	udb.tr_udb[15]
CYHAL_TRIGGER_USB_DMA_REQ0	usb.dma_req[0]
CYHAL_TRIGGER_USB_DMA_REQ1	usb.dma_req[1]
CYHAL_TRIGGER_USB_DMA_REQ2	usb.dma_req[2]
CYHAL_TRIGGER_USB_DMA_REQ3	usb.dma_req[3]
CYHAL_TRIGGER_USB_DMA_REQ4	usb.dma_req[4]
CYHAL_TRIGGER_USB_DMA_REQ5	usb.dma_req[5]
CYHAL_TRIGGER_USB_DMA_REQ6	usb.dma_req[6]
CYHAL_TRIGGER_USB_DMA_REQ7	usb.dma_req[7]

cyhal_trigger_dest_psoc6_01_t

enum cyhal_trigger_dest_psoc6_01_t

Name of each output trigger.

Enumerator
CYHAL_TRIGGER_CPUSS_CTI_TR_IN0	CPUSS Cross-Triggering-Interface trigger multiplexer (CTI) - cpuss.cti_tr_in[0].
CYHAL_TRIGGER_CPUSS_CTI_TR_IN1	CPUSS Cross-Triggering-Interface trigger multiplexer (CTI) - cpuss.cti_tr_in[1].
CYHAL_TRIGGER_CPUSS_DW0_TR_IN0	DW0 trigger multiplexer - cpuss.dw0_tr_in[0].
CYHAL_TRIGGER_CPUSS_DW0_TR_IN1	DW0 trigger multiplexer - cpuss.dw0_tr_in[1].
CYHAL_TRIGGER_CPUSS_DW0_TR_IN2	DW0 trigger multiplexer - cpuss.dw0_tr_in[2].
CYHAL_TRIGGER_CPUSS_DW0_TR_IN3	DW0 trigger multiplexer - cpuss.dw0_tr_in[3].
CYHAL_TRIGGER_CPUSS_DW0_TR_IN4	DW0 trigger multiplexer - cpuss.dw0_tr_in[4].
CYHAL_TRIGGER_CPUSS_DW0_TR_IN5	DW0 trigger multiplexer - cpuss.dw0_tr_in[5].
CYHAL_TRIGGER_CPUSS_DW0_TR_IN6	DW0 trigger multiplexer - cpuss.dw0_tr_in[6].
CYHAL_TRIGGER_CPUSS_DW0_TR_IN7	DW0 trigger multiplexer - cpuss.dw0_tr_in[7].
CYHAL_TRIGGER_CPUSS_DW0_TR_IN8	DW0 trigger multiplexer - cpuss.dw0_tr_in[8].
CYHAL_TRIGGER_CPUSS_DW0_TR_IN9	DW0 trigger multiplexer - cpuss.dw0_tr_in[9].
CYHAL_TRIGGER_CPUSS_DW0_TR_IN10	DW0 trigger multiplexer - cpuss.dw0_tr_in[10].
CYHAL_TRIGGER_CPUSS_DW0_TR_IN11	DW0 trigger multiplexer - cpuss.dw0_tr_in[11].
CYHAL_TRIGGER_CPUSS_DW0_TR_IN12	DW0 trigger multiplexer - cpuss.dw0_tr_in[12].
CYHAL_TRIGGER_CPUSS_DW0_TR_IN13	DW0 trigger multiplexer - cpuss.dw0_tr_in[13].
CYHAL_TRIGGER_CPUSS_DW0_TR_IN14	DW0 trigger multiplexer - cpuss.dw0_tr_in[14].
CYHAL_TRIGGER_CPUSS_DW0_TR_IN15	DW0 trigger multiplexer - cpuss.dw0_tr_in[15].
CYHAL_TRIGGER_CPUSS_DW1_TR_IN0	DW1 trigger multiplexer - cpuss.dw1_tr_in[0].
CYHAL_TRIGGER_CPUSS_DW1_TR_IN1	DW1 trigger multiplexer - cpuss.dw1_tr_in[1].
CYHAL_TRIGGER_CPUSS_DW1_TR_IN2	DW1 trigger multiplexer - cpuss.dw1_tr_in[2].
CYHAL_TRIGGER_CPUSS_DW1_TR_IN3	DW1 trigger multiplexer - cpuss.dw1_tr_in[3].
CYHAL_TRIGGER_CPUSS_DW1_TR_IN4	DW1 trigger multiplexer - cpuss.dw1_tr_in[4].
CYHAL_TRIGGER_CPUSS_DW1_TR_IN5	DW1 trigger multiplexer - cpuss.dw1_tr_in[5].
CYHAL_TRIGGER_CPUSS_DW1_TR_IN6	DW1 trigger multiplexer - cpuss.dw1_tr_in[6].
CYHAL_TRIGGER_CPUSS_DW1_TR_IN7	DW1 trigger multiplexer - cpuss.dw1_tr_in[7].
CYHAL_TRIGGER_CPUSS_DW1_TR_IN8	DW1 trigger multiplexer - cpuss.dw1_tr_in[8].
CYHAL_TRIGGER_CPUSS_DW1_TR_IN9	DW1 trigger multiplexer - cpuss.dw1_tr_in[9].
CYHAL_TRIGGER_CPUSS_DW1_TR_IN10	DW1 trigger multiplexer - cpuss.dw1_tr_in[10].
CYHAL_TRIGGER_CPUSS_DW1_TR_IN11	DW1 trigger multiplexer - cpuss.dw1_tr_in[11].
CYHAL_TRIGGER_CPUSS_DW1_TR_IN12	DW1 trigger multiplexer - cpuss.dw1_tr_in[12].
CYHAL_TRIGGER_CPUSS_DW1_TR_IN13	DW1 trigger multiplexer - cpuss.dw1_tr_in[13].
CYHAL_TRIGGER_CPUSS_DW1_TR_IN14	DW1 trigger multiplexer - cpuss.dw1_tr_in[14].
CYHAL_TRIGGER_CPUSS_DW1_TR_IN15	DW1 trigger multiplexer - cpuss.dw1_tr_in[15].
CYHAL_TRIGGER_PASS_TR_SAR_IN	PASS trigger multiplexer - pass.tr_sar_in.
CYHAL_TRIGGER_PERI_TR_IO_OUTPUT0	GPIO/HSIOM trigger multiplexer - peri.tr_io_output[0].
CYHAL_TRIGGER_PERI_TR_IO_OUTPUT1	GPIO/HSIOM trigger multiplexer - peri.tr_io_output[1].
CYHAL_TRIGGER_PROFILE_TR_START	PROFILE trigger multiplexer - profile.tr_start.
CYHAL_TRIGGER_PROFILE_TR_STOP	PROFILE trigger multiplexer - profile.tr_stop.
CYHAL_TRIGGER_TCPWM0_TR_IN0	TCPWM0 Trigger Multiplexer - tcpwm[0].tr_in[0].
CYHAL_TRIGGER_TCPWM0_TR_IN1	TCPWM0 Trigger Multiplexer - tcpwm[0].tr_in[1].
CYHAL_TRIGGER_TCPWM0_TR_IN2	TCPWM0 Trigger Multiplexer - tcpwm[0].tr_in[2].
CYHAL_TRIGGER_TCPWM0_TR_IN3	TCPWM0 Trigger Multiplexer - tcpwm[0].tr_in[3].
CYHAL_TRIGGER_TCPWM0_TR_IN4	TCPWM0 Trigger Multiplexer - tcpwm[0].tr_in[4].
CYHAL_TRIGGER_TCPWM0_TR_IN5	TCPWM0 Trigger Multiplexer - tcpwm[0].tr_in[5].
CYHAL_TRIGGER_TCPWM0_TR_IN6	TCPWM0 Trigger Multiplexer - tcpwm[0].tr_in[6].
CYHAL_TRIGGER_TCPWM0_TR_IN7	TCPWM0 Trigger Multiplexer - tcpwm[0].tr_in[7].
CYHAL_TRIGGER_TCPWM0_TR_IN8	TCPWM0 Trigger Multiplexer - tcpwm[0].tr_in[8].
CYHAL_TRIGGER_TCPWM0_TR_IN9	TCPWM0 Trigger Multiplexer - tcpwm[0].tr_in[9].
CYHAL_TRIGGER_TCPWM0_TR_IN10	TCPWM0 Trigger Multiplexer - tcpwm[0].tr_in[10].
CYHAL_TRIGGER_TCPWM0_TR_IN11	TCPWM0 Trigger Multiplexer - tcpwm[0].tr_in[11].
CYHAL_TRIGGER_TCPWM0_TR_IN12	TCPWM0 Trigger Multiplexer - tcpwm[0].tr_in[12].
CYHAL_TRIGGER_TCPWM0_TR_IN13	TCPWM0 Trigger Multiplexer - tcpwm[0].tr_in[13].
CYHAL_TRIGGER_TCPWM1_TR_IN0	TCPWM1 Trigger Multiplexer - tcpwm[1].tr_in[0].
CYHAL_TRIGGER_TCPWM1_TR_IN1	TCPWM1 Trigger Multiplexer - tcpwm[1].tr_in[1].
CYHAL_TRIGGER_TCPWM1_TR_IN2	TCPWM1 Trigger Multiplexer - tcpwm[1].tr_in[2].
CYHAL_TRIGGER_TCPWM1_TR_IN3	TCPWM1 Trigger Multiplexer - tcpwm[1].tr_in[3].
CYHAL_TRIGGER_TCPWM1_TR_IN4	TCPWM1 Trigger Multiplexer - tcpwm[1].tr_in[4].
CYHAL_TRIGGER_TCPWM1_TR_IN5	TCPWM1 Trigger Multiplexer - tcpwm[1].tr_in[5].
CYHAL_TRIGGER_TCPWM1_TR_IN6	TCPWM1 Trigger Multiplexer - tcpwm[1].tr_in[6].
CYHAL_TRIGGER_TCPWM1_TR_IN7	TCPWM1 Trigger Multiplexer - tcpwm[1].tr_in[7].
CYHAL_TRIGGER_TCPWM1_TR_IN8	TCPWM1 Trigger Multiplexer - tcpwm[1].tr_in[8].
CYHAL_TRIGGER_TCPWM1_TR_IN9	TCPWM1 Trigger Multiplexer - tcpwm[1].tr_in[9].
CYHAL_TRIGGER_TCPWM1_TR_IN10	TCPWM1 Trigger Multiplexer - tcpwm[1].tr_in[10].
CYHAL_TRIGGER_TCPWM1_TR_IN11	TCPWM1 Trigger Multiplexer - tcpwm[1].tr_in[11].
CYHAL_TRIGGER_TCPWM1_TR_IN12	TCPWM1 Trigger Multiplexer - tcpwm[1].tr_in[12].
CYHAL_TRIGGER_TCPWM1_TR_IN13	TCPWM1 Trigger Multiplexer - tcpwm[1].tr_in[13].
CYHAL_TRIGGER_TR_GROUP0_INPUT1	Datawire output trigger reduction mux - tr_group[0].input[1].
CYHAL_TRIGGER_TR_GROUP0_INPUT2	Datawire output trigger reduction mux - tr_group[0].input[2].
CYHAL_TRIGGER_TR_GROUP0_INPUT3	Datawire output trigger reduction mux - tr_group[0].input[3].
CYHAL_TRIGGER_TR_GROUP0_INPUT4	Datawire output trigger reduction mux - tr_group[0].input[4].
CYHAL_TRIGGER_TR_GROUP0_INPUT5	Datawire output trigger reduction mux - tr_group[0].input[5].
CYHAL_TRIGGER_TR_GROUP0_INPUT6	Datawire output trigger reduction mux - tr_group[0].input[6].
CYHAL_TRIGGER_TR_GROUP0_INPUT7	Datawire output trigger reduction mux - tr_group[0].input[7].
CYHAL_TRIGGER_TR_GROUP0_INPUT8	Datawire output trigger reduction mux - tr_group[0].input[8].
CYHAL_TRIGGER_TR_GROUP0_INPUT9	TCPWM trigger output reduction mux - tr_group[0].input[9].
CYHAL_TRIGGER_TR_GROUP0_INPUT10	TCPWM trigger output reduction mux - tr_group[0].input[10].
CYHAL_TRIGGER_TR_GROUP0_INPUT11	TCPWM trigger output reduction mux - tr_group[0].input[11].
CYHAL_TRIGGER_TR_GROUP0_INPUT12	TCPWM trigger output reduction mux - tr_group[0].input[12].
CYHAL_TRIGGER_TR_GROUP0_INPUT13	TCPWM trigger output reduction mux - tr_group[0].input[13].
CYHAL_TRIGGER_TR_GROUP0_INPUT14	TCPWM trigger output reduction mux - tr_group[0].input[14].
CYHAL_TRIGGER_TR_GROUP0_INPUT15	TCPWM trigger output reduction mux - tr_group[0].input[15].
CYHAL_TRIGGER_TR_GROUP0_INPUT16	TCPWM trigger output reduction mux - tr_group[0].input[16].
CYHAL_TRIGGER_TR_GROUP0_INPUT17	TCPWM trigger output reduction mux - tr_group[0].input[17].
CYHAL_TRIGGER_TR_GROUP0_INPUT18	TCPWM trigger output reduction mux - tr_group[0].input[18].
CYHAL_TRIGGER_TR_GROUP0_INPUT19	TCPWM trigger output reduction mux - tr_group[0].input[19].
CYHAL_TRIGGER_TR_GROUP0_INPUT20	TCPWM trigger output reduction mux - tr_group[0].input[20].
CYHAL_TRIGGER_TR_GROUP0_INPUT21	TCPWM trigger output reduction mux - tr_group[0].input[21].
CYHAL_TRIGGER_TR_GROUP0_INPUT22	TCPWM trigger output reduction mux - tr_group[0].input[22].
CYHAL_TRIGGER_TR_GROUP0_INPUT23	TCPWM trigger output reduction mux - tr_group[0].input[23].
CYHAL_TRIGGER_TR_GROUP0_INPUT24	TCPWM trigger output reduction mux - tr_group[0].input[24].
CYHAL_TRIGGER_TR_GROUP0_INPUT25	HSIOM Pin input reduction mux - tr_group[0].input[25].
CYHAL_TRIGGER_TR_GROUP0_INPUT26	HSIOM Pin input reduction mux - tr_group[0].input[26].
CYHAL_TRIGGER_TR_GROUP0_INPUT27	DMA request reduction mux - tr_group[0].input[27].
CYHAL_TRIGGER_TR_GROUP0_INPUT28	DMA request reduction mux - tr_group[0].input[28].
CYHAL_TRIGGER_TR_GROUP0_INPUT29	DMA request reduction mux - tr_group[0].input[29].
CYHAL_TRIGGER_TR_GROUP0_INPUT30	DMA request reduction mux - tr_group[0].input[30].
CYHAL_TRIGGER_TR_GROUP0_INPUT31	DMA request reduction mux - tr_group[0].input[31].
CYHAL_TRIGGER_TR_GROUP0_INPUT32	DMA request reduction mux - tr_group[0].input[32].
CYHAL_TRIGGER_TR_GROUP0_INPUT33	DMA request reduction mux - tr_group[0].input[33].
CYHAL_TRIGGER_TR_GROUP0_INPUT34	DMA request reduction mux - tr_group[0].input[34].
CYHAL_TRIGGER_TR_GROUP0_INPUT35	DMA request reduction mux - tr_group[0].input[35].
CYHAL_TRIGGER_TR_GROUP0_INPUT36	DMA request reduction mux - tr_group[0].input[36].
CYHAL_TRIGGER_TR_GROUP0_INPUT37	DMA request reduction mux - tr_group[0].input[37].
CYHAL_TRIGGER_TR_GROUP0_INPUT38	DMA request reduction mux - tr_group[0].input[38].
CYHAL_TRIGGER_TR_GROUP0_INPUT39	DMA request reduction mux - tr_group[0].input[39].
CYHAL_TRIGGER_TR_GROUP0_INPUT40	DMA request reduction mux - tr_group[0].input[40].
CYHAL_TRIGGER_TR_GROUP0_INPUT41	DMA request reduction mux - tr_group[0].input[41].
CYHAL_TRIGGER_TR_GROUP0_INPUT42	DMA request reduction mux - tr_group[0].input[42].
CYHAL_TRIGGER_TR_GROUP0_INPUT43	Trigger input reduction mux - tr_group[0].input[43].
CYHAL_TRIGGER_TR_GROUP0_INPUT44	Trigger input reduction mux - tr_group[0].input[44].
CYHAL_TRIGGER_TR_GROUP0_INPUT45	Trigger input reduction mux - tr_group[0].input[45].
CYHAL_TRIGGER_TR_GROUP0_INPUT46	Trigger input reduction mux - tr_group[0].input[46].
CYHAL_TRIGGER_TR_GROUP0_INPUT47	Trigger input reduction mux - tr_group[0].input[47].
CYHAL_TRIGGER_TR_GROUP0_INPUT48	Trigger input reduction mux - tr_group[0].input[48].
CYHAL_TRIGGER_TR_GROUP0_INPUT49	Trigger input reduction mux - tr_group[0].input[49].
CYHAL_TRIGGER_TR_GROUP0_INPUT50	Trigger input reduction mux - tr_group[0].input[50].
CYHAL_TRIGGER_TR_GROUP1_INPUT1	Datawire output trigger reduction mux - tr_group[1].input[1].
CYHAL_TRIGGER_TR_GROUP1_INPUT2	Datawire output trigger reduction mux - tr_group[1].input[2].
CYHAL_TRIGGER_TR_GROUP1_INPUT3	Datawire output trigger reduction mux - tr_group[1].input[3].
CYHAL_TRIGGER_TR_GROUP1_INPUT4	Datawire output trigger reduction mux - tr_group[1].input[4].
CYHAL_TRIGGER_TR_GROUP1_INPUT5	Datawire output trigger reduction mux - tr_group[1].input[5].
CYHAL_TRIGGER_TR_GROUP1_INPUT6	Datawire output trigger reduction mux - tr_group[1].input[6].
CYHAL_TRIGGER_TR_GROUP1_INPUT7	Datawire output trigger reduction mux - tr_group[1].input[7].
CYHAL_TRIGGER_TR_GROUP1_INPUT8	Datawire output trigger reduction mux - tr_group[1].input[8].
CYHAL_TRIGGER_TR_GROUP1_INPUT9	TCPWM trigger output reduction mux - tr_group[1].input[9].
CYHAL_TRIGGER_TR_GROUP1_INPUT10	TCPWM trigger output reduction mux - tr_group[1].input[10].
CYHAL_TRIGGER_TR_GROUP1_INPUT11	TCPWM trigger output reduction mux - tr_group[1].input[11].
CYHAL_TRIGGER_TR_GROUP1_INPUT12	TCPWM trigger output reduction mux - tr_group[1].input[12].
CYHAL_TRIGGER_TR_GROUP1_INPUT13	TCPWM trigger output reduction mux - tr_group[1].input[13].
CYHAL_TRIGGER_TR_GROUP1_INPUT14	TCPWM trigger output reduction mux - tr_group[1].input[14].
CYHAL_TRIGGER_TR_GROUP1_INPUT15	TCPWM trigger output reduction mux - tr_group[1].input[15].
CYHAL_TRIGGER_TR_GROUP1_INPUT16	TCPWM trigger output reduction mux - tr_group[1].input[16].
CYHAL_TRIGGER_TR_GROUP1_INPUT17	TCPWM trigger output reduction mux - tr_group[1].input[17].
CYHAL_TRIGGER_TR_GROUP1_INPUT18	TCPWM trigger output reduction mux - tr_group[1].input[18].
CYHAL_TRIGGER_TR_GROUP1_INPUT19	TCPWM trigger output reduction mux - tr_group[1].input[19].
CYHAL_TRIGGER_TR_GROUP1_INPUT20	TCPWM trigger output reduction mux - tr_group[1].input[20].
CYHAL_TRIGGER_TR_GROUP1_INPUT21	TCPWM trigger output reduction mux - tr_group[1].input[21].
CYHAL_TRIGGER_TR_GROUP1_INPUT22	TCPWM trigger output reduction mux - tr_group[1].input[22].
CYHAL_TRIGGER_TR_GROUP1_INPUT23	TCPWM trigger output reduction mux - tr_group[1].input[23].
CYHAL_TRIGGER_TR_GROUP1_INPUT24	TCPWM trigger output reduction mux - tr_group[1].input[24].
CYHAL_TRIGGER_TR_GROUP1_INPUT25	HSIOM Pin input reduction mux - tr_group[1].input[25].
CYHAL_TRIGGER_TR_GROUP1_INPUT26	HSIOM Pin input reduction mux - tr_group[1].input[26].
CYHAL_TRIGGER_TR_GROUP1_INPUT27	DMA request reduction mux - tr_group[1].input[27].
CYHAL_TRIGGER_TR_GROUP1_INPUT28	DMA request reduction mux - tr_group[1].input[28].
CYHAL_TRIGGER_TR_GROUP1_INPUT29	DMA request reduction mux - tr_group[1].input[29].
CYHAL_TRIGGER_TR_GROUP1_INPUT30	DMA request reduction mux - tr_group[1].input[30].
CYHAL_TRIGGER_TR_GROUP1_INPUT31	DMA request reduction mux - tr_group[1].input[31].
CYHAL_TRIGGER_TR_GROUP1_INPUT32	DMA request reduction mux - tr_group[1].input[32].
CYHAL_TRIGGER_TR_GROUP1_INPUT33	DMA request reduction mux - tr_group[1].input[33].
CYHAL_TRIGGER_TR_GROUP1_INPUT34	DMA request reduction mux - tr_group[1].input[34].
CYHAL_TRIGGER_TR_GROUP1_INPUT35	DMA request reduction mux - tr_group[1].input[35].
CYHAL_TRIGGER_TR_GROUP1_INPUT36	DMA request reduction mux - tr_group[1].input[36].
CYHAL_TRIGGER_TR_GROUP1_INPUT37	DMA request reduction mux - tr_group[1].input[37].
CYHAL_TRIGGER_TR_GROUP1_INPUT38	DMA request reduction mux - tr_group[1].input[38].
CYHAL_TRIGGER_TR_GROUP1_INPUT39	DMA request reduction mux - tr_group[1].input[39].
CYHAL_TRIGGER_TR_GROUP1_INPUT40	DMA request reduction mux - tr_group[1].input[40].
CYHAL_TRIGGER_TR_GROUP1_INPUT41	DMA request reduction mux - tr_group[1].input[41].
CYHAL_TRIGGER_TR_GROUP1_INPUT42	DMA request reduction mux - tr_group[1].input[42].
CYHAL_TRIGGER_TR_GROUP1_INPUT43	Trigger input reduction mux - tr_group[1].input[43].
CYHAL_TRIGGER_TR_GROUP1_INPUT44	Trigger input reduction mux - tr_group[1].input[44].
CYHAL_TRIGGER_TR_GROUP1_INPUT45	Trigger input reduction mux - tr_group[1].input[45].
CYHAL_TRIGGER_TR_GROUP1_INPUT46	Trigger input reduction mux - tr_group[1].input[46].
CYHAL_TRIGGER_TR_GROUP1_INPUT47	Trigger input reduction mux - tr_group[1].input[47].
CYHAL_TRIGGER_TR_GROUP1_INPUT48	Trigger input reduction mux - tr_group[1].input[48].
CYHAL_TRIGGER_TR_GROUP1_INPUT49	Trigger input reduction mux - tr_group[1].input[49].
CYHAL_TRIGGER_TR_GROUP1_INPUT50	Trigger input reduction mux - tr_group[1].input[50].
CYHAL_TRIGGER_TR_GROUP2_INPUT1	Datawire output trigger reduction mux - tr_group[2].input[1].
CYHAL_TRIGGER_TR_GROUP2_INPUT2	Datawire output trigger reduction mux - tr_group[2].input[2].
CYHAL_TRIGGER_TR_GROUP2_INPUT3	Datawire output trigger reduction mux - tr_group[2].input[3].
CYHAL_TRIGGER_TR_GROUP2_INPUT4	Datawire output trigger reduction mux - tr_group[2].input[4].
CYHAL_TRIGGER_TR_GROUP2_INPUT5	Datawire output trigger reduction mux - tr_group[2].input[5].
CYHAL_TRIGGER_TR_GROUP2_INPUT6	Datawire output trigger reduction mux - tr_group[2].input[6].
CYHAL_TRIGGER_TR_GROUP2_INPUT7	Datawire output trigger reduction mux - tr_group[2].input[7].
CYHAL_TRIGGER_TR_GROUP2_INPUT8	Datawire output trigger reduction mux - tr_group[2].input[8].
CYHAL_TRIGGER_TR_GROUP2_INPUT9	TCPWM trigger output reduction mux - tr_group[2].input[9].
CYHAL_TRIGGER_TR_GROUP2_INPUT10	TCPWM trigger output reduction mux - tr_group[2].input[10].
CYHAL_TRIGGER_TR_GROUP2_INPUT11	TCPWM trigger output reduction mux - tr_group[2].input[11].
CYHAL_TRIGGER_TR_GROUP2_INPUT12	TCPWM trigger output reduction mux - tr_group[2].input[12].
CYHAL_TRIGGER_TR_GROUP2_INPUT13	TCPWM trigger output reduction mux - tr_group[2].input[13].
CYHAL_TRIGGER_TR_GROUP2_INPUT14	TCPWM trigger output reduction mux - tr_group[2].input[14].
CYHAL_TRIGGER_TR_GROUP2_INPUT15	TCPWM trigger output reduction mux - tr_group[2].input[15].
CYHAL_TRIGGER_TR_GROUP2_INPUT16	TCPWM trigger output reduction mux - tr_group[2].input[16].
CYHAL_TRIGGER_TR_GROUP2_INPUT17	TCPWM trigger output reduction mux - tr_group[2].input[17].
CYHAL_TRIGGER_TR_GROUP2_INPUT18	TCPWM trigger output reduction mux - tr_group[2].input[18].
CYHAL_TRIGGER_TR_GROUP2_INPUT19	TCPWM trigger output reduction mux - tr_group[2].input[19].
CYHAL_TRIGGER_TR_GROUP2_INPUT20	TCPWM trigger output reduction mux - tr_group[2].input[20].
CYHAL_TRIGGER_TR_GROUP2_INPUT21	TCPWM trigger output reduction mux - tr_group[2].input[21].
CYHAL_TRIGGER_TR_GROUP2_INPUT22	TCPWM trigger output reduction mux - tr_group[2].input[22].
CYHAL_TRIGGER_TR_GROUP2_INPUT23	TCPWM trigger output reduction mux - tr_group[2].input[23].
CYHAL_TRIGGER_TR_GROUP2_INPUT24	TCPWM trigger output reduction mux - tr_group[2].input[24].
CYHAL_TRIGGER_TR_GROUP2_INPUT25	HSIOM Pin input reduction mux - tr_group[2].input[25].
CYHAL_TRIGGER_TR_GROUP2_INPUT26	HSIOM Pin input reduction mux - tr_group[2].input[26].
CYHAL_TRIGGER_TR_GROUP2_INPUT27	HSIOM Pin input reduction mux - tr_group[2].input[27].
CYHAL_TRIGGER_TR_GROUP2_INPUT28	HSIOM Pin input reduction mux - tr_group[2].input[28].
CYHAL_TRIGGER_TR_GROUP2_INPUT29	HSIOM Pin input reduction mux - tr_group[2].input[29].
CYHAL_TRIGGER_TR_GROUP2_INPUT30	HSIOM Pin input reduction mux - tr_group[2].input[30].
CYHAL_TRIGGER_TR_GROUP2_INPUT31	HSIOM Pin input reduction mux - tr_group[2].input[31].
CYHAL_TRIGGER_TR_GROUP2_INPUT32	HSIOM Pin input reduction mux - tr_group[2].input[32].
CYHAL_TRIGGER_TR_GROUP2_INPUT33	DMA request reduction mux - tr_group[2].input[33].
CYHAL_TRIGGER_TR_GROUP2_INPUT34	DMA request reduction mux - tr_group[2].input[34].
CYHAL_TRIGGER_TR_GROUP2_INPUT35	Trigger input reduction mux - tr_group[2].input[35].
CYHAL_TRIGGER_TR_GROUP2_INPUT36	Trigger input reduction mux - tr_group[2].input[36].
CYHAL_TRIGGER_TR_GROUP2_INPUT37	Trigger input reduction mux - tr_group[2].input[37].
CYHAL_TRIGGER_TR_GROUP2_INPUT38	Trigger input reduction mux - tr_group[2].input[38].
CYHAL_TRIGGER_TR_GROUP2_INPUT39	Trigger input reduction mux - tr_group[2].input[39].
CYHAL_TRIGGER_TR_GROUP2_INPUT40	Trigger input reduction mux - tr_group[2].input[40].
CYHAL_TRIGGER_TR_GROUP2_INPUT41	Trigger input reduction mux - tr_group[2].input[41].
CYHAL_TRIGGER_TR_GROUP2_INPUT42	Trigger input reduction mux - tr_group[2].input[42].
CYHAL_TRIGGER_TR_GROUP3_INPUT1	Datawire output trigger reduction mux - tr_group[3].input[1].
CYHAL_TRIGGER_TR_GROUP3_INPUT2	Datawire output trigger reduction mux - tr_group[3].input[2].
CYHAL_TRIGGER_TR_GROUP3_INPUT3	Datawire output trigger reduction mux - tr_group[3].input[3].
CYHAL_TRIGGER_TR_GROUP3_INPUT4	Datawire output trigger reduction mux - tr_group[3].input[4].
CYHAL_TRIGGER_TR_GROUP3_INPUT5	Datawire output trigger reduction mux - tr_group[3].input[5].
CYHAL_TRIGGER_TR_GROUP3_INPUT6	Datawire output trigger reduction mux - tr_group[3].input[6].
CYHAL_TRIGGER_TR_GROUP3_INPUT7	Datawire output trigger reduction mux - tr_group[3].input[7].
CYHAL_TRIGGER_TR_GROUP3_INPUT8	Datawire output trigger reduction mux - tr_group[3].input[8].
CYHAL_TRIGGER_TR_GROUP3_INPUT9	TCPWM trigger output reduction mux - tr_group[3].input[9].
CYHAL_TRIGGER_TR_GROUP3_INPUT10	TCPWM trigger output reduction mux - tr_group[3].input[10].
CYHAL_TRIGGER_TR_GROUP3_INPUT11	TCPWM trigger output reduction mux - tr_group[3].input[11].
CYHAL_TRIGGER_TR_GROUP3_INPUT12	TCPWM trigger output reduction mux - tr_group[3].input[12].
CYHAL_TRIGGER_TR_GROUP3_INPUT13	TCPWM trigger output reduction mux - tr_group[3].input[13].
CYHAL_TRIGGER_TR_GROUP3_INPUT14	TCPWM trigger output reduction mux - tr_group[3].input[14].
CYHAL_TRIGGER_TR_GROUP3_INPUT15	TCPWM trigger output reduction mux - tr_group[3].input[15].
CYHAL_TRIGGER_TR_GROUP3_INPUT16	TCPWM trigger output reduction mux - tr_group[3].input[16].
CYHAL_TRIGGER_TR_GROUP3_INPUT17	TCPWM trigger output reduction mux - tr_group[3].input[17].
CYHAL_TRIGGER_TR_GROUP3_INPUT18	TCPWM trigger output reduction mux - tr_group[3].input[18].
CYHAL_TRIGGER_TR_GROUP3_INPUT19	TCPWM trigger output reduction mux - tr_group[3].input[19].
CYHAL_TRIGGER_TR_GROUP3_INPUT20	TCPWM trigger output reduction mux - tr_group[3].input[20].
CYHAL_TRIGGER_TR_GROUP3_INPUT21	TCPWM trigger output reduction mux - tr_group[3].input[21].
CYHAL_TRIGGER_TR_GROUP3_INPUT22	TCPWM trigger output reduction mux - tr_group[3].input[22].
CYHAL_TRIGGER_TR_GROUP3_INPUT23	TCPWM trigger output reduction mux - tr_group[3].input[23].
CYHAL_TRIGGER_TR_GROUP3_INPUT24	TCPWM trigger output reduction mux - tr_group[3].input[24].
CYHAL_TRIGGER_TR_GROUP3_INPUT25	HSIOM Pin input reduction mux - tr_group[3].input[25].
CYHAL_TRIGGER_TR_GROUP3_INPUT26	HSIOM Pin input reduction mux - tr_group[3].input[26].
CYHAL_TRIGGER_TR_GROUP3_INPUT27	HSIOM Pin input reduction mux - tr_group[3].input[27].
CYHAL_TRIGGER_TR_GROUP3_INPUT28	HSIOM Pin input reduction mux - tr_group[3].input[28].
CYHAL_TRIGGER_TR_GROUP3_INPUT29	HSIOM Pin input reduction mux - tr_group[3].input[29].
CYHAL_TRIGGER_TR_GROUP3_INPUT30	HSIOM Pin input reduction mux - tr_group[3].input[30].
CYHAL_TRIGGER_TR_GROUP3_INPUT31	HSIOM Pin input reduction mux - tr_group[3].input[31].
CYHAL_TRIGGER_TR_GROUP3_INPUT32	HSIOM Pin input reduction mux - tr_group[3].input[32].
CYHAL_TRIGGER_TR_GROUP3_INPUT33	DMA request reduction mux - tr_group[3].input[33].
CYHAL_TRIGGER_TR_GROUP3_INPUT34	DMA request reduction mux - tr_group[3].input[34].
CYHAL_TRIGGER_TR_GROUP3_INPUT35	Trigger input reduction mux - tr_group[3].input[35].
CYHAL_TRIGGER_TR_GROUP3_INPUT36	Trigger input reduction mux - tr_group[3].input[36].
CYHAL_TRIGGER_TR_GROUP3_INPUT37	Trigger input reduction mux - tr_group[3].input[37].
CYHAL_TRIGGER_TR_GROUP3_INPUT38	Trigger input reduction mux - tr_group[3].input[38].
CYHAL_TRIGGER_TR_GROUP3_INPUT39	Trigger input reduction mux - tr_group[3].input[39].
CYHAL_TRIGGER_TR_GROUP3_INPUT40	Trigger input reduction mux - tr_group[3].input[40].
CYHAL_TRIGGER_TR_GROUP3_INPUT41	Trigger input reduction mux - tr_group[3].input[41].
CYHAL_TRIGGER_TR_GROUP3_INPUT42	Trigger input reduction mux - tr_group[3].input[42].
CYHAL_TRIGGER_TR_GROUP4_INPUT1	Datawire output trigger reduction mux - tr_group[4].input[1].
CYHAL_TRIGGER_TR_GROUP4_INPUT2	Datawire output trigger reduction mux - tr_group[4].input[2].
CYHAL_TRIGGER_TR_GROUP4_INPUT3	Datawire output trigger reduction mux - tr_group[4].input[3].
CYHAL_TRIGGER_TR_GROUP4_INPUT4	Datawire output trigger reduction mux - tr_group[4].input[4].
CYHAL_TRIGGER_TR_GROUP4_INPUT5	Datawire output trigger reduction mux - tr_group[4].input[5].
CYHAL_TRIGGER_TR_GROUP4_INPUT6	Datawire output trigger reduction mux - tr_group[4].input[6].
CYHAL_TRIGGER_TR_GROUP4_INPUT7	Datawire output trigger reduction mux - tr_group[4].input[7].
CYHAL_TRIGGER_TR_GROUP4_INPUT8	Datawire output trigger reduction mux - tr_group[4].input[8].
CYHAL_TRIGGER_TR_GROUP4_INPUT9	TCPWM trigger output reduction mux - tr_group[4].input[9].
CYHAL_TRIGGER_TR_GROUP4_INPUT10	TCPWM trigger output reduction mux - tr_group[4].input[10].
CYHAL_TRIGGER_TR_GROUP4_INPUT11	TCPWM trigger output reduction mux - tr_group[4].input[11].
CYHAL_TRIGGER_TR_GROUP4_INPUT12	TCPWM trigger output reduction mux - tr_group[4].input[12].
CYHAL_TRIGGER_TR_GROUP4_INPUT13	TCPWM trigger output reduction mux - tr_group[4].input[13].
CYHAL_TRIGGER_TR_GROUP4_INPUT14	TCPWM trigger output reduction mux - tr_group[4].input[14].
CYHAL_TRIGGER_TR_GROUP4_INPUT15	TCPWM trigger output reduction mux - tr_group[4].input[15].
CYHAL_TRIGGER_TR_GROUP4_INPUT16	TCPWM trigger output reduction mux - tr_group[4].input[16].
CYHAL_TRIGGER_TR_GROUP4_INPUT17	TCPWM trigger output reduction mux - tr_group[4].input[17].
CYHAL_TRIGGER_TR_GROUP4_INPUT18	TCPWM trigger output reduction mux - tr_group[4].input[18].
CYHAL_TRIGGER_TR_GROUP4_INPUT19	TCPWM trigger output reduction mux - tr_group[4].input[19].
CYHAL_TRIGGER_TR_GROUP4_INPUT20	TCPWM trigger output reduction mux - tr_group[4].input[20].
CYHAL_TRIGGER_TR_GROUP4_INPUT21	TCPWM trigger output reduction mux - tr_group[4].input[21].
CYHAL_TRIGGER_TR_GROUP4_INPUT22	TCPWM trigger output reduction mux - tr_group[4].input[22].
CYHAL_TRIGGER_TR_GROUP4_INPUT23	TCPWM trigger output reduction mux - tr_group[4].input[23].
CYHAL_TRIGGER_TR_GROUP4_INPUT24	TCPWM trigger output reduction mux - tr_group[4].input[24].
CYHAL_TRIGGER_TR_GROUP4_INPUT25	HSIOM Pin input reduction mux - tr_group[4].input[25].
CYHAL_TRIGGER_TR_GROUP4_INPUT26	HSIOM Pin input reduction mux - tr_group[4].input[26].
CYHAL_TRIGGER_TR_GROUP4_INPUT27	HSIOM Pin input reduction mux - tr_group[4].input[27].
CYHAL_TRIGGER_TR_GROUP4_INPUT28	HSIOM Pin input reduction mux - tr_group[4].input[28].
CYHAL_TRIGGER_TR_GROUP4_INPUT29	HSIOM Pin input reduction mux - tr_group[4].input[29].
CYHAL_TRIGGER_TR_GROUP4_INPUT30	HSIOM Pin input reduction mux - tr_group[4].input[30].
CYHAL_TRIGGER_TR_GROUP4_INPUT31	HSIOM Pin input reduction mux - tr_group[4].input[31].
CYHAL_TRIGGER_TR_GROUP4_INPUT32	HSIOM Pin input reduction mux - tr_group[4].input[32].
CYHAL_TRIGGER_TR_GROUP4_INPUT33	DMA request reduction mux - tr_group[4].input[33].
CYHAL_TRIGGER_TR_GROUP4_INPUT34	DMA request reduction mux - tr_group[4].input[34].
CYHAL_TRIGGER_TR_GROUP4_INPUT35	Trigger input reduction mux - tr_group[4].input[35].
CYHAL_TRIGGER_TR_GROUP4_INPUT36	Trigger input reduction mux - tr_group[4].input[36].
CYHAL_TRIGGER_TR_GROUP4_INPUT37	Trigger input reduction mux - tr_group[4].input[37].
CYHAL_TRIGGER_TR_GROUP4_INPUT38	Trigger input reduction mux - tr_group[4].input[38].
CYHAL_TRIGGER_TR_GROUP4_INPUT39	Trigger input reduction mux - tr_group[4].input[39].
CYHAL_TRIGGER_TR_GROUP4_INPUT40	Trigger input reduction mux - tr_group[4].input[40].
CYHAL_TRIGGER_TR_GROUP4_INPUT41	Trigger input reduction mux - tr_group[4].input[41].
CYHAL_TRIGGER_TR_GROUP4_INPUT42	Trigger input reduction mux - tr_group[4].input[42].
CYHAL_TRIGGER_TR_GROUP5_INPUT1	Datawire output trigger reduction mux - tr_group[5].input[1].
CYHAL_TRIGGER_TR_GROUP5_INPUT2	Datawire output trigger reduction mux - tr_group[5].input[2].
CYHAL_TRIGGER_TR_GROUP5_INPUT3	Datawire output trigger reduction mux - tr_group[5].input[3].
CYHAL_TRIGGER_TR_GROUP5_INPUT4	Datawire output trigger reduction mux - tr_group[5].input[4].
CYHAL_TRIGGER_TR_GROUP5_INPUT5	Datawire output trigger reduction mux - tr_group[5].input[5].
CYHAL_TRIGGER_TR_GROUP5_INPUT6	Datawire output trigger reduction mux - tr_group[5].input[6].
CYHAL_TRIGGER_TR_GROUP5_INPUT7	Datawire output trigger reduction mux - tr_group[5].input[7].
CYHAL_TRIGGER_TR_GROUP5_INPUT8	Datawire output trigger reduction mux - tr_group[5].input[8].
CYHAL_TRIGGER_TR_GROUP5_INPUT9	TCPWM trigger output reduction mux - tr_group[5].input[9].
CYHAL_TRIGGER_TR_GROUP5_INPUT10	TCPWM trigger output reduction mux - tr_group[5].input[10].
CYHAL_TRIGGER_TR_GROUP5_INPUT11	TCPWM trigger output reduction mux - tr_group[5].input[11].
CYHAL_TRIGGER_TR_GROUP5_INPUT12	TCPWM trigger output reduction mux - tr_group[5].input[12].
CYHAL_TRIGGER_TR_GROUP5_INPUT13	TCPWM trigger output reduction mux - tr_group[5].input[13].
CYHAL_TRIGGER_TR_GROUP5_INPUT14	TCPWM trigger output reduction mux - tr_group[5].input[14].
CYHAL_TRIGGER_TR_GROUP5_INPUT15	TCPWM trigger output reduction mux - tr_group[5].input[15].
CYHAL_TRIGGER_TR_GROUP5_INPUT16	TCPWM trigger output reduction mux - tr_group[5].input[16].
CYHAL_TRIGGER_TR_GROUP5_INPUT17	TCPWM trigger output reduction mux - tr_group[5].input[17].
CYHAL_TRIGGER_TR_GROUP5_INPUT18	TCPWM trigger output reduction mux - tr_group[5].input[18].
CYHAL_TRIGGER_TR_GROUP5_INPUT19	TCPWM trigger output reduction mux - tr_group[5].input[19].
CYHAL_TRIGGER_TR_GROUP5_INPUT20	TCPWM trigger output reduction mux - tr_group[5].input[20].
CYHAL_TRIGGER_TR_GROUP5_INPUT21	TCPWM trigger output reduction mux - tr_group[5].input[21].
CYHAL_TRIGGER_TR_GROUP5_INPUT22	TCPWM trigger output reduction mux - tr_group[5].input[22].
CYHAL_TRIGGER_TR_GROUP5_INPUT23	TCPWM trigger output reduction mux - tr_group[5].input[23].
CYHAL_TRIGGER_TR_GROUP5_INPUT24	TCPWM trigger output reduction mux - tr_group[5].input[24].
CYHAL_TRIGGER_TR_GROUP5_INPUT25	HSIOM Pin input reduction mux - tr_group[5].input[25].
CYHAL_TRIGGER_TR_GROUP5_INPUT26	HSIOM Pin input reduction mux - tr_group[5].input[26].
CYHAL_TRIGGER_TR_GROUP5_INPUT27	HSIOM Pin input reduction mux - tr_group[5].input[27].
CYHAL_TRIGGER_TR_GROUP5_INPUT28	HSIOM Pin input reduction mux - tr_group[5].input[28].
CYHAL_TRIGGER_TR_GROUP5_INPUT29	HSIOM Pin input reduction mux - tr_group[5].input[29].
CYHAL_TRIGGER_TR_GROUP5_INPUT30	HSIOM Pin input reduction mux - tr_group[5].input[30].
CYHAL_TRIGGER_TR_GROUP5_INPUT31	HSIOM Pin input reduction mux - tr_group[5].input[31].
CYHAL_TRIGGER_TR_GROUP5_INPUT32	HSIOM Pin input reduction mux - tr_group[5].input[32].
CYHAL_TRIGGER_TR_GROUP5_INPUT33	DMA request reduction mux - tr_group[5].input[33].
CYHAL_TRIGGER_TR_GROUP5_INPUT34	DMA request reduction mux - tr_group[5].input[34].
CYHAL_TRIGGER_TR_GROUP5_INPUT35	Trigger input reduction mux - tr_group[5].input[35].
CYHAL_TRIGGER_TR_GROUP5_INPUT36	Trigger input reduction mux - tr_group[5].input[36].
CYHAL_TRIGGER_TR_GROUP5_INPUT37	Trigger input reduction mux - tr_group[5].input[37].
CYHAL_TRIGGER_TR_GROUP5_INPUT38	Trigger input reduction mux - tr_group[5].input[38].
CYHAL_TRIGGER_TR_GROUP5_INPUT39	Trigger input reduction mux - tr_group[5].input[39].
CYHAL_TRIGGER_TR_GROUP5_INPUT40	Trigger input reduction mux - tr_group[5].input[40].
CYHAL_TRIGGER_TR_GROUP5_INPUT41	Trigger input reduction mux - tr_group[5].input[41].
CYHAL_TRIGGER_TR_GROUP5_INPUT42	Trigger input reduction mux - tr_group[5].input[42].
CYHAL_TRIGGER_TR_GROUP6_INPUT1	Datawire output trigger reduction mux - tr_group[6].input[1].
CYHAL_TRIGGER_TR_GROUP6_INPUT2	Datawire output trigger reduction mux - tr_group[6].input[2].
CYHAL_TRIGGER_TR_GROUP6_INPUT3	Datawire output trigger reduction mux - tr_group[6].input[3].
CYHAL_TRIGGER_TR_GROUP6_INPUT4	Datawire output trigger reduction mux - tr_group[6].input[4].
CYHAL_TRIGGER_TR_GROUP6_INPUT5	Datawire output trigger reduction mux - tr_group[6].input[5].
CYHAL_TRIGGER_TR_GROUP6_INPUT6	Datawire output trigger reduction mux - tr_group[6].input[6].
CYHAL_TRIGGER_TR_GROUP6_INPUT7	Datawire output trigger reduction mux - tr_group[6].input[7].
CYHAL_TRIGGER_TR_GROUP6_INPUT8	Datawire output trigger reduction mux - tr_group[6].input[8].
CYHAL_TRIGGER_TR_GROUP6_INPUT9	TCPWM trigger output reduction mux - tr_group[6].input[9].
CYHAL_TRIGGER_TR_GROUP6_INPUT10	TCPWM trigger output reduction mux - tr_group[6].input[10].
CYHAL_TRIGGER_TR_GROUP6_INPUT11	TCPWM trigger output reduction mux - tr_group[6].input[11].
CYHAL_TRIGGER_TR_GROUP6_INPUT12	TCPWM trigger output reduction mux - tr_group[6].input[12].
CYHAL_TRIGGER_TR_GROUP6_INPUT13	TCPWM trigger output reduction mux - tr_group[6].input[13].
CYHAL_TRIGGER_TR_GROUP6_INPUT14	TCPWM trigger output reduction mux - tr_group[6].input[14].
CYHAL_TRIGGER_TR_GROUP6_INPUT15	TCPWM trigger output reduction mux - tr_group[6].input[15].
CYHAL_TRIGGER_TR_GROUP6_INPUT16	TCPWM trigger output reduction mux - tr_group[6].input[16].
CYHAL_TRIGGER_TR_GROUP6_INPUT17	TCPWM trigger output reduction mux - tr_group[6].input[17].
CYHAL_TRIGGER_TR_GROUP6_INPUT18	TCPWM trigger output reduction mux - tr_group[6].input[18].
CYHAL_TRIGGER_TR_GROUP6_INPUT19	TCPWM trigger output reduction mux - tr_group[6].input[19].
CYHAL_TRIGGER_TR_GROUP6_INPUT20	TCPWM trigger output reduction mux - tr_group[6].input[20].
CYHAL_TRIGGER_TR_GROUP6_INPUT21	TCPWM trigger output reduction mux - tr_group[6].input[21].
CYHAL_TRIGGER_TR_GROUP6_INPUT22	TCPWM trigger output reduction mux - tr_group[6].input[22].
CYHAL_TRIGGER_TR_GROUP6_INPUT23	TCPWM trigger output reduction mux - tr_group[6].input[23].
CYHAL_TRIGGER_TR_GROUP6_INPUT24	TCPWM trigger output reduction mux - tr_group[6].input[24].
CYHAL_TRIGGER_TR_GROUP6_INPUT25	HSIOM Pin input reduction mux - tr_group[6].input[25].
CYHAL_TRIGGER_TR_GROUP6_INPUT26	HSIOM Pin input reduction mux - tr_group[6].input[26].
CYHAL_TRIGGER_TR_GROUP6_INPUT27	HSIOM Pin input reduction mux - tr_group[6].input[27].
CYHAL_TRIGGER_TR_GROUP6_INPUT28	HSIOM Pin input reduction mux - tr_group[6].input[28].
CYHAL_TRIGGER_TR_GROUP6_INPUT29	HSIOM Pin input reduction mux - tr_group[6].input[29].
CYHAL_TRIGGER_TR_GROUP6_INPUT30	HSIOM Pin input reduction mux - tr_group[6].input[30].
CYHAL_TRIGGER_TR_GROUP6_INPUT31	HSIOM Pin input reduction mux - tr_group[6].input[31].
CYHAL_TRIGGER_TR_GROUP6_INPUT32	HSIOM Pin input reduction mux - tr_group[6].input[32].
CYHAL_TRIGGER_TR_GROUP6_INPUT33	DMA request reduction mux - tr_group[6].input[33].
CYHAL_TRIGGER_TR_GROUP6_INPUT34	DMA request reduction mux - tr_group[6].input[34].
CYHAL_TRIGGER_TR_GROUP6_INPUT35	Trigger input reduction mux - tr_group[6].input[35].
CYHAL_TRIGGER_TR_GROUP6_INPUT36	Trigger input reduction mux - tr_group[6].input[36].
CYHAL_TRIGGER_TR_GROUP6_INPUT37	Trigger input reduction mux - tr_group[6].input[37].
CYHAL_TRIGGER_TR_GROUP6_INPUT38	Trigger input reduction mux - tr_group[6].input[38].
CYHAL_TRIGGER_TR_GROUP6_INPUT39	Trigger input reduction mux - tr_group[6].input[39].
CYHAL_TRIGGER_TR_GROUP6_INPUT40	Trigger input reduction mux - tr_group[6].input[40].
CYHAL_TRIGGER_TR_GROUP6_INPUT41	Trigger input reduction mux - tr_group[6].input[41].
CYHAL_TRIGGER_TR_GROUP6_INPUT42	Trigger input reduction mux - tr_group[6].input[42].
CYHAL_TRIGGER_TR_GROUP7_INPUT1	Datawire output trigger reduction mux - tr_group[7].input[1].
CYHAL_TRIGGER_TR_GROUP7_INPUT2	Datawire output trigger reduction mux - tr_group[7].input[2].
CYHAL_TRIGGER_TR_GROUP7_INPUT3	Datawire output trigger reduction mux - tr_group[7].input[3].
CYHAL_TRIGGER_TR_GROUP7_INPUT4	Datawire output trigger reduction mux - tr_group[7].input[4].
CYHAL_TRIGGER_TR_GROUP7_INPUT5	Datawire output trigger reduction mux - tr_group[7].input[5].
CYHAL_TRIGGER_TR_GROUP7_INPUT6	Datawire output trigger reduction mux - tr_group[7].input[6].
CYHAL_TRIGGER_TR_GROUP7_INPUT7	Datawire output trigger reduction mux - tr_group[7].input[7].
CYHAL_TRIGGER_TR_GROUP7_INPUT8	Datawire output trigger reduction mux - tr_group[7].input[8].
CYHAL_TRIGGER_TR_GROUP7_INPUT9	TCPWM trigger output reduction mux - tr_group[7].input[9].
CYHAL_TRIGGER_TR_GROUP7_INPUT10	TCPWM trigger output reduction mux - tr_group[7].input[10].
CYHAL_TRIGGER_TR_GROUP7_INPUT11	TCPWM trigger output reduction mux - tr_group[7].input[11].
CYHAL_TRIGGER_TR_GROUP7_INPUT12	TCPWM trigger output reduction mux - tr_group[7].input[12].
CYHAL_TRIGGER_TR_GROUP7_INPUT13	TCPWM trigger output reduction mux - tr_group[7].input[13].
CYHAL_TRIGGER_TR_GROUP7_INPUT14	TCPWM trigger output reduction mux - tr_group[7].input[14].
CYHAL_TRIGGER_TR_GROUP7_INPUT15	TCPWM trigger output reduction mux - tr_group[7].input[15].
CYHAL_TRIGGER_TR_GROUP7_INPUT16	TCPWM trigger output reduction mux - tr_group[7].input[16].
CYHAL_TRIGGER_TR_GROUP7_INPUT17	TCPWM trigger output reduction mux - tr_group[7].input[17].
CYHAL_TRIGGER_TR_GROUP7_INPUT18	TCPWM trigger output reduction mux - tr_group[7].input[18].
CYHAL_TRIGGER_TR_GROUP7_INPUT19	TCPWM trigger output reduction mux - tr_group[7].input[19].
CYHAL_TRIGGER_TR_GROUP7_INPUT20	TCPWM trigger output reduction mux - tr_group[7].input[20].
CYHAL_TRIGGER_TR_GROUP7_INPUT21	TCPWM trigger output reduction mux - tr_group[7].input[21].
CYHAL_TRIGGER_TR_GROUP7_INPUT22	TCPWM trigger output reduction mux - tr_group[7].input[22].
CYHAL_TRIGGER_TR_GROUP7_INPUT23	TCPWM trigger output reduction mux - tr_group[7].input[23].
CYHAL_TRIGGER_TR_GROUP7_INPUT24	TCPWM trigger output reduction mux - tr_group[7].input[24].
CYHAL_TRIGGER_TR_GROUP7_INPUT25	HSIOM Pin input reduction mux - tr_group[7].input[25].
CYHAL_TRIGGER_TR_GROUP7_INPUT26	HSIOM Pin input reduction mux - tr_group[7].input[26].
CYHAL_TRIGGER_TR_GROUP7_INPUT27	HSIOM Pin input reduction mux - tr_group[7].input[27].
CYHAL_TRIGGER_TR_GROUP7_INPUT28	HSIOM Pin input reduction mux - tr_group[7].input[28].
CYHAL_TRIGGER_TR_GROUP7_INPUT29	HSIOM Pin input reduction mux - tr_group[7].input[29].
CYHAL_TRIGGER_TR_GROUP7_INPUT30	HSIOM Pin input reduction mux - tr_group[7].input[30].
CYHAL_TRIGGER_TR_GROUP7_INPUT31	HSIOM Pin input reduction mux - tr_group[7].input[31].
CYHAL_TRIGGER_TR_GROUP7_INPUT32	HSIOM Pin input reduction mux - tr_group[7].input[32].
CYHAL_TRIGGER_TR_GROUP7_INPUT33	DMA request reduction mux - tr_group[7].input[33].
CYHAL_TRIGGER_TR_GROUP7_INPUT34	DMA request reduction mux - tr_group[7].input[34].
CYHAL_TRIGGER_TR_GROUP7_INPUT35	Trigger input reduction mux - tr_group[7].input[35].
CYHAL_TRIGGER_TR_GROUP7_INPUT36	Trigger input reduction mux - tr_group[7].input[36].
CYHAL_TRIGGER_TR_GROUP7_INPUT37	Trigger input reduction mux - tr_group[7].input[37].
CYHAL_TRIGGER_TR_GROUP7_INPUT38	Trigger input reduction mux - tr_group[7].input[38].
CYHAL_TRIGGER_TR_GROUP7_INPUT39	Trigger input reduction mux - tr_group[7].input[39].
CYHAL_TRIGGER_TR_GROUP7_INPUT40	Trigger input reduction mux - tr_group[7].input[40].
CYHAL_TRIGGER_TR_GROUP7_INPUT41	Trigger input reduction mux - tr_group[7].input[41].
CYHAL_TRIGGER_TR_GROUP7_INPUT42	Trigger input reduction mux - tr_group[7].input[42].
CYHAL_TRIGGER_TR_GROUP8_INPUT1	Datawire output trigger reduction mux - tr_group[8].input[1].
CYHAL_TRIGGER_TR_GROUP8_INPUT2	Datawire output trigger reduction mux - tr_group[8].input[2].
CYHAL_TRIGGER_TR_GROUP8_INPUT3	Datawire output trigger reduction mux - tr_group[8].input[3].
CYHAL_TRIGGER_TR_GROUP8_INPUT4	Datawire output trigger reduction mux - tr_group[8].input[4].
CYHAL_TRIGGER_TR_GROUP8_INPUT5	Datawire output trigger reduction mux - tr_group[8].input[5].
CYHAL_TRIGGER_TR_GROUP8_INPUT6	Datawire output trigger reduction mux - tr_group[8].input[6].
CYHAL_TRIGGER_TR_GROUP8_INPUT7	Datawire output trigger reduction mux - tr_group[8].input[7].
CYHAL_TRIGGER_TR_GROUP8_INPUT8	Datawire output trigger reduction mux - tr_group[8].input[8].
CYHAL_TRIGGER_TR_GROUP8_INPUT9	TCPWM trigger output reduction mux - tr_group[8].input[9].
CYHAL_TRIGGER_TR_GROUP8_INPUT10	TCPWM trigger output reduction mux - tr_group[8].input[10].
CYHAL_TRIGGER_TR_GROUP8_INPUT11	TCPWM trigger output reduction mux - tr_group[8].input[11].
CYHAL_TRIGGER_TR_GROUP8_INPUT12	TCPWM trigger output reduction mux - tr_group[8].input[12].
CYHAL_TRIGGER_TR_GROUP8_INPUT13	TCPWM trigger output reduction mux - tr_group[8].input[13].
CYHAL_TRIGGER_TR_GROUP8_INPUT14	TCPWM trigger output reduction mux - tr_group[8].input[14].
CYHAL_TRIGGER_TR_GROUP8_INPUT15	TCPWM trigger output reduction mux - tr_group[8].input[15].
CYHAL_TRIGGER_TR_GROUP8_INPUT16	TCPWM trigger output reduction mux - tr_group[8].input[16].
CYHAL_TRIGGER_TR_GROUP8_INPUT17	TCPWM trigger output reduction mux - tr_group[8].input[17].
CYHAL_TRIGGER_TR_GROUP8_INPUT18	TCPWM trigger output reduction mux - tr_group[8].input[18].
CYHAL_TRIGGER_TR_GROUP8_INPUT19	TCPWM trigger output reduction mux - tr_group[8].input[19].
CYHAL_TRIGGER_TR_GROUP8_INPUT20	TCPWM trigger output reduction mux - tr_group[8].input[20].
CYHAL_TRIGGER_TR_GROUP8_INPUT21	TCPWM trigger output reduction mux - tr_group[8].input[21].
CYHAL_TRIGGER_TR_GROUP8_INPUT22	TCPWM trigger output reduction mux - tr_group[8].input[22].
CYHAL_TRIGGER_TR_GROUP8_INPUT23	TCPWM trigger output reduction mux - tr_group[8].input[23].
CYHAL_TRIGGER_TR_GROUP8_INPUT24	TCPWM trigger output reduction mux - tr_group[8].input[24].
CYHAL_TRIGGER_TR_GROUP8_INPUT25	HSIOM Pin input reduction mux - tr_group[8].input[25].
CYHAL_TRIGGER_TR_GROUP8_INPUT26	HSIOM Pin input reduction mux - tr_group[8].input[26].
CYHAL_TRIGGER_TR_GROUP8_INPUT27	HSIOM Pin input reduction mux - tr_group[8].input[27].
CYHAL_TRIGGER_TR_GROUP8_INPUT28	HSIOM Pin input reduction mux - tr_group[8].input[28].
CYHAL_TRIGGER_TR_GROUP8_INPUT29	HSIOM Pin input reduction mux - tr_group[8].input[29].
CYHAL_TRIGGER_TR_GROUP8_INPUT30	HSIOM Pin input reduction mux - tr_group[8].input[30].
CYHAL_TRIGGER_TR_GROUP8_INPUT31	HSIOM Pin input reduction mux - tr_group[8].input[31].
CYHAL_TRIGGER_TR_GROUP8_INPUT32	HSIOM Pin input reduction mux - tr_group[8].input[32].
CYHAL_TRIGGER_TR_GROUP8_INPUT33	DMA request reduction mux - tr_group[8].input[33].
CYHAL_TRIGGER_TR_GROUP8_INPUT34	DMA request reduction mux - tr_group[8].input[34].
CYHAL_TRIGGER_TR_GROUP8_INPUT35	Trigger input reduction mux - tr_group[8].input[35].
CYHAL_TRIGGER_TR_GROUP8_INPUT36	Trigger input reduction mux - tr_group[8].input[36].
CYHAL_TRIGGER_TR_GROUP8_INPUT37	Trigger input reduction mux - tr_group[8].input[37].
CYHAL_TRIGGER_TR_GROUP8_INPUT38	Trigger input reduction mux - tr_group[8].input[38].
CYHAL_TRIGGER_TR_GROUP8_INPUT39	Trigger input reduction mux - tr_group[8].input[39].
CYHAL_TRIGGER_TR_GROUP8_INPUT40	Trigger input reduction mux - tr_group[8].input[40].
CYHAL_TRIGGER_TR_GROUP8_INPUT41	Trigger input reduction mux - tr_group[8].input[41].
CYHAL_TRIGGER_TR_GROUP8_INPUT42	Trigger input reduction mux - tr_group[8].input[42].
CYHAL_TRIGGER_UDB_TR_DW_ACK0	Datawire output trigger reduction mux - udb.tr_dw_ack[0].
CYHAL_TRIGGER_UDB_TR_DW_ACK1	Datawire output trigger reduction mux - udb.tr_dw_ack[1].
CYHAL_TRIGGER_UDB_TR_DW_ACK2	Datawire output trigger reduction mux - udb.tr_dw_ack[2].
CYHAL_TRIGGER_UDB_TR_DW_ACK3	Datawire output trigger reduction mux - udb.tr_dw_ack[3].
CYHAL_TRIGGER_UDB_TR_DW_ACK4	Datawire output trigger reduction mux - udb.tr_dw_ack[4].
CYHAL_TRIGGER_UDB_TR_DW_ACK5	Datawire output trigger reduction mux - udb.tr_dw_ack[5].
CYHAL_TRIGGER_UDB_TR_DW_ACK6	Datawire output trigger reduction mux - udb.tr_dw_ack[6].
CYHAL_TRIGGER_UDB_TR_DW_ACK7	Datawire output trigger reduction mux - udb.tr_dw_ack[7].
CYHAL_TRIGGER_UDB_TR_IN0	UDB trigger multiplexer - udb.tr_in[0].
CYHAL_TRIGGER_UDB_TR_IN1	UDB trigger multiplexer - udb.tr_in[1].
CYHAL_TRIGGER_USB_DMA_BURSTEND0	USB DMA burstend multiplexer - usb.dma_burstend[0].
CYHAL_TRIGGER_USB_DMA_BURSTEND1	USB DMA burstend multiplexer - usb.dma_burstend[1].
CYHAL_TRIGGER_USB_DMA_BURSTEND2	USB DMA burstend multiplexer - usb.dma_burstend[2].
CYHAL_TRIGGER_USB_DMA_BURSTEND3	USB DMA burstend multiplexer - usb.dma_burstend[3].
CYHAL_TRIGGER_USB_DMA_BURSTEND4	USB DMA burstend multiplexer - usb.dma_burstend[4].
CYHAL_TRIGGER_USB_DMA_BURSTEND5	USB DMA burstend multiplexer - usb.dma_burstend[5].
CYHAL_TRIGGER_USB_DMA_BURSTEND6	USB DMA burstend multiplexer - usb.dma_burstend[6].
CYHAL_TRIGGER_USB_DMA_BURSTEND7	USB DMA burstend multiplexer - usb.dma_burstend[7].