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Hardware Abstraction Layer (HAL)
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Hardware Abstraction Layer (HAL)
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In CAT1 & CAT2 (PSoC™ 6/4), each GPIO port has a single IRQ line. Hence, there can only be a single interrupt handler and priority set at the hardware level. The HAL tracks any interrupt handler that is registered through cyhal_gpio_register_callback separately so it can run the appropriate pin specific callback anyway. However, the HAL will take over the interrupt for the port. Additionally, it cannot do anything about the priority and all pins on the port will share the last priority set via cyhal_gpio_enable_event. for a specific pin on a port will apply to the all the pins in that pin's port. If multiple pins on the same port are set at different priorities, the priority that the last pin is set to will be applied to all pins used on that port.
In CAT1 & CAT2 (PSoC™ 6/4) only a subset of pins available on a board are connected to input triggers. Another subset is connected to output triggers. Check the appropriate file for your board in pin_packages/ to determine what pins can be used. A particular pin can have 0 or 1 input triggers and 0 or 1 output triggers. Input triggers to a pin are used to clear/set the GPIO pins output. An output trigger on a pin is activated when the pins GPIO input is set.