TVIIBE1M 64-LQFP

General Description

Pin definitions and connections specific to the TVIIBE1M 64-LQFP package.

Data Structures
struct	cyhal_resource_pin_mapping_t
	Represents an association between a pin and a resource. More...

Macros
#define	CYHAL_GET_GPIO(port, pin)   ((((uint8_t)(port)) << 3U) + ((uint8_t)(pin)))
	Gets a pin definition from the provided port and pin numbers.
#define	CYHAL_GET_PIN(pin)   ((uint8_t)(((uint8_t)pin) & 0x07U))
	Macro that, given a gpio, will extract the pin number.
#define	CYHAL_GET_PORT(pin)   ((uint8_t)(((uint8_t)pin) >> 3U))
	Macro that, given a gpio, will extract the port number.
#define	CYHAL_PIN_MAP_DRIVE_MODE_CANFD_TTCAN_RX   (CY_GPIO_DM_HIGHZ)
	Indicates that a pin map exists for canfd_ttcan_rx.
#define	CYHAL_PIN_MAP_DRIVE_MODE_CANFD_TTCAN_TX   (CY_GPIO_DM_STRONG_IN_OFF)
	Indicates that a pin map exists for canfd_ttcan_tx.
#define	CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_CAL_SUP_NZ   (CY_GPIO_DM_STRONG_IN_OFF)
	Indicates that a pin map exists for cpuss_cal_sup_nz.
#define	CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_CLK_FM_PUMP   (CY_GPIO_DM_STRONG_IN_OFF)
	Indicates that a pin map exists for cpuss_clk_fm_pump.
#define	CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_FAULT_OUT   (CY_GPIO_DM_STRONG_IN_OFF)
	Indicates that a pin map exists for cpuss_fault_out.
#define	CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_SWJ_SWCLK_TCLK   (CY_GPIO_DM_PULLDOWN)
	Indicates that a pin map exists for cpuss_swj_swclk_tclk.
#define	CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_SWJ_SWDIO_TMS   (CY_GPIO_DM_PULLUP)
	Indicates that a pin map exists for cpuss_swj_swdio_tms.
#define	CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_SWJ_SWDOE_TDI   (CY_GPIO_DM_PULLUP)
	Indicates that a pin map exists for cpuss_swj_swdoe_tdi.
#define	CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_SWJ_SWO_TDO   (CY_GPIO_DM_STRONG_IN_OFF)
	Indicates that a pin map exists for cpuss_swj_swo_tdo.
#define	CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_SWJ_TRSTN   (CY_GPIO_DM_PULLUP)
	Indicates that a pin map exists for cpuss_swj_trstn.
#define	CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_TRACE_CLOCK   (CY_GPIO_DM_STRONG_IN_OFF)
	Indicates that a pin map exists for cpuss_trace_clock.
#define	CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_TRACE_DATA   (CY_GPIO_DM_STRONG_IN_OFF)
	Indicates that a pin map exists for cpuss_trace_data.
#define	CYHAL_PIN_MAP_DRIVE_MODE_LIN_LIN_EN   (CY_GPIO_DM_HIGHZ)
	Indicates that a pin map exists for lin_lin_en.
#define	CYHAL_PIN_MAP_DRIVE_MODE_LIN_LIN_RX   (CY_GPIO_DM_HIGHZ)
	Indicates that a pin map exists for lin_lin_rx.
#define	CYHAL_PIN_MAP_DRIVE_MODE_LIN_LIN_TX   (CY_GPIO_DM_STRONG_IN_OFF)
	Indicates that a pin map exists for lin_lin_tx.
#define	CYHAL_PIN_MAP_DRIVE_MODE_PASS_SAR_EXT_MUX_EN   (CY_GPIO_DM_STRONG_IN_OFF)
	Indicates that a pin map exists for pass_sar_ext_mux_en.
#define	CYHAL_PIN_MAP_DRIVE_MODE_PASS_SAR_EXT_MUX_SEL   (CY_GPIO_DM_STRONG_IN_OFF)
	Indicates that a pin map exists for pass_sar_ext_mux_sel.
#define	CYHAL_PIN_MAP_DRIVE_MODE_PASS_SARMUX_PADS   (CY_GPIO_DM_ANALOG)
	Indicates that a pin map exists for pass_sarmux_pads.
#define	CYHAL_PIN_MAP_DRIVE_MODE_PERI_TR_IO_INPUT   (CY_GPIO_DM_HIGHZ)
	Indicates that a pin map exists for peri_tr_io_input.
#define	CYHAL_PIN_MAP_DRIVE_MODE_PERI_TR_IO_OUTPUT   (CY_GPIO_DM_HIGHZ)
	Indicates that a pin map exists for peri_tr_io_output.
#define	CYHAL_PIN_MAP_DRIVE_MODE_SCB_I2C_SCL   (CY_GPIO_DM_OD_DRIVESLOW)
	Indicates that a pin map exists for scb_i2c_scl.
#define	CYHAL_PIN_MAP_DRIVE_MODE_SCB_I2C_SDA   (CY_GPIO_DM_OD_DRIVESLOW)
	Indicates that a pin map exists for scb_i2c_sda.
#define	CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_CLK   (CY_GPIO_DM_STRONG_IN_OFF)
	Indicates that a pin map exists for scb_spi_m_clk.
#define	CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_MISO   (CY_GPIO_DM_HIGHZ)
	Indicates that a pin map exists for scb_spi_m_miso.
#define	CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_MOSI   (CY_GPIO_DM_STRONG_IN_OFF)
	Indicates that a pin map exists for scb_spi_m_mosi.
#define	CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_SELECT0   (CY_GPIO_DM_STRONG_IN_OFF)
	Indicates that a pin map exists for scb_spi_m_select0.
#define	CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_SELECT1   (CY_GPIO_DM_STRONG_IN_OFF)
	Indicates that a pin map exists for scb_spi_m_select1.
#define	CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_SELECT2   (CY_GPIO_DM_STRONG_IN_OFF)
	Indicates that a pin map exists for scb_spi_m_select2.
#define	CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_SELECT3   (CY_GPIO_DM_STRONG_IN_OFF)
	Indicates that a pin map exists for scb_spi_m_select3.
#define	CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_CLK   (CY_GPIO_DM_HIGHZ)
	Indicates that a pin map exists for scb_spi_s_clk.
#define	CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_MISO   (CY_GPIO_DM_STRONG_IN_OFF)
	Indicates that a pin map exists for scb_spi_s_miso.
#define	CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_MOSI   (CY_GPIO_DM_HIGHZ)
	Indicates that a pin map exists for scb_spi_s_mosi.
#define	CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_SELECT0   (CY_GPIO_DM_HIGHZ)
	Indicates that a pin map exists for scb_spi_s_select0.
#define	CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_SELECT1   (CY_GPIO_DM_HIGHZ)
	Indicates that a pin map exists for scb_spi_s_select1.
#define	CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_SELECT2   (CY_GPIO_DM_HIGHZ)
	Indicates that a pin map exists for scb_spi_s_select2.
#define	CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_SELECT3   (CY_GPIO_DM_HIGHZ)
	Indicates that a pin map exists for scb_spi_s_select3.
#define	CYHAL_PIN_MAP_DRIVE_MODE_SCB_UART_CTS   (CY_GPIO_DM_HIGHZ)
	Indicates that a pin map exists for scb_uart_cts.
#define	CYHAL_PIN_MAP_DRIVE_MODE_SCB_UART_RTS   (CY_GPIO_DM_STRONG_IN_OFF)
	Indicates that a pin map exists for scb_uart_rts.
#define	CYHAL_PIN_MAP_DRIVE_MODE_SCB_UART_RX   (CY_GPIO_DM_HIGHZ)
	Indicates that a pin map exists for scb_uart_rx.
#define	CYHAL_PIN_MAP_DRIVE_MODE_SCB_UART_TX   (CY_GPIO_DM_STRONG_IN_OFF)
	Indicates that a pin map exists for scb_uart_tx.
#define	CYHAL_PIN_MAP_DRIVE_MODE_TCPWM_LINE   (CY_GPIO_DM_STRONG_IN_OFF)
	Indicates that a pin map exists for tcpwm_line.
#define	CYHAL_PIN_MAP_DRIVE_MODE_TCPWM_LINE_COMPL   (CY_GPIO_DM_STRONG_IN_OFF)
	Indicates that a pin map exists for tcpwm_line_compl.
#define	CYHAL_PIN_MAP_DRIVE_MODE_TCPWM_TR_ONE_CNT_IN   (CY_GPIO_DM_HIGHZ)
	Indicates that a pin map exists for tcpwm_tr_one_cnt_in.

Typedefs
typedef cyhal_gpio_tviibe1m_64_lqfp_t	cyhal_gpio_t
	Create generic name for the series/package specific type.

Enumerations
enum	cyhal_gpio_tviibe1m_64_lqfp_t {   NC = 0xFF ,   P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0) ,   P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1) ,   P0_2 = CYHAL_GET_GPIO(CYHAL_PORT_0, 2) ,   P0_3 = CYHAL_GET_GPIO(CYHAL_PORT_0, 3) ,   P2_0 = CYHAL_GET_GPIO(CYHAL_PORT_2, 0) ,   P2_1 = CYHAL_GET_GPIO(CYHAL_PORT_2, 1) ,   P5_0 = CYHAL_GET_GPIO(CYHAL_PORT_5, 0) ,   P5_1 = CYHAL_GET_GPIO(CYHAL_PORT_5, 1) ,   P6_0 = CYHAL_GET_GPIO(CYHAL_PORT_6, 0) ,   P6_1 = CYHAL_GET_GPIO(CYHAL_PORT_6, 1) ,   P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2) ,   P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3) ,   P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4) ,   P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5) ,   P6_6 = CYHAL_GET_GPIO(CYHAL_PORT_6, 6) ,   P7_0 = CYHAL_GET_GPIO(CYHAL_PORT_7, 0) ,   P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1) ,   P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2) ,   P8_0 = CYHAL_GET_GPIO(CYHAL_PORT_8, 0) ,   P8_1 = CYHAL_GET_GPIO(CYHAL_PORT_8, 1) ,   P11_0 = CYHAL_GET_GPIO(CYHAL_PORT_11, 0) ,   P11_1 = CYHAL_GET_GPIO(CYHAL_PORT_11, 1) ,   P11_2 = CYHAL_GET_GPIO(CYHAL_PORT_11, 2) ,   P12_0 = CYHAL_GET_GPIO(CYHAL_PORT_12, 0) ,   P12_1 = CYHAL_GET_GPIO(CYHAL_PORT_12, 1) ,   P13_0 = CYHAL_GET_GPIO(CYHAL_PORT_13, 0) ,   P13_1 = CYHAL_GET_GPIO(CYHAL_PORT_13, 1) ,   P13_2 = CYHAL_GET_GPIO(CYHAL_PORT_13, 2) ,   P13_3 = CYHAL_GET_GPIO(CYHAL_PORT_13, 3) ,   P14_0 = CYHAL_GET_GPIO(CYHAL_PORT_14, 0) ,   P14_1 = CYHAL_GET_GPIO(CYHAL_PORT_14, 1) ,   P14_2 = CYHAL_GET_GPIO(CYHAL_PORT_14, 2) ,   P18_0 = CYHAL_GET_GPIO(CYHAL_PORT_18, 0) ,   P18_1 = CYHAL_GET_GPIO(CYHAL_PORT_18, 1) ,   P18_3 = CYHAL_GET_GPIO(CYHAL_PORT_18, 3) ,   P18_4 = CYHAL_GET_GPIO(CYHAL_PORT_18, 4) ,   P18_5 = CYHAL_GET_GPIO(CYHAL_PORT_18, 5) ,   P18_6 = CYHAL_GET_GPIO(CYHAL_PORT_18, 6) ,   P18_7 = CYHAL_GET_GPIO(CYHAL_PORT_18, 7) ,   P21_0 = CYHAL_GET_GPIO(CYHAL_PORT_21, 0) ,   P21_1 = CYHAL_GET_GPIO(CYHAL_PORT_21, 1) ,   P21_2 = CYHAL_GET_GPIO(CYHAL_PORT_21, 2) ,   P21_3 = CYHAL_GET_GPIO(CYHAL_PORT_21, 3) ,   P22_0 = CYHAL_GET_GPIO(CYHAL_PORT_22, 0) ,   P23_3 = CYHAL_GET_GPIO(CYHAL_PORT_23, 3) ,   P23_4 = CYHAL_GET_GPIO(CYHAL_PORT_23, 4) ,   P23_5 = CYHAL_GET_GPIO(CYHAL_PORT_23, 5) ,   P23_6 = CYHAL_GET_GPIO(CYHAL_PORT_23, 6) ,   P23_7 = CYHAL_GET_GPIO(CYHAL_PORT_23, 7) }
	Definitions for all of the pins that are bonded out on in the 64-LQFP package for the TVIIBE1M series. More...

Variables
const cyhal_resource_pin_mapping_t	cyhal_pin_map_canfd_ttcan_rx [7]
	List of valid pin to peripheral connections for the canfd_ttcan_rx signal.
const cyhal_resource_pin_mapping_t	cyhal_pin_map_canfd_ttcan_tx [8]
	List of valid pin to peripheral connections for the canfd_ttcan_tx signal.
const cyhal_resource_pin_mapping_t	cyhal_pin_map_cpuss_cal_sup_nz [2]
	List of valid pin to peripheral connections for the cpuss_cal_sup_nz signal.
const cyhal_resource_pin_mapping_t	cyhal_pin_map_cpuss_clk_fm_pump [1]
	List of valid pin to peripheral connections for the cpuss_clk_fm_pump signal.
const cyhal_resource_pin_mapping_t	cyhal_pin_map_cpuss_fault_out [3]
	List of valid pin to peripheral connections for the cpuss_fault_out signal.
const cyhal_resource_pin_mapping_t	cyhal_pin_map_cpuss_swj_swclk_tclk [1]
	List of valid pin to peripheral connections for the cpuss_swj_swclk_tclk signal.
const cyhal_resource_pin_mapping_t	cyhal_pin_map_cpuss_swj_swdio_tms [1]
	List of valid pin to peripheral connections for the cpuss_swj_swdio_tms signal.
const cyhal_resource_pin_mapping_t	cyhal_pin_map_cpuss_swj_swdoe_tdi [1]
	List of valid pin to peripheral connections for the cpuss_swj_swdoe_tdi signal.
const cyhal_resource_pin_mapping_t	cyhal_pin_map_cpuss_swj_swo_tdo [1]
	List of valid pin to peripheral connections for the cpuss_swj_swo_tdo signal.
const cyhal_resource_pin_mapping_t	cyhal_pin_map_cpuss_swj_trstn [1]
	List of valid pin to peripheral connections for the cpuss_swj_trstn signal.
const cyhal_resource_pin_mapping_t	cyhal_pin_map_cpuss_trace_clock [1]
	List of valid pin to peripheral connections for the cpuss_trace_clock signal.
const cyhal_resource_pin_mapping_t	cyhal_pin_map_cpuss_trace_data [5]
	List of valid pin to peripheral connections for the cpuss_trace_data signal.
const cyhal_resource_pin_mapping_t	cyhal_pin_map_lin_lin_en [5]
	List of valid pin to peripheral connections for the lin_lin_en signal.
const cyhal_resource_pin_mapping_t	cyhal_pin_map_lin_lin_rx [8]
	List of valid pin to peripheral connections for the lin_lin_rx signal.
const cyhal_resource_pin_mapping_t	cyhal_pin_map_lin_lin_tx [7]
	List of valid pin to peripheral connections for the lin_lin_tx signal.
const cyhal_resource_pin_mapping_t	cyhal_pin_map_pass_sar_ext_mux_en [1]
	List of valid pin to peripheral connections for the pass_sar_ext_mux_en signal.
const cyhal_resource_pin_mapping_t	cyhal_pin_map_pass_sar_ext_mux_sel [3]
	List of valid pin to peripheral connections for the pass_sar_ext_mux_sel signal.
const cyhal_resource_pin_mapping_t	cyhal_pin_map_pass_sarmux_pads [27]
	List of valid pin to peripheral connections for the pass_sarmux_pads signal.
const cyhal_resource_pin_mapping_t	cyhal_pin_map_peri_tr_io_input [8]
	List of valid pin to peripheral connections for the peri_tr_io_input signal.
const cyhal_resource_pin_mapping_t	cyhal_pin_map_peri_tr_io_output [2]
	List of valid pin to peripheral connections for the peri_tr_io_output signal.
const cyhal_resource_pin_mapping_t	cyhal_pin_map_scb_i2c_scl [6]
	List of valid pin to peripheral connections for the scb_i2c_scl signal.
const cyhal_resource_pin_mapping_t	cyhal_pin_map_scb_i2c_sda [8]
	List of valid pin to peripheral connections for the scb_i2c_sda signal.
const cyhal_resource_pin_mapping_t	cyhal_pin_map_scb_spi_m_clk [5]
	List of valid pin to peripheral connections for the scb_spi_m_clk signal.
const cyhal_resource_pin_mapping_t	cyhal_pin_map_scb_spi_m_miso [8]
	List of valid pin to peripheral connections for the scb_spi_m_miso signal.
const cyhal_resource_pin_mapping_t	cyhal_pin_map_scb_spi_m_mosi [7]
	List of valid pin to peripheral connections for the scb_spi_m_mosi signal.
const cyhal_resource_pin_mapping_t	cyhal_pin_map_scb_spi_m_select0 [5]
	List of valid pin to peripheral connections for the scb_spi_m_select0 signal.
const cyhal_resource_pin_mapping_t	cyhal_pin_map_scb_spi_m_select1 [4]
	List of valid pin to peripheral connections for the scb_spi_m_select1 signal.
const cyhal_resource_pin_mapping_t	cyhal_pin_map_scb_spi_m_select2 [6]
	List of valid pin to peripheral connections for the scb_spi_m_select2 signal.
const cyhal_resource_pin_mapping_t	cyhal_pin_map_scb_spi_m_select3 [2]
	List of valid pin to peripheral connections for the scb_spi_m_select3 signal.
const cyhal_resource_pin_mapping_t	cyhal_pin_map_scb_spi_s_clk [5]
	List of valid pin to peripheral connections for the scb_spi_s_clk signal.
const cyhal_resource_pin_mapping_t	cyhal_pin_map_scb_spi_s_miso [8]
	List of valid pin to peripheral connections for the scb_spi_s_miso signal.
const cyhal_resource_pin_mapping_t	cyhal_pin_map_scb_spi_s_mosi [7]
	List of valid pin to peripheral connections for the scb_spi_s_mosi signal.
const cyhal_resource_pin_mapping_t	cyhal_pin_map_scb_spi_s_select0 [5]
	List of valid pin to peripheral connections for the scb_spi_s_select0 signal.
const cyhal_resource_pin_mapping_t	cyhal_pin_map_scb_spi_s_select1 [4]
	List of valid pin to peripheral connections for the scb_spi_s_select1 signal.
const cyhal_resource_pin_mapping_t	cyhal_pin_map_scb_spi_s_select2 [6]
	List of valid pin to peripheral connections for the scb_spi_s_select2 signal.
const cyhal_resource_pin_mapping_t	cyhal_pin_map_scb_spi_s_select3 [2]
	List of valid pin to peripheral connections for the scb_spi_s_select3 signal.
const cyhal_resource_pin_mapping_t	cyhal_pin_map_scb_uart_cts [5]
	List of valid pin to peripheral connections for the scb_uart_cts signal.
const cyhal_resource_pin_mapping_t	cyhal_pin_map_scb_uart_rts [5]
	List of valid pin to peripheral connections for the scb_uart_rts signal.
const cyhal_resource_pin_mapping_t	cyhal_pin_map_scb_uart_rx [8]
	List of valid pin to peripheral connections for the scb_uart_rx signal.
const cyhal_resource_pin_mapping_t	cyhal_pin_map_scb_uart_tx [7]
	List of valid pin to peripheral connections for the scb_uart_tx signal.
const cyhal_resource_pin_mapping_t	cyhal_pin_map_tcpwm_line [49]
	List of valid pin to peripheral connections for the tcpwm_line signal.
const cyhal_resource_pin_mapping_t	cyhal_pin_map_tcpwm_line_compl [50]
	List of valid pin to peripheral connections for the tcpwm_line_compl signal.
const cyhal_resource_pin_mapping_t	cyhal_pin_map_tcpwm_tr_one_cnt_in [92]
	List of valid pin to peripheral connections for the tcpwm_tr_one_cnt_in signal.

---

Data Structure Documentation

cyhal_resource_pin_mapping_t

struct cyhal_resource_pin_mapping_t

Data Fields
uint8_t	block_num	The block number of the resource with this connection.
uint8_t	channel_num	The channel number of the block with this connection.
cyhal_gpio_t	pin	The GPIO pin the connection is with.
en_hsiom_sel_t	hsiom	The HSIOM configuration value.

Enumeration Type Documentation

cyhal_gpio_tviibe1m_64_lqfp_t

enum cyhal_gpio_tviibe1m_64_lqfp_t

Definitions for all of the pins that are bonded out on in the 64-LQFP package for the TVIIBE1M series.

Enumerator
NC	No Connect/Invalid Pin.
P0_0	Port 0 Pin 0.
P0_1	Port 0 Pin 1.
P0_2	Port 0 Pin 2.
P0_3	Port 0 Pin 3.
P2_0	Port 2 Pin 0.
P2_1	Port 2 Pin 1.
P5_0	Port 5 Pin 0.
P5_1	Port 5 Pin 1.
P6_0	Port 6 Pin 0.
P6_1	Port 6 Pin 1.
P6_2	Port 6 Pin 2.
P6_3	Port 6 Pin 3.
P6_4	Port 6 Pin 4.
P6_5	Port 6 Pin 5.
P6_6	Port 6 Pin 6.
P7_0	Port 7 Pin 0.
P7_1	Port 7 Pin 1.
P7_2	Port 7 Pin 2.
P8_0	Port 8 Pin 0.
P8_1	Port 8 Pin 1.
P11_0	Port 11 Pin 0.
P11_1	Port 11 Pin 1.
P11_2	Port 11 Pin 2.
P12_0	Port 12 Pin 0.
P12_1	Port 12 Pin 1.
P13_0	Port 13 Pin 0.
P13_1	Port 13 Pin 1.
P13_2	Port 13 Pin 2.
P13_3	Port 13 Pin 3.
P14_0	Port 14 Pin 0.
P14_1	Port 14 Pin 1.
P14_2	Port 14 Pin 2.
P18_0	Port 18 Pin 0.
P18_1	Port 18 Pin 1.
P18_3	Port 18 Pin 3.
P18_4	Port 18 Pin 4.
P18_5	Port 18 Pin 5.
P18_6	Port 18 Pin 6.
P18_7	Port 18 Pin 7.
P21_0	Port 21 Pin 0.
P21_1	Port 21 Pin 1.
P21_2	Port 21 Pin 2.
P21_3	Port 21 Pin 3.
P22_0	Port 22 Pin 0.
P23_3	Port 23 Pin 3.
P23_4	Port 23 Pin 4.
P23_5	Port 23 Pin 5.
P23_6	Port 23 Pin 6.
P23_7	Port 23 Pin 7.