There are two situations where system interrupts do not correlate 1:1 to CPU interrupts.

("System interrupt" refers to a signal on a peripheral that can request an interrupt. "CPU interrupt" refers to an IRQ input line on the cpu). Each has a different potential impact on application behavior.

• When running on the CM0+ on PSoC 6 S1 devices, there are 32 CPU interrupts available. Each CPU interrupt can be associatedd with exactly one system interrupt. This means that if the application attempts to initialize more than 32 HAL driver instances which require unique interrupt handlers, the initialization will fail because there are no CPU interrupt slots remaining.
• When running on the CM0+ on all other CAT1 devices, or when running on the CM7 on CAT3 devices, there are 8 CPU interrupts. Any system interrupt can be assigned to any CPU interrupt. In the event that more than one system interrupt fires at the same time for a given CPU interrupt, the interrupts are serviced in ascending numerical order (see the device datasheet for numeric IRQ values). This means that the above error case where all CPU interrupts have been consumed does not apply. The HAL automatically divides the system interrupts across the CPU interrupts. However, it is only possible to assign one priority per CPU interrupt, even though the HAL APIs expose the interrupt priority per system interrupt. The CAT1 HAL handles this situation by tracking the requested priority for each system interrupt, then setting the priority for each CPU interrupt as the lowest (i.e. most important) value requested across all of its associated system interrupts.