PSOC6_03

General Description

Trigger connections for psoc6_03.

PSoC™ 6S3 Triggers:

Macros
#define	CYHAL_TRIGGER_CPUSS_ZERO   (CYHAL_TRIGGER_CPUSS_ZERO_LEVEL)
	Deprecated defines for signals that can be either level or edge. More...
#define	CYHAL_TRIGGER_CSD_DSI_SENSE_OUT   (CYHAL_TRIGGER_CSD_DSI_SENSE_OUT_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_CSD_TR_ADC_DONE   (CYHAL_TRIGGER_CSD_TR_ADC_DONE_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_PERI_TR_IO_INPUT0   (CYHAL_TRIGGER_PERI_TR_IO_INPUT0_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_PERI_TR_IO_INPUT1   (CYHAL_TRIGGER_PERI_TR_IO_INPUT1_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_PERI_TR_IO_INPUT2   (CYHAL_TRIGGER_PERI_TR_IO_INPUT2_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_PERI_TR_IO_INPUT3   (CYHAL_TRIGGER_PERI_TR_IO_INPUT3_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_PERI_TR_IO_INPUT4   (CYHAL_TRIGGER_PERI_TR_IO_INPUT4_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_PERI_TR_IO_INPUT5   (CYHAL_TRIGGER_PERI_TR_IO_INPUT5_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_PERI_TR_IO_INPUT6   (CYHAL_TRIGGER_PERI_TR_IO_INPUT6_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_PERI_TR_IO_INPUT7   (CYHAL_TRIGGER_PERI_TR_IO_INPUT7_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_PERI_TR_IO_INPUT8   (CYHAL_TRIGGER_PERI_TR_IO_INPUT8_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_PERI_TR_IO_INPUT9   (CYHAL_TRIGGER_PERI_TR_IO_INPUT9_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_PERI_TR_IO_INPUT10   (CYHAL_TRIGGER_PERI_TR_IO_INPUT10_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_PERI_TR_IO_INPUT11   (CYHAL_TRIGGER_PERI_TR_IO_INPUT11_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_PERI_TR_IO_INPUT12   (CYHAL_TRIGGER_PERI_TR_IO_INPUT12_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_PERI_TR_IO_INPUT13   (CYHAL_TRIGGER_PERI_TR_IO_INPUT13_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_PERI_TR_IO_INPUT14   (CYHAL_TRIGGER_PERI_TR_IO_INPUT14_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_PERI_TR_IO_INPUT15   (CYHAL_TRIGGER_PERI_TR_IO_INPUT15_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_PERI_TR_IO_INPUT16   (CYHAL_TRIGGER_PERI_TR_IO_INPUT16_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_PERI_TR_IO_INPUT17   (CYHAL_TRIGGER_PERI_TR_IO_INPUT17_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_PERI_TR_IO_INPUT18   (CYHAL_TRIGGER_PERI_TR_IO_INPUT18_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_PERI_TR_IO_INPUT19   (CYHAL_TRIGGER_PERI_TR_IO_INPUT19_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_PERI_TR_IO_INPUT20   (CYHAL_TRIGGER_PERI_TR_IO_INPUT20_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_PERI_TR_IO_INPUT21   (CYHAL_TRIGGER_PERI_TR_IO_INPUT21_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_PERI_TR_IO_INPUT22   (CYHAL_TRIGGER_PERI_TR_IO_INPUT22_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_PERI_TR_IO_INPUT23   (CYHAL_TRIGGER_PERI_TR_IO_INPUT23_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_PERI_TR_IO_INPUT24   (CYHAL_TRIGGER_PERI_TR_IO_INPUT24_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_PERI_TR_IO_INPUT25   (CYHAL_TRIGGER_PERI_TR_IO_INPUT25_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.

Typedefs
typedef cyhal_trigger_source_psoc6_03_t	cyhal_source_t
	Typedef from device family specific trigger source to generic trigger source.
typedef cyhal_trigger_dest_psoc6_03_t	cyhal_dest_t
	Typedef from device family specific trigger dest to generic trigger dest.

Enumerations
enum	cyhal_trigger_source_psoc6_03_t {   CYHAL_TRIGGER_CPUSS_ZERO_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_ZERO, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CPUSS_ZERO_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_ZERO, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_CANFD0_TR_DBG_DMA_REQ0 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD0_TR_DBG_DMA_REQ0, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_CANFD0_TR_FIFO00 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD0_TR_FIFO00, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_CANFD0_TR_FIFO10 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD0_TR_FIFO10, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_CANFD0_TR_TMP_RTP_OUT0 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD0_TR_TMP_RTP_OUT0, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CPUSS_CTI_TR_OUT0 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_CTI_TR_OUT0, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CPUSS_CTI_TR_OUT1 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_CTI_TR_OUT1, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT0 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT0, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT1 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT1, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CPUSS_DW0_TR_OUT0 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT0, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CPUSS_DW0_TR_OUT1 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT1, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CPUSS_DW0_TR_OUT2 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT2, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CPUSS_DW0_TR_OUT3 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT3, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CPUSS_DW0_TR_OUT4 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT4, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CPUSS_DW0_TR_OUT5 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT5, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CPUSS_DW0_TR_OUT6 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT6, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CPUSS_DW0_TR_OUT7 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT7, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CPUSS_DW0_TR_OUT8 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT8, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CPUSS_DW0_TR_OUT9 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT9, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CPUSS_DW0_TR_OUT10 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT10, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CPUSS_DW0_TR_OUT11 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT11, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CPUSS_DW0_TR_OUT12 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT12, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CPUSS_DW0_TR_OUT13 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT13, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CPUSS_DW0_TR_OUT14 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT14, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CPUSS_DW0_TR_OUT15 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT15, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CPUSS_DW0_TR_OUT16 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT16, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CPUSS_DW0_TR_OUT17 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT17, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CPUSS_DW0_TR_OUT18 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT18, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CPUSS_DW0_TR_OUT19 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT19, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CPUSS_DW0_TR_OUT20 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT20, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CPUSS_DW0_TR_OUT21 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT21, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CPUSS_DW0_TR_OUT22 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT22, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CPUSS_DW0_TR_OUT23 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT23, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CPUSS_DW0_TR_OUT24 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT24, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CPUSS_DW0_TR_OUT25 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT25, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CPUSS_DW0_TR_OUT26 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT26, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CPUSS_DW0_TR_OUT27 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT27, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CPUSS_DW0_TR_OUT28 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT28, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CPUSS_DW1_TR_OUT0 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT0, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CPUSS_DW1_TR_OUT1 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT1, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CPUSS_DW1_TR_OUT2 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT2, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CPUSS_DW1_TR_OUT3 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT3, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CPUSS_DW1_TR_OUT4 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT4, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CPUSS_DW1_TR_OUT5 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT5, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CPUSS_DW1_TR_OUT6 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT6, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CPUSS_DW1_TR_OUT7 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT7, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CPUSS_DW1_TR_OUT8 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT8, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CPUSS_DW1_TR_OUT9 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT9, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CPUSS_DW1_TR_OUT10 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT10, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CPUSS_DW1_TR_OUT11 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT11, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CPUSS_DW1_TR_OUT12 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT12, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CPUSS_DW1_TR_OUT13 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT13, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CPUSS_DW1_TR_OUT14 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT14, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CPUSS_DW1_TR_OUT15 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT15, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CPUSS_DW1_TR_OUT16 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT16, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CPUSS_DW1_TR_OUT17 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT17, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CPUSS_DW1_TR_OUT18 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT18, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CPUSS_DW1_TR_OUT19 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT19, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CPUSS_DW1_TR_OUT20 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT20, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CPUSS_DW1_TR_OUT21 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT21, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CPUSS_DW1_TR_OUT22 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT22, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CPUSS_DW1_TR_OUT23 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT23, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CPUSS_DW1_TR_OUT24 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT24, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CPUSS_DW1_TR_OUT25 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT25, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CPUSS_DW1_TR_OUT26 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT26, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CPUSS_DW1_TR_OUT27 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT27, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CPUSS_DW1_TR_OUT28 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT28, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CPUSS_DW1_TR_OUT29 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT29, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CPUSS_DW1_TR_OUT30 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT30, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CPUSS_DW1_TR_OUT31 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT31, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CPUSS_TR_FAULT0 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_TR_FAULT0, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CPUSS_TR_FAULT1 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_TR_FAULT1, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CSD_DSI_SAMPLE_OUT = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CSD_DSI_SAMPLE_OUT, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CSD_DSI_SENSE_OUT_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CSD_DSI_SENSE_OUT, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CSD_DSI_SENSE_OUT_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CSD_DSI_SENSE_OUT, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_CSD_TR_ADC_DONE_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CSD_TR_ADC_DONE, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CSD_TR_ADC_DONE_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CSD_TR_ADC_DONE, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_LPCOMP_DSI_COMP0 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_LPCOMP_DSI_COMP0, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_LPCOMP_DSI_COMP1 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_LPCOMP_DSI_COMP1, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_PASS_TR_SAR_OUT = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS_TR_SAR_OUT, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_PERI_TR_IO_INPUT0_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT0, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_PERI_TR_IO_INPUT0_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT0, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_PERI_TR_IO_INPUT1_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT1, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_PERI_TR_IO_INPUT1_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT1, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_PERI_TR_IO_INPUT2_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT2, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_PERI_TR_IO_INPUT2_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT2, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_PERI_TR_IO_INPUT3_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT3, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_PERI_TR_IO_INPUT3_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT3, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_PERI_TR_IO_INPUT4_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT4, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_PERI_TR_IO_INPUT4_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT4, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_PERI_TR_IO_INPUT5_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT5, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_PERI_TR_IO_INPUT5_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT5, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_PERI_TR_IO_INPUT6_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT6, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_PERI_TR_IO_INPUT6_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT6, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_PERI_TR_IO_INPUT7_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT7, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_PERI_TR_IO_INPUT7_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT7, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_PERI_TR_IO_INPUT8_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT8, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_PERI_TR_IO_INPUT8_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT8, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_PERI_TR_IO_INPUT9_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT9, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_PERI_TR_IO_INPUT9_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT9, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_PERI_TR_IO_INPUT10_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT10, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_PERI_TR_IO_INPUT10_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT10, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_PERI_TR_IO_INPUT11_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT11, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_PERI_TR_IO_INPUT11_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT11, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_PERI_TR_IO_INPUT12_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT12, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_PERI_TR_IO_INPUT12_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT12, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_PERI_TR_IO_INPUT13_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT13, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_PERI_TR_IO_INPUT13_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT13, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_PERI_TR_IO_INPUT14_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT14, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_PERI_TR_IO_INPUT14_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT14, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_PERI_TR_IO_INPUT15_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT15, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_PERI_TR_IO_INPUT15_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT15, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_PERI_TR_IO_INPUT16_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT16, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_PERI_TR_IO_INPUT16_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT16, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_PERI_TR_IO_INPUT17_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT17, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_PERI_TR_IO_INPUT17_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT17, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_PERI_TR_IO_INPUT18_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT18, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_PERI_TR_IO_INPUT18_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT18, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_PERI_TR_IO_INPUT19_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT19, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_PERI_TR_IO_INPUT19_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT19, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_PERI_TR_IO_INPUT20_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT20, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_PERI_TR_IO_INPUT20_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT20, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_PERI_TR_IO_INPUT21_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT21, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_PERI_TR_IO_INPUT21_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT21, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_PERI_TR_IO_INPUT22_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT22, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_PERI_TR_IO_INPUT22_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT22, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_PERI_TR_IO_INPUT23_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT23, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_PERI_TR_IO_INPUT23_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT23, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_PERI_TR_IO_INPUT24_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT24, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_PERI_TR_IO_INPUT24_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT24, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_PERI_TR_IO_INPUT25_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT25, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_PERI_TR_IO_INPUT25_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT25, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_SCB0_TR_I2C_SCL_FILTERED = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB0_TR_I2C_SCL_FILTERED, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_SCB1_TR_I2C_SCL_FILTERED = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB1_TR_I2C_SCL_FILTERED, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_SCB2_TR_I2C_SCL_FILTERED = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB2_TR_I2C_SCL_FILTERED, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_SCB3_TR_I2C_SCL_FILTERED = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB3_TR_I2C_SCL_FILTERED, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_SCB4_TR_I2C_SCL_FILTERED = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB4_TR_I2C_SCL_FILTERED, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_SCB5_TR_I2C_SCL_FILTERED = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB5_TR_I2C_SCL_FILTERED, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_SCB6_TR_I2C_SCL_FILTERED = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB6_TR_I2C_SCL_FILTERED, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_SCB0_TR_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB0_TR_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_SCB1_TR_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB1_TR_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_SCB2_TR_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB2_TR_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_SCB3_TR_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB3_TR_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_SCB4_TR_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB4_TR_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_SCB5_TR_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB5_TR_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_SCB6_TR_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB6_TR_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_SCB0_TR_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB0_TR_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_SCB1_TR_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB1_TR_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_SCB2_TR_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB2_TR_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_SCB3_TR_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB3_TR_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_SCB4_TR_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB4_TR_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_SCB5_TR_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB5_TR_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_SCB6_TR_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB6_TR_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_SMIF_TR_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SMIF_TR_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_SMIF_TR_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SMIF_TR_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_TCPWM0_TR_COMPARE_MATCH0 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_COMPARE_MATCH0, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM0_TR_COMPARE_MATCH1 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_COMPARE_MATCH1, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM0_TR_COMPARE_MATCH2 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_COMPARE_MATCH2, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM0_TR_COMPARE_MATCH3 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_COMPARE_MATCH3, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH0 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH0, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH1 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH1, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH2 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH2, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH3 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH3, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH4 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH4, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH5 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH5, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH6 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH6, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH7 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH7, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM0_TR_OVERFLOW0 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OVERFLOW0, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM0_TR_OVERFLOW1 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OVERFLOW1, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM0_TR_OVERFLOW2 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OVERFLOW2, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM0_TR_OVERFLOW3 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OVERFLOW3, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW0 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW0, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW1 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW1, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW2 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW2, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW3 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW3, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW4 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW4, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW5 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW5, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW6 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW6, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW7 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW7, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM0_TR_UNDERFLOW0 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_UNDERFLOW0, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM0_TR_UNDERFLOW1 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_UNDERFLOW1, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM0_TR_UNDERFLOW2 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_UNDERFLOW2, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM0_TR_UNDERFLOW3 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_UNDERFLOW3, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW0 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW0, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW1 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW1, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW2 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW2, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW3 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW3, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW4 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW4, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW5 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW5, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW6 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW6, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW7 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW7, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_USB_DMA_REQ0 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_USB_DMA_REQ0, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_USB_DMA_REQ1 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_USB_DMA_REQ1, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_USB_DMA_REQ2 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_USB_DMA_REQ2, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_USB_DMA_REQ3 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_USB_DMA_REQ3, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_USB_DMA_REQ4 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_USB_DMA_REQ4, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_USB_DMA_REQ5 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_USB_DMA_REQ5, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_USB_DMA_REQ6 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_USB_DMA_REQ6, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_USB_DMA_REQ7 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_USB_DMA_REQ7, CYHAL_SIGNAL_TYPE_EDGE) }
	Name of each input trigger. More...
enum	cyhal_trigger_dest_psoc6_03_t {   CYHAL_TRIGGER_CANFD0_TR_DBG_DMA_ACK0 = 0 ,   CYHAL_TRIGGER_CANFD0_TR_EVT_SWT_IN0 = 1 ,   CYHAL_TRIGGER_CPUSS_CTI_TR_IN0 = 2 ,   CYHAL_TRIGGER_CPUSS_CTI_TR_IN1 = 3 ,   CYHAL_TRIGGER_CPUSS_DMAC_TR_IN0 = 4 ,   CYHAL_TRIGGER_CPUSS_DMAC_TR_IN1 = 5 ,   CYHAL_TRIGGER_CPUSS_DW0_TR_IN0 = 6 ,   CYHAL_TRIGGER_CPUSS_DW0_TR_IN1 = 7 ,   CYHAL_TRIGGER_CPUSS_DW0_TR_IN2 = 8 ,   CYHAL_TRIGGER_CPUSS_DW0_TR_IN3 = 9 ,   CYHAL_TRIGGER_CPUSS_DW0_TR_IN4 = 10 ,   CYHAL_TRIGGER_CPUSS_DW0_TR_IN5 = 11 ,   CYHAL_TRIGGER_CPUSS_DW0_TR_IN6 = 12 ,   CYHAL_TRIGGER_CPUSS_DW0_TR_IN7 = 13 ,   CYHAL_TRIGGER_CPUSS_DW0_TR_IN8 = 14 ,   CYHAL_TRIGGER_CPUSS_DW0_TR_IN9 = 15 ,   CYHAL_TRIGGER_CPUSS_DW0_TR_IN10 = 16 ,   CYHAL_TRIGGER_CPUSS_DW0_TR_IN11 = 17 ,   CYHAL_TRIGGER_CPUSS_DW0_TR_IN12 = 18 ,   CYHAL_TRIGGER_CPUSS_DW0_TR_IN13 = 19 ,   CYHAL_TRIGGER_CPUSS_DW0_TR_IN14 = 20 ,   CYHAL_TRIGGER_CPUSS_DW0_TR_IN15 = 21 ,   CYHAL_TRIGGER_CPUSS_DW0_TR_IN16 = 22 ,   CYHAL_TRIGGER_CPUSS_DW0_TR_IN17 = 23 ,   CYHAL_TRIGGER_CPUSS_DW0_TR_IN18 = 24 ,   CYHAL_TRIGGER_CPUSS_DW0_TR_IN19 = 25 ,   CYHAL_TRIGGER_CPUSS_DW0_TR_IN20 = 26 ,   CYHAL_TRIGGER_CPUSS_DW0_TR_IN21 = 27 ,   CYHAL_TRIGGER_CPUSS_DW0_TR_IN22 = 28 ,   CYHAL_TRIGGER_CPUSS_DW0_TR_IN23 = 29 ,   CYHAL_TRIGGER_CPUSS_DW0_TR_IN24 = 30 ,   CYHAL_TRIGGER_CPUSS_DW0_TR_IN25 = 31 ,   CYHAL_TRIGGER_CPUSS_DW0_TR_IN26 = 32 ,   CYHAL_TRIGGER_CPUSS_DW0_TR_IN27 = 33 ,   CYHAL_TRIGGER_CPUSS_DW0_TR_IN28 = 34 ,   CYHAL_TRIGGER_CPUSS_DW1_TR_IN0 = 35 ,   CYHAL_TRIGGER_CPUSS_DW1_TR_IN1 = 36 ,   CYHAL_TRIGGER_CPUSS_DW1_TR_IN2 = 37 ,   CYHAL_TRIGGER_CPUSS_DW1_TR_IN3 = 38 ,   CYHAL_TRIGGER_CPUSS_DW1_TR_IN4 = 39 ,   CYHAL_TRIGGER_CPUSS_DW1_TR_IN5 = 40 ,   CYHAL_TRIGGER_CPUSS_DW1_TR_IN6 = 41 ,   CYHAL_TRIGGER_CPUSS_DW1_TR_IN7 = 42 ,   CYHAL_TRIGGER_CPUSS_DW1_TR_IN8 = 43 ,   CYHAL_TRIGGER_CPUSS_DW1_TR_IN9 = 44 ,   CYHAL_TRIGGER_CPUSS_DW1_TR_IN10 = 45 ,   CYHAL_TRIGGER_CPUSS_DW1_TR_IN11 = 46 ,   CYHAL_TRIGGER_CPUSS_DW1_TR_IN12 = 47 ,   CYHAL_TRIGGER_CPUSS_DW1_TR_IN13 = 48 ,   CYHAL_TRIGGER_CPUSS_DW1_TR_IN14 = 49 ,   CYHAL_TRIGGER_CPUSS_DW1_TR_IN15 = 50 ,   CYHAL_TRIGGER_CPUSS_DW1_TR_IN16 = 51 ,   CYHAL_TRIGGER_CPUSS_DW1_TR_IN17 = 52 ,   CYHAL_TRIGGER_CPUSS_DW1_TR_IN18 = 53 ,   CYHAL_TRIGGER_CPUSS_DW1_TR_IN19 = 54 ,   CYHAL_TRIGGER_CPUSS_DW1_TR_IN20 = 55 ,   CYHAL_TRIGGER_CPUSS_DW1_TR_IN21 = 56 ,   CYHAL_TRIGGER_CPUSS_DW1_TR_IN22 = 57 ,   CYHAL_TRIGGER_CPUSS_DW1_TR_IN23 = 58 ,   CYHAL_TRIGGER_CPUSS_DW1_TR_IN24 = 59 ,   CYHAL_TRIGGER_CPUSS_DW1_TR_IN25 = 60 ,   CYHAL_TRIGGER_CPUSS_DW1_TR_IN26 = 61 ,   CYHAL_TRIGGER_CPUSS_DW1_TR_IN27 = 62 ,   CYHAL_TRIGGER_CPUSS_DW1_TR_IN28 = 63 ,   CYHAL_TRIGGER_CPUSS_DW1_TR_IN29 = 64 ,   CYHAL_TRIGGER_CPUSS_DW1_TR_IN30 = 65 ,   CYHAL_TRIGGER_CPUSS_DW1_TR_IN31 = 66 ,   CYHAL_TRIGGER_CSD_DSI_START = 67 ,   CYHAL_TRIGGER_PASS_TR_SAR_IN = 68 ,   CYHAL_TRIGGER_PERI_TR_DBG_FREEZE = 69 ,   CYHAL_TRIGGER_PERI_TR_IO_OUTPUT0 = 70 ,   CYHAL_TRIGGER_PERI_TR_IO_OUTPUT1 = 71 ,   CYHAL_TRIGGER_TCPWM0_TR_IN0 = 72 ,   CYHAL_TRIGGER_TCPWM0_TR_IN1 = 73 ,   CYHAL_TRIGGER_TCPWM0_TR_IN2 = 74 ,   CYHAL_TRIGGER_TCPWM0_TR_IN3 = 75 ,   CYHAL_TRIGGER_TCPWM0_TR_IN4 = 76 ,   CYHAL_TRIGGER_TCPWM0_TR_IN5 = 77 ,   CYHAL_TRIGGER_TCPWM0_TR_IN6 = 78 ,   CYHAL_TRIGGER_TCPWM0_TR_IN7 = 79 ,   CYHAL_TRIGGER_TCPWM0_TR_IN8 = 80 ,   CYHAL_TRIGGER_TCPWM0_TR_IN9 = 81 ,   CYHAL_TRIGGER_TCPWM0_TR_IN10 = 82 ,   CYHAL_TRIGGER_TCPWM0_TR_IN11 = 83 ,   CYHAL_TRIGGER_TCPWM0_TR_IN12 = 84 ,   CYHAL_TRIGGER_TCPWM0_TR_IN13 = 85 ,   CYHAL_TRIGGER_TCPWM1_TR_IN0 = 86 ,   CYHAL_TRIGGER_TCPWM1_TR_IN1 = 87 ,   CYHAL_TRIGGER_TCPWM1_TR_IN2 = 88 ,   CYHAL_TRIGGER_TCPWM1_TR_IN3 = 89 ,   CYHAL_TRIGGER_TCPWM1_TR_IN4 = 90 ,   CYHAL_TRIGGER_TCPWM1_TR_IN5 = 91 ,   CYHAL_TRIGGER_TCPWM1_TR_IN6 = 92 ,   CYHAL_TRIGGER_TCPWM1_TR_IN7 = 93 ,   CYHAL_TRIGGER_TCPWM1_TR_IN8 = 94 ,   CYHAL_TRIGGER_TCPWM1_TR_IN9 = 95 ,   CYHAL_TRIGGER_TCPWM1_TR_IN10 = 96 ,   CYHAL_TRIGGER_TCPWM1_TR_IN11 = 97 ,   CYHAL_TRIGGER_TCPWM1_TR_IN12 = 98 ,   CYHAL_TRIGGER_TCPWM1_TR_IN13 = 99 ,   CYHAL_TRIGGER_USB_DMA_BURSTEND0 = 100 ,   CYHAL_TRIGGER_USB_DMA_BURSTEND1 = 101 ,   CYHAL_TRIGGER_USB_DMA_BURSTEND2 = 102 ,   CYHAL_TRIGGER_USB_DMA_BURSTEND3 = 103 ,   CYHAL_TRIGGER_USB_DMA_BURSTEND4 = 104 ,   CYHAL_TRIGGER_USB_DMA_BURSTEND5 = 105 ,   CYHAL_TRIGGER_USB_DMA_BURSTEND6 = 106 ,   CYHAL_TRIGGER_USB_DMA_BURSTEND7 = 107 }
	Name of each output trigger. More...

Macro Definition Documentation

CYHAL_TRIGGER_CPUSS_ZERO

#define CYHAL_TRIGGER_CPUSS_ZERO   (CYHAL_TRIGGER_CPUSS_ZERO_LEVEL)

Deprecated defines for signals that can be either level or edge.

Legacy define. Instead, use the explicit _LEVEL or _EDGE version.

Enumeration Type Documentation

cyhal_trigger_source_psoc6_03_t

enum cyhal_trigger_source_psoc6_03_t

Name of each input trigger.

Enumerator
CYHAL_TRIGGER_CPUSS_ZERO_EDGE	cpuss.zero
CYHAL_TRIGGER_CPUSS_ZERO_LEVEL	cpuss.zero
CYHAL_TRIGGER_CANFD0_TR_DBG_DMA_REQ0	canfd[0].tr_dbg_dma_req[0]
CYHAL_TRIGGER_CANFD0_TR_FIFO00	canfd[0].tr_fifo0[0]
CYHAL_TRIGGER_CANFD0_TR_FIFO10	canfd[0].tr_fifo1[0]
CYHAL_TRIGGER_CANFD0_TR_TMP_RTP_OUT0	canfd[0].tr_tmp_rtp_out[0]
CYHAL_TRIGGER_CPUSS_CTI_TR_OUT0	cpuss.cti_tr_out[0]
CYHAL_TRIGGER_CPUSS_CTI_TR_OUT1	cpuss.cti_tr_out[1]
CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT0	cpuss.dmac_tr_out[0]
CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT1	cpuss.dmac_tr_out[1]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT0	cpuss.dw0_tr_out[0]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT1	cpuss.dw0_tr_out[1]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT2	cpuss.dw0_tr_out[2]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT3	cpuss.dw0_tr_out[3]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT4	cpuss.dw0_tr_out[4]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT5	cpuss.dw0_tr_out[5]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT6	cpuss.dw0_tr_out[6]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT7	cpuss.dw0_tr_out[7]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT8	cpuss.dw0_tr_out[8]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT9	cpuss.dw0_tr_out[9]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT10	cpuss.dw0_tr_out[10]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT11	cpuss.dw0_tr_out[11]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT12	cpuss.dw0_tr_out[12]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT13	cpuss.dw0_tr_out[13]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT14	cpuss.dw0_tr_out[14]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT15	cpuss.dw0_tr_out[15]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT16	cpuss.dw0_tr_out[16]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT17	cpuss.dw0_tr_out[17]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT18	cpuss.dw0_tr_out[18]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT19	cpuss.dw0_tr_out[19]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT20	cpuss.dw0_tr_out[20]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT21	cpuss.dw0_tr_out[21]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT22	cpuss.dw0_tr_out[22]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT23	cpuss.dw0_tr_out[23]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT24	cpuss.dw0_tr_out[24]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT25	cpuss.dw0_tr_out[25]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT26	cpuss.dw0_tr_out[26]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT27	cpuss.dw0_tr_out[27]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT28	cpuss.dw0_tr_out[28]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT0	cpuss.dw1_tr_out[0]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT1	cpuss.dw1_tr_out[1]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT2	cpuss.dw1_tr_out[2]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT3	cpuss.dw1_tr_out[3]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT4	cpuss.dw1_tr_out[4]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT5	cpuss.dw1_tr_out[5]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT6	cpuss.dw1_tr_out[6]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT7	cpuss.dw1_tr_out[7]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT8	cpuss.dw1_tr_out[8]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT9	cpuss.dw1_tr_out[9]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT10	cpuss.dw1_tr_out[10]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT11	cpuss.dw1_tr_out[11]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT12	cpuss.dw1_tr_out[12]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT13	cpuss.dw1_tr_out[13]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT14	cpuss.dw1_tr_out[14]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT15	cpuss.dw1_tr_out[15]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT16	cpuss.dw1_tr_out[16]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT17	cpuss.dw1_tr_out[17]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT18	cpuss.dw1_tr_out[18]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT19	cpuss.dw1_tr_out[19]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT20	cpuss.dw1_tr_out[20]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT21	cpuss.dw1_tr_out[21]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT22	cpuss.dw1_tr_out[22]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT23	cpuss.dw1_tr_out[23]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT24	cpuss.dw1_tr_out[24]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT25	cpuss.dw1_tr_out[25]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT26	cpuss.dw1_tr_out[26]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT27	cpuss.dw1_tr_out[27]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT28	cpuss.dw1_tr_out[28]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT29	cpuss.dw1_tr_out[29]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT30	cpuss.dw1_tr_out[30]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT31	cpuss.dw1_tr_out[31]
CYHAL_TRIGGER_CPUSS_TR_FAULT0	cpuss.tr_fault[0]
CYHAL_TRIGGER_CPUSS_TR_FAULT1	cpuss.tr_fault[1]
CYHAL_TRIGGER_CSD_DSI_SAMPLE_OUT	csd.dsi_sample_out
CYHAL_TRIGGER_CSD_DSI_SENSE_OUT_EDGE	csd.dsi_sense_out
CYHAL_TRIGGER_CSD_DSI_SENSE_OUT_LEVEL	csd.dsi_sense_out
CYHAL_TRIGGER_CSD_TR_ADC_DONE_EDGE	csd.tr_adc_done
CYHAL_TRIGGER_CSD_TR_ADC_DONE_LEVEL	csd.tr_adc_done
CYHAL_TRIGGER_LPCOMP_DSI_COMP0	lpcomp.dsi_comp0
CYHAL_TRIGGER_LPCOMP_DSI_COMP1	lpcomp.dsi_comp1
CYHAL_TRIGGER_PASS_TR_SAR_OUT	pass.tr_sar_out
CYHAL_TRIGGER_PERI_TR_IO_INPUT0_EDGE	peri.tr_io_input[0]
CYHAL_TRIGGER_PERI_TR_IO_INPUT0_LEVEL	peri.tr_io_input[0]
CYHAL_TRIGGER_PERI_TR_IO_INPUT1_EDGE	peri.tr_io_input[1]
CYHAL_TRIGGER_PERI_TR_IO_INPUT1_LEVEL	peri.tr_io_input[1]
CYHAL_TRIGGER_PERI_TR_IO_INPUT2_EDGE	peri.tr_io_input[2]
CYHAL_TRIGGER_PERI_TR_IO_INPUT2_LEVEL	peri.tr_io_input[2]
CYHAL_TRIGGER_PERI_TR_IO_INPUT3_EDGE	peri.tr_io_input[3]
CYHAL_TRIGGER_PERI_TR_IO_INPUT3_LEVEL	peri.tr_io_input[3]
CYHAL_TRIGGER_PERI_TR_IO_INPUT4_EDGE	peri.tr_io_input[4]
CYHAL_TRIGGER_PERI_TR_IO_INPUT4_LEVEL	peri.tr_io_input[4]
CYHAL_TRIGGER_PERI_TR_IO_INPUT5_EDGE	peri.tr_io_input[5]
CYHAL_TRIGGER_PERI_TR_IO_INPUT5_LEVEL	peri.tr_io_input[5]
CYHAL_TRIGGER_PERI_TR_IO_INPUT6_EDGE	peri.tr_io_input[6]
CYHAL_TRIGGER_PERI_TR_IO_INPUT6_LEVEL	peri.tr_io_input[6]
CYHAL_TRIGGER_PERI_TR_IO_INPUT7_EDGE	peri.tr_io_input[7]
CYHAL_TRIGGER_PERI_TR_IO_INPUT7_LEVEL	peri.tr_io_input[7]
CYHAL_TRIGGER_PERI_TR_IO_INPUT8_EDGE	peri.tr_io_input[8]
CYHAL_TRIGGER_PERI_TR_IO_INPUT8_LEVEL	peri.tr_io_input[8]
CYHAL_TRIGGER_PERI_TR_IO_INPUT9_EDGE	peri.tr_io_input[9]
CYHAL_TRIGGER_PERI_TR_IO_INPUT9_LEVEL	peri.tr_io_input[9]
CYHAL_TRIGGER_PERI_TR_IO_INPUT10_EDGE	peri.tr_io_input[10]
CYHAL_TRIGGER_PERI_TR_IO_INPUT10_LEVEL	peri.tr_io_input[10]
CYHAL_TRIGGER_PERI_TR_IO_INPUT11_EDGE	peri.tr_io_input[11]
CYHAL_TRIGGER_PERI_TR_IO_INPUT11_LEVEL	peri.tr_io_input[11]
CYHAL_TRIGGER_PERI_TR_IO_INPUT12_EDGE	peri.tr_io_input[12]
CYHAL_TRIGGER_PERI_TR_IO_INPUT12_LEVEL	peri.tr_io_input[12]
CYHAL_TRIGGER_PERI_TR_IO_INPUT13_EDGE	peri.tr_io_input[13]
CYHAL_TRIGGER_PERI_TR_IO_INPUT13_LEVEL	peri.tr_io_input[13]
CYHAL_TRIGGER_PERI_TR_IO_INPUT14_EDGE	peri.tr_io_input[14]
CYHAL_TRIGGER_PERI_TR_IO_INPUT14_LEVEL	peri.tr_io_input[14]
CYHAL_TRIGGER_PERI_TR_IO_INPUT15_EDGE	peri.tr_io_input[15]
CYHAL_TRIGGER_PERI_TR_IO_INPUT15_LEVEL	peri.tr_io_input[15]
CYHAL_TRIGGER_PERI_TR_IO_INPUT16_EDGE	peri.tr_io_input[16]
CYHAL_TRIGGER_PERI_TR_IO_INPUT16_LEVEL	peri.tr_io_input[16]
CYHAL_TRIGGER_PERI_TR_IO_INPUT17_EDGE	peri.tr_io_input[17]
CYHAL_TRIGGER_PERI_TR_IO_INPUT17_LEVEL	peri.tr_io_input[17]
CYHAL_TRIGGER_PERI_TR_IO_INPUT18_EDGE	peri.tr_io_input[18]
CYHAL_TRIGGER_PERI_TR_IO_INPUT18_LEVEL	peri.tr_io_input[18]
CYHAL_TRIGGER_PERI_TR_IO_INPUT19_EDGE	peri.tr_io_input[19]
CYHAL_TRIGGER_PERI_TR_IO_INPUT19_LEVEL	peri.tr_io_input[19]
CYHAL_TRIGGER_PERI_TR_IO_INPUT20_EDGE	peri.tr_io_input[20]
CYHAL_TRIGGER_PERI_TR_IO_INPUT20_LEVEL	peri.tr_io_input[20]
CYHAL_TRIGGER_PERI_TR_IO_INPUT21_EDGE	peri.tr_io_input[21]
CYHAL_TRIGGER_PERI_TR_IO_INPUT21_LEVEL	peri.tr_io_input[21]
CYHAL_TRIGGER_PERI_TR_IO_INPUT22_EDGE	peri.tr_io_input[22]
CYHAL_TRIGGER_PERI_TR_IO_INPUT22_LEVEL	peri.tr_io_input[22]
CYHAL_TRIGGER_PERI_TR_IO_INPUT23_EDGE	peri.tr_io_input[23]
CYHAL_TRIGGER_PERI_TR_IO_INPUT23_LEVEL	peri.tr_io_input[23]
CYHAL_TRIGGER_PERI_TR_IO_INPUT24_EDGE	peri.tr_io_input[24]
CYHAL_TRIGGER_PERI_TR_IO_INPUT24_LEVEL	peri.tr_io_input[24]
CYHAL_TRIGGER_PERI_TR_IO_INPUT25_EDGE	peri.tr_io_input[25]
CYHAL_TRIGGER_PERI_TR_IO_INPUT25_LEVEL	peri.tr_io_input[25]
CYHAL_TRIGGER_SCB0_TR_I2C_SCL_FILTERED	scb[0].tr_i2c_scl_filtered
CYHAL_TRIGGER_SCB1_TR_I2C_SCL_FILTERED	scb[1].tr_i2c_scl_filtered
CYHAL_TRIGGER_SCB2_TR_I2C_SCL_FILTERED	scb[2].tr_i2c_scl_filtered
CYHAL_TRIGGER_SCB3_TR_I2C_SCL_FILTERED	scb[3].tr_i2c_scl_filtered
CYHAL_TRIGGER_SCB4_TR_I2C_SCL_FILTERED	scb[4].tr_i2c_scl_filtered
CYHAL_TRIGGER_SCB5_TR_I2C_SCL_FILTERED	scb[5].tr_i2c_scl_filtered
CYHAL_TRIGGER_SCB6_TR_I2C_SCL_FILTERED	scb[6].tr_i2c_scl_filtered
CYHAL_TRIGGER_SCB0_TR_RX_REQ	scb[0].tr_rx_req
CYHAL_TRIGGER_SCB1_TR_RX_REQ	scb[1].tr_rx_req
CYHAL_TRIGGER_SCB2_TR_RX_REQ	scb[2].tr_rx_req
CYHAL_TRIGGER_SCB3_TR_RX_REQ	scb[3].tr_rx_req
CYHAL_TRIGGER_SCB4_TR_RX_REQ	scb[4].tr_rx_req
CYHAL_TRIGGER_SCB5_TR_RX_REQ	scb[5].tr_rx_req
CYHAL_TRIGGER_SCB6_TR_RX_REQ	scb[6].tr_rx_req
CYHAL_TRIGGER_SCB0_TR_TX_REQ	scb[0].tr_tx_req
CYHAL_TRIGGER_SCB1_TR_TX_REQ	scb[1].tr_tx_req
CYHAL_TRIGGER_SCB2_TR_TX_REQ	scb[2].tr_tx_req
CYHAL_TRIGGER_SCB3_TR_TX_REQ	scb[3].tr_tx_req
CYHAL_TRIGGER_SCB4_TR_TX_REQ	scb[4].tr_tx_req
CYHAL_TRIGGER_SCB5_TR_TX_REQ	scb[5].tr_tx_req
CYHAL_TRIGGER_SCB6_TR_TX_REQ	scb[6].tr_tx_req
CYHAL_TRIGGER_SMIF_TR_RX_REQ	smif.tr_rx_req
CYHAL_TRIGGER_SMIF_TR_TX_REQ	smif.tr_tx_req
CYHAL_TRIGGER_TCPWM0_TR_COMPARE_MATCH0	tcpwm[0].tr_compare_match[0]
CYHAL_TRIGGER_TCPWM0_TR_COMPARE_MATCH1	tcpwm[0].tr_compare_match[1]
CYHAL_TRIGGER_TCPWM0_TR_COMPARE_MATCH2	tcpwm[0].tr_compare_match[2]
CYHAL_TRIGGER_TCPWM0_TR_COMPARE_MATCH3	tcpwm[0].tr_compare_match[3]
CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH0	tcpwm[1].tr_compare_match[0]
CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH1	tcpwm[1].tr_compare_match[1]
CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH2	tcpwm[1].tr_compare_match[2]
CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH3	tcpwm[1].tr_compare_match[3]
CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH4	tcpwm[1].tr_compare_match[4]
CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH5	tcpwm[1].tr_compare_match[5]
CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH6	tcpwm[1].tr_compare_match[6]
CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH7	tcpwm[1].tr_compare_match[7]
CYHAL_TRIGGER_TCPWM0_TR_OVERFLOW0	tcpwm[0].tr_overflow[0]
CYHAL_TRIGGER_TCPWM0_TR_OVERFLOW1	tcpwm[0].tr_overflow[1]
CYHAL_TRIGGER_TCPWM0_TR_OVERFLOW2	tcpwm[0].tr_overflow[2]
CYHAL_TRIGGER_TCPWM0_TR_OVERFLOW3	tcpwm[0].tr_overflow[3]
CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW0	tcpwm[1].tr_overflow[0]
CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW1	tcpwm[1].tr_overflow[1]
CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW2	tcpwm[1].tr_overflow[2]
CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW3	tcpwm[1].tr_overflow[3]
CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW4	tcpwm[1].tr_overflow[4]
CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW5	tcpwm[1].tr_overflow[5]
CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW6	tcpwm[1].tr_overflow[6]
CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW7	tcpwm[1].tr_overflow[7]
CYHAL_TRIGGER_TCPWM0_TR_UNDERFLOW0	tcpwm[0].tr_underflow[0]
CYHAL_TRIGGER_TCPWM0_TR_UNDERFLOW1	tcpwm[0].tr_underflow[1]
CYHAL_TRIGGER_TCPWM0_TR_UNDERFLOW2	tcpwm[0].tr_underflow[2]
CYHAL_TRIGGER_TCPWM0_TR_UNDERFLOW3	tcpwm[0].tr_underflow[3]
CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW0	tcpwm[1].tr_underflow[0]
CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW1	tcpwm[1].tr_underflow[1]
CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW2	tcpwm[1].tr_underflow[2]
CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW3	tcpwm[1].tr_underflow[3]
CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW4	tcpwm[1].tr_underflow[4]
CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW5	tcpwm[1].tr_underflow[5]
CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW6	tcpwm[1].tr_underflow[6]
CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW7	tcpwm[1].tr_underflow[7]
CYHAL_TRIGGER_USB_DMA_REQ0	usb.dma_req[0]
CYHAL_TRIGGER_USB_DMA_REQ1	usb.dma_req[1]
CYHAL_TRIGGER_USB_DMA_REQ2	usb.dma_req[2]
CYHAL_TRIGGER_USB_DMA_REQ3	usb.dma_req[3]
CYHAL_TRIGGER_USB_DMA_REQ4	usb.dma_req[4]
CYHAL_TRIGGER_USB_DMA_REQ5	usb.dma_req[5]
CYHAL_TRIGGER_USB_DMA_REQ6	usb.dma_req[6]
CYHAL_TRIGGER_USB_DMA_REQ7	usb.dma_req[7]

cyhal_trigger_dest_psoc6_03_t

enum cyhal_trigger_dest_psoc6_03_t

Name of each output trigger.

Enumerator
CYHAL_TRIGGER_CANFD0_TR_DBG_DMA_ACK0	CAN DW0 triggers (from DW back to CAN) - canfd[0].tr_dbg_dma_ack[0].
CYHAL_TRIGGER_CANFD0_TR_EVT_SWT_IN0	CAN TT Sync - canfd[0].tr_evt_swt_in[0].
CYHAL_TRIGGER_CPUSS_CTI_TR_IN0	CPUSS Debug trigger multiplexer - cpuss.cti_tr_in[0].
CYHAL_TRIGGER_CPUSS_CTI_TR_IN1	CPUSS Debug trigger multiplexer - cpuss.cti_tr_in[1].
CYHAL_TRIGGER_CPUSS_DMAC_TR_IN0	MDMA trigger multiplexer - cpuss.dmac_tr_in[0].
CYHAL_TRIGGER_CPUSS_DMAC_TR_IN1	MDMA trigger multiplexer - cpuss.dmac_tr_in[1].
CYHAL_TRIGGER_CPUSS_DW0_TR_IN0	PDMA0 trigger multiplexer - cpuss.dw0_tr_in[0].
CYHAL_TRIGGER_CPUSS_DW0_TR_IN1	PDMA0 trigger multiplexer - cpuss.dw0_tr_in[1].
CYHAL_TRIGGER_CPUSS_DW0_TR_IN2	PDMA0 trigger multiplexer - cpuss.dw0_tr_in[2].
CYHAL_TRIGGER_CPUSS_DW0_TR_IN3	PDMA0 trigger multiplexer - cpuss.dw0_tr_in[3].
CYHAL_TRIGGER_CPUSS_DW0_TR_IN4	PDMA0 trigger multiplexer - cpuss.dw0_tr_in[4].
CYHAL_TRIGGER_CPUSS_DW0_TR_IN5	PDMA0 trigger multiplexer - cpuss.dw0_tr_in[5].
CYHAL_TRIGGER_CPUSS_DW0_TR_IN6	PDMA0 trigger multiplexer - cpuss.dw0_tr_in[6].
CYHAL_TRIGGER_CPUSS_DW0_TR_IN7	PDMA0 trigger multiplexer - cpuss.dw0_tr_in[7].
CYHAL_TRIGGER_CPUSS_DW0_TR_IN8	USB PDMA0 Triggers - cpuss.dw0_tr_in[8].
CYHAL_TRIGGER_CPUSS_DW0_TR_IN9	USB PDMA0 Triggers - cpuss.dw0_tr_in[9].
CYHAL_TRIGGER_CPUSS_DW0_TR_IN10	USB PDMA0 Triggers - cpuss.dw0_tr_in[10].
CYHAL_TRIGGER_CPUSS_DW0_TR_IN11	USB PDMA0 Triggers - cpuss.dw0_tr_in[11].
CYHAL_TRIGGER_CPUSS_DW0_TR_IN12	USB PDMA0 Triggers - cpuss.dw0_tr_in[12].
CYHAL_TRIGGER_CPUSS_DW0_TR_IN13	USB PDMA0 Triggers - cpuss.dw0_tr_in[13].
CYHAL_TRIGGER_CPUSS_DW0_TR_IN14	USB PDMA0 Triggers - cpuss.dw0_tr_in[14].
CYHAL_TRIGGER_CPUSS_DW0_TR_IN15	USB PDMA0 Triggers - cpuss.dw0_tr_in[15].
CYHAL_TRIGGER_CPUSS_DW0_TR_IN16	SCB PDMA0 Triggers - cpuss.dw0_tr_in[16].
CYHAL_TRIGGER_CPUSS_DW0_TR_IN17	SCB PDMA0 Triggers - cpuss.dw0_tr_in[17].
CYHAL_TRIGGER_CPUSS_DW0_TR_IN18	SCB PDMA0 Triggers - cpuss.dw0_tr_in[18].
CYHAL_TRIGGER_CPUSS_DW0_TR_IN19	SCB PDMA0 Triggers - cpuss.dw0_tr_in[19].
CYHAL_TRIGGER_CPUSS_DW0_TR_IN20	SCB PDMA0 Triggers - cpuss.dw0_tr_in[20].
CYHAL_TRIGGER_CPUSS_DW0_TR_IN21	SCB PDMA0 Triggers - cpuss.dw0_tr_in[21].
CYHAL_TRIGGER_CPUSS_DW0_TR_IN22	SCB PDMA0 Triggers - cpuss.dw0_tr_in[22].
CYHAL_TRIGGER_CPUSS_DW0_TR_IN23	SCB PDMA0 Triggers - cpuss.dw0_tr_in[23].
CYHAL_TRIGGER_CPUSS_DW0_TR_IN24	SCB PDMA0 Triggers - cpuss.dw0_tr_in[24].
CYHAL_TRIGGER_CPUSS_DW0_TR_IN25	SCB PDMA0 Triggers - cpuss.dw0_tr_in[25].
CYHAL_TRIGGER_CPUSS_DW0_TR_IN26	SCB PDMA0 Triggers - cpuss.dw0_tr_in[26].
CYHAL_TRIGGER_CPUSS_DW0_TR_IN27	SCB PDMA0 Triggers - cpuss.dw0_tr_in[27].
CYHAL_TRIGGER_CPUSS_DW0_TR_IN28	SAR to PDMA1 direct connect - cpuss.dw0_tr_in[28].
CYHAL_TRIGGER_CPUSS_DW1_TR_IN0	PDMA1 trigger multiplexer - cpuss.dw1_tr_in[0].
CYHAL_TRIGGER_CPUSS_DW1_TR_IN1	PDMA1 trigger multiplexer - cpuss.dw1_tr_in[1].
CYHAL_TRIGGER_CPUSS_DW1_TR_IN2	PDMA1 trigger multiplexer - cpuss.dw1_tr_in[2].
CYHAL_TRIGGER_CPUSS_DW1_TR_IN3	PDMA1 trigger multiplexer - cpuss.dw1_tr_in[3].
CYHAL_TRIGGER_CPUSS_DW1_TR_IN4	PDMA1 trigger multiplexer - cpuss.dw1_tr_in[4].
CYHAL_TRIGGER_CPUSS_DW1_TR_IN5	PDMA1 trigger multiplexer - cpuss.dw1_tr_in[5].
CYHAL_TRIGGER_CPUSS_DW1_TR_IN6	PDMA1 trigger multiplexer - cpuss.dw1_tr_in[6].
CYHAL_TRIGGER_CPUSS_DW1_TR_IN7	PDMA1 trigger multiplexer - cpuss.dw1_tr_in[7].
CYHAL_TRIGGER_CPUSS_DW1_TR_IN8	SCB PDMA1 Triggers - cpuss.dw1_tr_in[8].
CYHAL_TRIGGER_CPUSS_DW1_TR_IN9	SCB PDMA1 Triggers - cpuss.dw1_tr_in[9].
CYHAL_TRIGGER_CPUSS_DW1_TR_IN10	SCB PDMA1 Triggers - cpuss.dw1_tr_in[10].
CYHAL_TRIGGER_CPUSS_DW1_TR_IN11	SCB PDMA1 Triggers - cpuss.dw1_tr_in[11].
CYHAL_TRIGGER_CPUSS_DW1_TR_IN12	SCB PDMA1 Triggers - cpuss.dw1_tr_in[12].
CYHAL_TRIGGER_CPUSS_DW1_TR_IN13	SCB PDMA1 Triggers - cpuss.dw1_tr_in[13].
CYHAL_TRIGGER_CPUSS_DW1_TR_IN14	SCB PDMA1 Triggers - cpuss.dw1_tr_in[14].
CYHAL_TRIGGER_CPUSS_DW1_TR_IN15	SCB PDMA1 Triggers - cpuss.dw1_tr_in[15].
CYHAL_TRIGGER_CPUSS_DW1_TR_IN16	SCB PDMA1 Triggers - cpuss.dw1_tr_in[16].
CYHAL_TRIGGER_CPUSS_DW1_TR_IN17	SCB PDMA1 Triggers - cpuss.dw1_tr_in[17].
CYHAL_TRIGGER_CPUSS_DW1_TR_IN18	SCB PDMA1 Triggers - cpuss.dw1_tr_in[18].
CYHAL_TRIGGER_CPUSS_DW1_TR_IN19	SCB PDMA1 Triggers - cpuss.dw1_tr_in[19].
CYHAL_TRIGGER_CPUSS_DW1_TR_IN20	SCB PDMA1 Triggers - cpuss.dw1_tr_in[20].
CYHAL_TRIGGER_CPUSS_DW1_TR_IN21	SCB PDMA1 Triggers - cpuss.dw1_tr_in[21].
CYHAL_TRIGGER_CPUSS_DW1_TR_IN22	SMIF to PDMA1 direct connect - cpuss.dw1_tr_in[22].
CYHAL_TRIGGER_CPUSS_DW1_TR_IN23	SMIF to PDMA1 direct connect - cpuss.dw1_tr_in[23].
CYHAL_TRIGGER_CPUSS_DW1_TR_IN24	SMIF to PDMA1 direct connect - cpuss.dw1_tr_in[24].
CYHAL_TRIGGER_CPUSS_DW1_TR_IN25	SMIF to PDMA1 direct connect - cpuss.dw1_tr_in[25].
CYHAL_TRIGGER_CPUSS_DW1_TR_IN26	SMIF to PDMA1 direct connect - cpuss.dw1_tr_in[26].
CYHAL_TRIGGER_CPUSS_DW1_TR_IN27	SMIF to PDMA1 direct connect - cpuss.dw1_tr_in[27].
CYHAL_TRIGGER_CPUSS_DW1_TR_IN28	SMIF to PDMA1 direct connect - cpuss.dw1_tr_in[28].
CYHAL_TRIGGER_CPUSS_DW1_TR_IN29	CAN PDMA1 triggers - cpuss.dw1_tr_in[29].
CYHAL_TRIGGER_CPUSS_DW1_TR_IN30	CAN PDMA1 triggers - cpuss.dw1_tr_in[30].
CYHAL_TRIGGER_CPUSS_DW1_TR_IN31	CAN PDMA1 triggers - cpuss.dw1_tr_in[31].
CYHAL_TRIGGER_CSD_DSI_START	Capsense trigger multiplexer - csd.dsi_start.
CYHAL_TRIGGER_PASS_TR_SAR_IN	ADC trigger multiplexer - pass.tr_sar_in.
CYHAL_TRIGGER_PERI_TR_DBG_FREEZE	PERI Freeze trigger multiplexer - peri.tr_dbg_freeze.
CYHAL_TRIGGER_PERI_TR_IO_OUTPUT0	HSIOM trigger multiplexer - peri.tr_io_output[0].
CYHAL_TRIGGER_PERI_TR_IO_OUTPUT1	HSIOM trigger multiplexer - peri.tr_io_output[1].
CYHAL_TRIGGER_TCPWM0_TR_IN0	TCPWM0 trigger multiplexer - tcpwm[0].tr_in[0].
CYHAL_TRIGGER_TCPWM0_TR_IN1	TCPWM0 trigger multiplexer - tcpwm[0].tr_in[1].
CYHAL_TRIGGER_TCPWM0_TR_IN2	TCPWM0 trigger multiplexer - tcpwm[0].tr_in[2].
CYHAL_TRIGGER_TCPWM0_TR_IN3	TCPWM0 trigger multiplexer - tcpwm[0].tr_in[3].
CYHAL_TRIGGER_TCPWM0_TR_IN4	TCPWM0 trigger multiplexer - tcpwm[0].tr_in[4].
CYHAL_TRIGGER_TCPWM0_TR_IN5	TCPWM0 trigger multiplexer - tcpwm[0].tr_in[5].
CYHAL_TRIGGER_TCPWM0_TR_IN6	TCPWM0 trigger multiplexer - tcpwm[0].tr_in[6].
CYHAL_TRIGGER_TCPWM0_TR_IN7	TCPWM0 trigger multiplexer - tcpwm[0].tr_in[7].
CYHAL_TRIGGER_TCPWM0_TR_IN8	TCPWM0 trigger multiplexer - tcpwm[0].tr_in[8].
CYHAL_TRIGGER_TCPWM0_TR_IN9	TCPWM0 trigger multiplexer - tcpwm[0].tr_in[9].
CYHAL_TRIGGER_TCPWM0_TR_IN10	TCPWM0 trigger multiplexer - tcpwm[0].tr_in[10].
CYHAL_TRIGGER_TCPWM0_TR_IN11	TCPWM0 trigger multiplexer - tcpwm[0].tr_in[11].
CYHAL_TRIGGER_TCPWM0_TR_IN12	TCPWM0 trigger multiplexer - tcpwm[0].tr_in[12].
CYHAL_TRIGGER_TCPWM0_TR_IN13	TCPWM0 trigger multiplexer - tcpwm[0].tr_in[13].
CYHAL_TRIGGER_TCPWM1_TR_IN0	TCPWM1 trigger multiplexer - tcpwm[1].tr_in[0].
CYHAL_TRIGGER_TCPWM1_TR_IN1	TCPWM1 trigger multiplexer - tcpwm[1].tr_in[1].
CYHAL_TRIGGER_TCPWM1_TR_IN2	TCPWM1 trigger multiplexer - tcpwm[1].tr_in[2].
CYHAL_TRIGGER_TCPWM1_TR_IN3	TCPWM1 trigger multiplexer - tcpwm[1].tr_in[3].
CYHAL_TRIGGER_TCPWM1_TR_IN4	TCPWM1 trigger multiplexer - tcpwm[1].tr_in[4].
CYHAL_TRIGGER_TCPWM1_TR_IN5	TCPWM1 trigger multiplexer - tcpwm[1].tr_in[5].
CYHAL_TRIGGER_TCPWM1_TR_IN6	TCPWM1 trigger multiplexer - tcpwm[1].tr_in[6].
CYHAL_TRIGGER_TCPWM1_TR_IN7	TCPWM1 trigger multiplexer - tcpwm[1].tr_in[7].
CYHAL_TRIGGER_TCPWM1_TR_IN8	TCPWM1 trigger multiplexer - tcpwm[1].tr_in[8].
CYHAL_TRIGGER_TCPWM1_TR_IN9	TCPWM1 trigger multiplexer - tcpwm[1].tr_in[9].
CYHAL_TRIGGER_TCPWM1_TR_IN10	TCPWM1 trigger multiplexer - tcpwm[1].tr_in[10].
CYHAL_TRIGGER_TCPWM1_TR_IN11	TCPWM1 trigger multiplexer - tcpwm[1].tr_in[11].
CYHAL_TRIGGER_TCPWM1_TR_IN12	TCPWM1 trigger multiplexer - tcpwm[1].tr_in[12].
CYHAL_TRIGGER_TCPWM1_TR_IN13	TCPWM1 trigger multiplexer - tcpwm[1].tr_in[13].
CYHAL_TRIGGER_USB_DMA_BURSTEND0	USB PDMA0 Acknowledge Triggers - usb.dma_burstend[0].
CYHAL_TRIGGER_USB_DMA_BURSTEND1	USB PDMA0 Acknowledge Triggers - usb.dma_burstend[1].
CYHAL_TRIGGER_USB_DMA_BURSTEND2	USB PDMA0 Acknowledge Triggers - usb.dma_burstend[2].
CYHAL_TRIGGER_USB_DMA_BURSTEND3	USB PDMA0 Acknowledge Triggers - usb.dma_burstend[3].
CYHAL_TRIGGER_USB_DMA_BURSTEND4	USB PDMA0 Acknowledge Triggers - usb.dma_burstend[4].
CYHAL_TRIGGER_USB_DMA_BURSTEND5	USB PDMA0 Acknowledge Triggers - usb.dma_burstend[5].
CYHAL_TRIGGER_USB_DMA_BURSTEND6	USB PDMA0 Acknowledge Triggers - usb.dma_burstend[6].
CYHAL_TRIGGER_USB_DMA_BURSTEND7	USB PDMA0 Acknowledge Triggers - usb.dma_burstend[7].