CYW20829

General Description

Trigger connections for cyw20829.

Macros
#define	CYHAL_TRIGGER_CPUSS_ZERO   (CYHAL_TRIGGER_CPUSS_ZERO_LEVEL)
	Deprecated defines for signals that can be either level or edge. More...
#define	CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN0   (CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN0_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN1   (CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN1_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN2   (CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN2_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN3   (CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN3_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN4   (CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN4_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN5   (CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN5_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN6   (CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN6_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN7   (CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN7_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_TCPWM0_TR_OUT00   (CYHAL_TRIGGER_TCPWM0_TR_OUT00_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_TCPWM0_TR_OUT01   (CYHAL_TRIGGER_TCPWM0_TR_OUT01_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_TCPWM0_TR_OUT0256   (CYHAL_TRIGGER_TCPWM0_TR_OUT0256_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_TCPWM0_TR_OUT0257   (CYHAL_TRIGGER_TCPWM0_TR_OUT0257_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_TCPWM0_TR_OUT0258   (CYHAL_TRIGGER_TCPWM0_TR_OUT0258_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_TCPWM0_TR_OUT0259   (CYHAL_TRIGGER_TCPWM0_TR_OUT0259_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_TCPWM0_TR_OUT0260   (CYHAL_TRIGGER_TCPWM0_TR_OUT0260_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_TCPWM0_TR_OUT0261   (CYHAL_TRIGGER_TCPWM0_TR_OUT0261_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_TCPWM0_TR_OUT0262   (CYHAL_TRIGGER_TCPWM0_TR_OUT0262_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_TCPWM0_TR_OUT10   (CYHAL_TRIGGER_TCPWM0_TR_OUT10_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_TCPWM0_TR_OUT11   (CYHAL_TRIGGER_TCPWM0_TR_OUT11_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_TCPWM0_TR_OUT1256   (CYHAL_TRIGGER_TCPWM0_TR_OUT1256_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_TCPWM0_TR_OUT1257   (CYHAL_TRIGGER_TCPWM0_TR_OUT1257_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_TCPWM0_TR_OUT1258   (CYHAL_TRIGGER_TCPWM0_TR_OUT1258_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_TCPWM0_TR_OUT1259   (CYHAL_TRIGGER_TCPWM0_TR_OUT1259_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_TCPWM0_TR_OUT1260   (CYHAL_TRIGGER_TCPWM0_TR_OUT1260_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_TCPWM0_TR_OUT1261   (CYHAL_TRIGGER_TCPWM0_TR_OUT1261_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_TCPWM0_TR_OUT1262   (CYHAL_TRIGGER_TCPWM0_TR_OUT1262_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.

Typedefs
typedef cyhal_trigger_source_cyw20829_t	cyhal_source_t
	Typedef from device family specific trigger source to generic trigger source.
typedef cyhal_trigger_dest_cyw20829_t	cyhal_dest_t
	Typedef from device family specific trigger dest to generic trigger dest.

Enumerations
enum	cyhal_trigger_source_cyw20829_t {   CYHAL_TRIGGER_CPUSS_ZERO_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_ZERO, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CPUSS_ZERO_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_ZERO, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_ADCMIC_TR_ADCMIC_DATA = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_ADCMIC_TR_ADCMIC_DATA, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_ADCMIC_TR_ADCMIC_DC = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_ADCMIC_TR_ADCMIC_DC, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_BTSS_TR_RX_PACKET_SYNC = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_BTSS_TR_RX_PACKET_SYNC, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_BTSS_TR_TX_START = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_BTSS_TR_TX_START, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CANFD0_TR_DBG_DMA_REQ0 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD0_TR_DBG_DMA_REQ0, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_CANFD0_TR_FIFO00 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD0_TR_FIFO00, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_CANFD0_TR_FIFO10 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD0_TR_FIFO10, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_CANFD0_TR_TMP_RTP_OUT0 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD0_TR_TMP_RTP_OUT0, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CPUSS_CTI_TR_OUT0 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_CTI_TR_OUT0, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CPUSS_CTI_TR_OUT1 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_CTI_TR_OUT1, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CPUSS_DW0_TR_OUT0 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT0, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CPUSS_DW0_TR_OUT1 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT1, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CPUSS_DW0_TR_OUT2 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT2, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CPUSS_DW0_TR_OUT3 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT3, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CPUSS_DW0_TR_OUT4 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT4, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CPUSS_DW0_TR_OUT5 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT5, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CPUSS_DW0_TR_OUT6 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT6, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CPUSS_DW0_TR_OUT7 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT7, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CPUSS_DW0_TR_OUT8 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT8, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CPUSS_DW0_TR_OUT9 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT9, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CPUSS_DW0_TR_OUT10 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT10, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CPUSS_DW0_TR_OUT11 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT11, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CPUSS_DW0_TR_OUT12 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT12, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CPUSS_DW0_TR_OUT13 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT13, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CPUSS_DW0_TR_OUT14 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT14, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CPUSS_DW0_TR_OUT15 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT15, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_CRYPTO_TR_TRNG_BITSTREAM = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CRYPTO_TR_TRNG_BITSTREAM, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN0_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN0, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN0_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN0, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN1_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN1, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN1_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN1, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN2_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN2, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN2_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN2, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN3_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN3, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN3_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN3, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN4_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN4, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN4_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN4, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN5_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN5, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN5_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN5, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN6_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN6, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN6_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN6, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN7_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN7, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN7_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN7, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_PDM_TR_RX_REQ_ALL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PDM_TR_RX_REQ_ALL, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_PDM_TR_RX_REQ0 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PDM_TR_RX_REQ0, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_PDM_TR_RX_REQ1 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PDM_TR_RX_REQ1, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_SCB0_TR_I2C_SCL_FILTERED = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB0_TR_I2C_SCL_FILTERED, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_SCB2_TR_I2C_SCL_FILTERED = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB2_TR_I2C_SCL_FILTERED, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_SCB0_TR_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB0_TR_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_SCB1_TR_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB1_TR_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_SCB2_TR_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB2_TR_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_SCB0_TR_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB0_TR_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_SCB1_TR_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB1_TR_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_SCB2_TR_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB2_TR_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_SMIF_TR_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SMIF_TR_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_SMIF_TR_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SMIF_TR_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_TCPWM0_TR_OUT00_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT00, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM0_TR_OUT00_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT00, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_TCPWM0_TR_OUT01_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT01, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM0_TR_OUT01_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT01, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_TCPWM0_TR_OUT0256_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0256, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM0_TR_OUT0256_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0256, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_TCPWM0_TR_OUT0257_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0257, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM0_TR_OUT0257_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0257, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_TCPWM0_TR_OUT0258_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0258, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM0_TR_OUT0258_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0258, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_TCPWM0_TR_OUT0259_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0259, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM0_TR_OUT0259_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0259, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_TCPWM0_TR_OUT0260_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0260, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM0_TR_OUT0260_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0260, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_TCPWM0_TR_OUT0261_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0261, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM0_TR_OUT0261_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0261, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_TCPWM0_TR_OUT0262_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0262, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM0_TR_OUT0262_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0262, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_TCPWM0_TR_OUT10_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT10, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM0_TR_OUT10_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT10, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_TCPWM0_TR_OUT11_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT11, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM0_TR_OUT11_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT11, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_TCPWM0_TR_OUT1256_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1256, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM0_TR_OUT1256_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1256, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_TCPWM0_TR_OUT1257_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1257, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM0_TR_OUT1257_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1257, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_TCPWM0_TR_OUT1258_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1258, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM0_TR_OUT1258_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1258, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_TCPWM0_TR_OUT1259_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1259, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM0_TR_OUT1259_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1259, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_TCPWM0_TR_OUT1260_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1260, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM0_TR_OUT1260_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1260, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_TCPWM0_TR_OUT1261_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1261, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM0_TR_OUT1261_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1261, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_TCPWM0_TR_OUT1262_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1262, CYHAL_SIGNAL_TYPE_EDGE) ,   CYHAL_TRIGGER_TCPWM0_TR_OUT1262_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1262, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_TDM_TR_RX_REQ0 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TDM_TR_RX_REQ0, CYHAL_SIGNAL_TYPE_LEVEL) ,   CYHAL_TRIGGER_TDM_TR_TX_REQ0 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TDM_TR_TX_REQ0, CYHAL_SIGNAL_TYPE_LEVEL) }
	Name of each input trigger. More...
enum	cyhal_trigger_dest_cyw20829_t {   CYHAL_TRIGGER_CANFD0_TR_DBG_DMA_ACK0 = 0 ,   CYHAL_TRIGGER_CANFD0_TR_EVT_SWT_IN0 = 1 ,   CYHAL_TRIGGER_CPUSS_CTI_TR_IN0 = 2 ,   CYHAL_TRIGGER_CPUSS_CTI_TR_IN1 = 3 ,   CYHAL_TRIGGER_CPUSS_DW0_TR_IN0 = 4 ,   CYHAL_TRIGGER_CPUSS_DW0_TR_IN1 = 5 ,   CYHAL_TRIGGER_CPUSS_DW0_TR_IN2 = 6 ,   CYHAL_TRIGGER_CPUSS_DW0_TR_IN3 = 7 ,   CYHAL_TRIGGER_CPUSS_DW0_TR_IN4 = 8 ,   CYHAL_TRIGGER_CPUSS_DW0_TR_IN5 = 9 ,   CYHAL_TRIGGER_CPUSS_DW0_TR_IN6 = 10 ,   CYHAL_TRIGGER_CPUSS_DW0_TR_IN7 = 11 ,   CYHAL_TRIGGER_CPUSS_DW0_TR_IN8 = 12 ,   CYHAL_TRIGGER_CPUSS_DW0_TR_IN9 = 13 ,   CYHAL_TRIGGER_CPUSS_DW0_TR_IN10 = 14 ,   CYHAL_TRIGGER_CPUSS_DW0_TR_IN11 = 15 ,   CYHAL_TRIGGER_CPUSS_DW0_TR_IN12 = 16 ,   CYHAL_TRIGGER_CPUSS_DW0_TR_IN13 = 17 ,   CYHAL_TRIGGER_CPUSS_DW0_TR_IN14 = 18 ,   CYHAL_TRIGGER_CPUSS_DW0_TR_IN15 = 19 ,   CYHAL_TRIGGER_IOSS_PERI_TR_IO_OUTPUT_OUT0 = 20 ,   CYHAL_TRIGGER_IOSS_PERI_TR_IO_OUTPUT_OUT1 = 21 ,   CYHAL_TRIGGER_LIN0_TR_CMD_TX_HEADER0 = 22 ,   CYHAL_TRIGGER_LIN0_TR_CMD_TX_HEADER1 = 23 ,   CYHAL_TRIGGER_PDM_TR_ACTIVATE0 = 24 ,   CYHAL_TRIGGER_PDM_TR_ACTIVATE1 = 25 ,   CYHAL_TRIGGER_PDM_TR_DBG_FREEZE = 26 ,   CYHAL_TRIGGER_PERI_TR_DBG_FREEZE = 27 ,   CYHAL_TRIGGER_SRSS_TR_DEBUG_FREEZE_MCWDT0 = 28 ,   CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN0 = 29 ,   CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN1 = 30 ,   CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN2 = 31 ,   CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN3 = 32 ,   CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN4 = 33 ,   CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN5 = 34 ,   CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN6 = 35 ,   CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN7 = 36 ,   CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN8 = 37 ,   CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN9 = 38 ,   CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN10 = 39 ,   CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN11 = 40 ,   CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN12 = 41 ,   CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN13 = 42 ,   CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN14 = 43 ,   CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN15 = 44 ,   CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN16 = 45 ,   CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN17 = 46 ,   CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN18 = 47 ,   CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN19 = 48 ,   CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN20 = 49 ,   CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN21 = 50 ,   CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN22 = 51 ,   CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN23 = 52 ,   CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN24 = 53 ,   CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN25 = 54 ,   CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN26 = 55 ,   CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN27 = 56 ,   CYHAL_TRIGGER_TCPWM0_TR_DEBUG_FREEZE = 57 ,   CYHAL_TRIGGER_TDM_TR_DBG_FREEZE = 58 }
	Name of each output trigger. More...

Macro Definition Documentation

CYHAL_TRIGGER_CPUSS_ZERO

#define CYHAL_TRIGGER_CPUSS_ZERO   (CYHAL_TRIGGER_CPUSS_ZERO_LEVEL)

Deprecated defines for signals that can be either level or edge.

Legacy define. Instead, use the explicit _LEVEL or _EDGE version.

Enumeration Type Documentation

cyhal_trigger_source_cyw20829_t

enum cyhal_trigger_source_cyw20829_t

Name of each input trigger.

Enumerator
CYHAL_TRIGGER_CPUSS_ZERO_EDGE	cpuss.zero
CYHAL_TRIGGER_CPUSS_ZERO_LEVEL	cpuss.zero
CYHAL_TRIGGER_ADCMIC_TR_ADCMIC_DATA	adcmic.tr_adcmic_data
CYHAL_TRIGGER_ADCMIC_TR_ADCMIC_DC	adcmic.tr_adcmic_dc
CYHAL_TRIGGER_BTSS_TR_RX_PACKET_SYNC	btss.tr_rx_packet_sync
CYHAL_TRIGGER_BTSS_TR_TX_START	btss.tr_tx_start
CYHAL_TRIGGER_CANFD0_TR_DBG_DMA_REQ0	canfd[0].tr_dbg_dma_req[0]
CYHAL_TRIGGER_CANFD0_TR_FIFO00	canfd[0].tr_fifo0[0]
CYHAL_TRIGGER_CANFD0_TR_FIFO10	canfd[0].tr_fifo1[0]
CYHAL_TRIGGER_CANFD0_TR_TMP_RTP_OUT0	canfd[0].tr_tmp_rtp_out[0]
CYHAL_TRIGGER_CPUSS_CTI_TR_OUT0	cpuss.cti_tr_out[0]
CYHAL_TRIGGER_CPUSS_CTI_TR_OUT1	cpuss.cti_tr_out[1]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT0	cpuss.dw0_tr_out[0]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT1	cpuss.dw0_tr_out[1]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT2	cpuss.dw0_tr_out[2]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT3	cpuss.dw0_tr_out[3]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT4	cpuss.dw0_tr_out[4]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT5	cpuss.dw0_tr_out[5]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT6	cpuss.dw0_tr_out[6]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT7	cpuss.dw0_tr_out[7]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT8	cpuss.dw0_tr_out[8]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT9	cpuss.dw0_tr_out[9]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT10	cpuss.dw0_tr_out[10]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT11	cpuss.dw0_tr_out[11]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT12	cpuss.dw0_tr_out[12]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT13	cpuss.dw0_tr_out[13]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT14	cpuss.dw0_tr_out[14]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT15	cpuss.dw0_tr_out[15]
CYHAL_TRIGGER_CRYPTO_TR_TRNG_BITSTREAM	crypto.tr_trng_bitstream
CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN0_EDGE	ioss.peri_tr_io_input_in[0]
CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN0_LEVEL	ioss.peri_tr_io_input_in[0]
CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN1_EDGE	ioss.peri_tr_io_input_in[1]
CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN1_LEVEL	ioss.peri_tr_io_input_in[1]
CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN2_EDGE	ioss.peri_tr_io_input_in[2]
CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN2_LEVEL	ioss.peri_tr_io_input_in[2]
CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN3_EDGE	ioss.peri_tr_io_input_in[3]
CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN3_LEVEL	ioss.peri_tr_io_input_in[3]
CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN4_EDGE	ioss.peri_tr_io_input_in[4]
CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN4_LEVEL	ioss.peri_tr_io_input_in[4]
CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN5_EDGE	ioss.peri_tr_io_input_in[5]
CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN5_LEVEL	ioss.peri_tr_io_input_in[5]
CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN6_EDGE	ioss.peri_tr_io_input_in[6]
CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN6_LEVEL	ioss.peri_tr_io_input_in[6]
CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN7_EDGE	ioss.peri_tr_io_input_in[7]
CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN7_LEVEL	ioss.peri_tr_io_input_in[7]
CYHAL_TRIGGER_PDM_TR_RX_REQ_ALL	pdm.tr_rx_req_all
CYHAL_TRIGGER_PDM_TR_RX_REQ0	pdm.tr_rx_req[0]
CYHAL_TRIGGER_PDM_TR_RX_REQ1	pdm.tr_rx_req[1]
CYHAL_TRIGGER_SCB0_TR_I2C_SCL_FILTERED	scb[0].tr_i2c_scl_filtered
CYHAL_TRIGGER_SCB2_TR_I2C_SCL_FILTERED	scb[2].tr_i2c_scl_filtered
CYHAL_TRIGGER_SCB0_TR_RX_REQ	scb[0].tr_rx_req
CYHAL_TRIGGER_SCB1_TR_RX_REQ	scb[1].tr_rx_req
CYHAL_TRIGGER_SCB2_TR_RX_REQ	scb[2].tr_rx_req
CYHAL_TRIGGER_SCB0_TR_TX_REQ	scb[0].tr_tx_req
CYHAL_TRIGGER_SCB1_TR_TX_REQ	scb[1].tr_tx_req
CYHAL_TRIGGER_SCB2_TR_TX_REQ	scb[2].tr_tx_req
CYHAL_TRIGGER_SMIF_TR_RX_REQ	smif.tr_rx_req
CYHAL_TRIGGER_SMIF_TR_TX_REQ	smif.tr_tx_req
CYHAL_TRIGGER_TCPWM0_TR_OUT00_EDGE	tcpwm[0].tr_out0[0]
CYHAL_TRIGGER_TCPWM0_TR_OUT00_LEVEL	tcpwm[0].tr_out0[0]
CYHAL_TRIGGER_TCPWM0_TR_OUT01_EDGE	tcpwm[0].tr_out0[1]
CYHAL_TRIGGER_TCPWM0_TR_OUT01_LEVEL	tcpwm[0].tr_out0[1]
CYHAL_TRIGGER_TCPWM0_TR_OUT0256_EDGE	tcpwm[0].tr_out0[256]
CYHAL_TRIGGER_TCPWM0_TR_OUT0256_LEVEL	tcpwm[0].tr_out0[256]
CYHAL_TRIGGER_TCPWM0_TR_OUT0257_EDGE	tcpwm[0].tr_out0[257]
CYHAL_TRIGGER_TCPWM0_TR_OUT0257_LEVEL	tcpwm[0].tr_out0[257]
CYHAL_TRIGGER_TCPWM0_TR_OUT0258_EDGE	tcpwm[0].tr_out0[258]
CYHAL_TRIGGER_TCPWM0_TR_OUT0258_LEVEL	tcpwm[0].tr_out0[258]
CYHAL_TRIGGER_TCPWM0_TR_OUT0259_EDGE	tcpwm[0].tr_out0[259]
CYHAL_TRIGGER_TCPWM0_TR_OUT0259_LEVEL	tcpwm[0].tr_out0[259]
CYHAL_TRIGGER_TCPWM0_TR_OUT0260_EDGE	tcpwm[0].tr_out0[260]
CYHAL_TRIGGER_TCPWM0_TR_OUT0260_LEVEL	tcpwm[0].tr_out0[260]
CYHAL_TRIGGER_TCPWM0_TR_OUT0261_EDGE	tcpwm[0].tr_out0[261]
CYHAL_TRIGGER_TCPWM0_TR_OUT0261_LEVEL	tcpwm[0].tr_out0[261]
CYHAL_TRIGGER_TCPWM0_TR_OUT0262_EDGE	tcpwm[0].tr_out0[262]
CYHAL_TRIGGER_TCPWM0_TR_OUT0262_LEVEL	tcpwm[0].tr_out0[262]
CYHAL_TRIGGER_TCPWM0_TR_OUT10_EDGE	tcpwm[0].tr_out1[0]
CYHAL_TRIGGER_TCPWM0_TR_OUT10_LEVEL	tcpwm[0].tr_out1[0]
CYHAL_TRIGGER_TCPWM0_TR_OUT11_EDGE	tcpwm[0].tr_out1[1]
CYHAL_TRIGGER_TCPWM0_TR_OUT11_LEVEL	tcpwm[0].tr_out1[1]
CYHAL_TRIGGER_TCPWM0_TR_OUT1256_EDGE	tcpwm[0].tr_out1[256]
CYHAL_TRIGGER_TCPWM0_TR_OUT1256_LEVEL	tcpwm[0].tr_out1[256]
CYHAL_TRIGGER_TCPWM0_TR_OUT1257_EDGE	tcpwm[0].tr_out1[257]
CYHAL_TRIGGER_TCPWM0_TR_OUT1257_LEVEL	tcpwm[0].tr_out1[257]
CYHAL_TRIGGER_TCPWM0_TR_OUT1258_EDGE	tcpwm[0].tr_out1[258]
CYHAL_TRIGGER_TCPWM0_TR_OUT1258_LEVEL	tcpwm[0].tr_out1[258]
CYHAL_TRIGGER_TCPWM0_TR_OUT1259_EDGE	tcpwm[0].tr_out1[259]
CYHAL_TRIGGER_TCPWM0_TR_OUT1259_LEVEL	tcpwm[0].tr_out1[259]
CYHAL_TRIGGER_TCPWM0_TR_OUT1260_EDGE	tcpwm[0].tr_out1[260]
CYHAL_TRIGGER_TCPWM0_TR_OUT1260_LEVEL	tcpwm[0].tr_out1[260]
CYHAL_TRIGGER_TCPWM0_TR_OUT1261_EDGE	tcpwm[0].tr_out1[261]
CYHAL_TRIGGER_TCPWM0_TR_OUT1261_LEVEL	tcpwm[0].tr_out1[261]
CYHAL_TRIGGER_TCPWM0_TR_OUT1262_EDGE	tcpwm[0].tr_out1[262]
CYHAL_TRIGGER_TCPWM0_TR_OUT1262_LEVEL	tcpwm[0].tr_out1[262]
CYHAL_TRIGGER_TDM_TR_RX_REQ0	tdm.tr_rx_req[0]
CYHAL_TRIGGER_TDM_TR_TX_REQ0	tdm.tr_tx_req[0]

cyhal_trigger_dest_cyw20829_t

enum cyhal_trigger_dest_cyw20829_t

Name of each output trigger.

Enumerator
CYHAL_TRIGGER_CANFD0_TR_DBG_DMA_ACK0	CAN DW0 triggers (from DW back to CAN) - canfd[0].tr_dbg_dma_ack[0].
CYHAL_TRIGGER_CANFD0_TR_EVT_SWT_IN0	CAN TT Sync - canfd[0].tr_evt_swt_in[0].
CYHAL_TRIGGER_CPUSS_CTI_TR_IN0	CPUSS Debug multiplexer - cpuss.cti_tr_in[0].
CYHAL_TRIGGER_CPUSS_CTI_TR_IN1	CPUSS Debug multiplexer - cpuss.cti_tr_in[1].
CYHAL_TRIGGER_CPUSS_DW0_TR_IN0	P-DMA0 trigger multiplexer - cpuss.dw0_tr_in[0].
CYHAL_TRIGGER_CPUSS_DW0_TR_IN1	P-DMA0 trigger multiplexer - cpuss.dw0_tr_in[1].
CYHAL_TRIGGER_CPUSS_DW0_TR_IN2	P-DMA0 trigger multiplexer - cpuss.dw0_tr_in[2].
CYHAL_TRIGGER_CPUSS_DW0_TR_IN3	P-DMA0 trigger multiplexer - cpuss.dw0_tr_in[3].
CYHAL_TRIGGER_CPUSS_DW0_TR_IN4	SCB_CAN0 - cpuss.dw0_tr_in[4].
CYHAL_TRIGGER_CPUSS_DW0_TR_IN5	SCB_CAN1 - cpuss.dw0_tr_in[5].
CYHAL_TRIGGER_CPUSS_DW0_TR_IN6	SCB DW0 Triggers - cpuss.dw0_tr_in[6].
CYHAL_TRIGGER_CPUSS_DW0_TR_IN7	SCB DW0 Triggers - cpuss.dw0_tr_in[7].
CYHAL_TRIGGER_CPUSS_DW0_TR_IN8	SCB DW0 Triggers - cpuss.dw0_tr_in[8].
CYHAL_TRIGGER_CPUSS_DW0_TR_IN9	SCB DW0 Triggers - cpuss.dw0_tr_in[9].
CYHAL_TRIGGER_CPUSS_DW0_TR_IN10	AUDIOSS PDMA1 triggers (I2S & PDM) - cpuss.dw0_tr_in[10].
CYHAL_TRIGGER_CPUSS_DW0_TR_IN11	AUDIOSS PDMA1 triggers (I2S & PDM) - cpuss.dw0_tr_in[11].
CYHAL_TRIGGER_CPUSS_DW0_TR_IN12	AUDIOSS PDMA1 triggers (I2S & PDM) - cpuss.dw0_tr_in[12].
CYHAL_TRIGGER_CPUSS_DW0_TR_IN13	AUDIOSS PDMA1 triggers (I2S & PDM) - cpuss.dw0_tr_in[13].
CYHAL_TRIGGER_CPUSS_DW0_TR_IN14	AUDIOSS PDMA1 triggers (I2S & PDM) - cpuss.dw0_tr_in[14].
CYHAL_TRIGGER_CPUSS_DW0_TR_IN15	CAN to PDMA0 direct connect - cpuss.dw0_tr_in[15].
CYHAL_TRIGGER_IOSS_PERI_TR_IO_OUTPUT_OUT0	HSIOM trigger multiplexer - ioss.peri_tr_io_output_out[0].
CYHAL_TRIGGER_IOSS_PERI_TR_IO_OUTPUT_OUT1	HSIOM trigger multiplexer - ioss.peri_tr_io_output_out[1].
CYHAL_TRIGGER_LIN0_TR_CMD_TX_HEADER0	To LIN0 - lin[0].tr_cmd_tx_header[0].
CYHAL_TRIGGER_LIN0_TR_CMD_TX_HEADER1	To LIN0 - lin[0].tr_cmd_tx_header[1].
CYHAL_TRIGGER_PDM_TR_ACTIVATE0	TCPWM and PDM trigger multiplexer - pdm.tr_activate[0].
CYHAL_TRIGGER_PDM_TR_ACTIVATE1	TCPWM and PDM trigger multiplexer - pdm.tr_activate[1].
CYHAL_TRIGGER_PDM_TR_DBG_FREEZE	PERI Freeze trigger multiplexer - pdm.tr_dbg_freeze.
CYHAL_TRIGGER_PERI_TR_DBG_FREEZE	PERI Freeze trigger multiplexer - peri.tr_dbg_freeze.
CYHAL_TRIGGER_SRSS_TR_DEBUG_FREEZE_MCWDT0	CPUSS Debug multiplexer - srss.tr_debug_freeze_mcwdt[0].
CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN0	TCPWM0 trigger multiplexer - tcpwm[0].tr_all_cnt_in[0].
CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN1	TCPWM0 trigger multiplexer - tcpwm[0].tr_all_cnt_in[1].
CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN2	TCPWM0 trigger multiplexer - tcpwm[0].tr_all_cnt_in[2].
CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN3	TCPWM0 trigger multiplexer - tcpwm[0].tr_all_cnt_in[3].
CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN4	TCPWM0 trigger multiplexer - tcpwm[0].tr_all_cnt_in[4].
CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN5	TCPWM0 trigger multiplexer - tcpwm[0].tr_all_cnt_in[5].
CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN6	TCPWM0 trigger multiplexer - tcpwm[0].tr_all_cnt_in[6].
CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN7	TCPWM0 trigger multiplexer - tcpwm[0].tr_all_cnt_in[7].
CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN8	TCPWM0 trigger multiplexer - tcpwm[0].tr_all_cnt_in[8].
CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN9	TCPWM0 trigger multiplexer - tcpwm[0].tr_all_cnt_in[9].
CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN10	TCPWM0 trigger multiplexer - tcpwm[0].tr_all_cnt_in[10].
CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN11	TCPWM0 trigger multiplexer - tcpwm[0].tr_all_cnt_in[11].
CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN12	TCPWM0 trigger multiplexer - tcpwm[0].tr_all_cnt_in[12].
CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN13	TCPWM0 trigger multiplexer - tcpwm[0].tr_all_cnt_in[13].
CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN14	TCPWM1 trigger multiplexer - tcpwm[0].tr_all_cnt_in[14].
CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN15	TCPWM1 trigger multiplexer - tcpwm[0].tr_all_cnt_in[15].
CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN16	TCPWM1 trigger multiplexer - tcpwm[0].tr_all_cnt_in[16].
CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN17	TCPWM1 trigger multiplexer - tcpwm[0].tr_all_cnt_in[17].
CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN18	TCPWM1 trigger multiplexer - tcpwm[0].tr_all_cnt_in[18].
CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN19	TCPWM1 trigger multiplexer - tcpwm[0].tr_all_cnt_in[19].
CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN20	TCPWM1 trigger multiplexer - tcpwm[0].tr_all_cnt_in[20].
CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN21	TCPWM1 trigger multiplexer - tcpwm[0].tr_all_cnt_in[21].
CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN22	TCPWM1 trigger multiplexer - tcpwm[0].tr_all_cnt_in[22].
CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN23	TCPWM1 trigger multiplexer - tcpwm[0].tr_all_cnt_in[23].
CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN24	TCPWM1 trigger multiplexer - tcpwm[0].tr_all_cnt_in[24].
CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN25	TCPWM1 trigger multiplexer - tcpwm[0].tr_all_cnt_in[25].
CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN26	TCPWM1 trigger multiplexer - tcpwm[0].tr_all_cnt_in[26].
CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN27	TCPWM1 trigger multiplexer - tcpwm[0].tr_all_cnt_in[27].
CYHAL_TRIGGER_TCPWM0_TR_DEBUG_FREEZE	PERI Freeze trigger multiplexer - tcpwm[0].tr_debug_freeze.
CYHAL_TRIGGER_TDM_TR_DBG_FREEZE	PERI Freeze trigger multiplexer - tdm.tr_dbg_freeze.