ADC (Analog Digital Converter)

Features

The CAT1B ADC supports the following features:

• Resolution: 16 bit
• Sample rate: Fixed 480 ksps
• Minimum acquisition time: Up to 2084 ns
• SW-based async transfer only (DMA is not supported)
• VREF: CYHAL_ADC_REF_INTERNAL (1.8V) only
• Only CYHAL_POWER_LEVEL_DEFAULT and CYHAL_POWER_LEVEL_OFF are defined.
• Single ended vneg: CYHAL_ADC_VNEG_VSSA

The following functions are not supported:

• Differential channels
• Continuous scanning
• CYHAL_ADC_EOS event (this is only applicable when continuously scanning)
• Averaging. In cyhal_adc_config_t, average count must be 1 and average_mode_flags must be 0. In cyhal_adc_channel_config_t, enable_averaging must be false.
• External vref and bypass pins