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Hardware Abstraction Layer (HAL)
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Hardware Abstraction Layer (HAL)
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SDHC specific return codes.
Macros | |
| #define | CYHAL_SDHC_RSLT_ERR_PIN (CY_RSLT_CREATE_EX(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_ABSTRACTION_HAL, CYHAL_RSLT_MODULE_SDHC, 0)) |
| Pin related Error. | |
| #define | CYHAL_SDHC_RSLT_ERR_UNSUPPORTED (CY_RSLT_CREATE_EX(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_ABSTRACTION_HAL, CYHAL_RSLT_MODULE_SDHC, 1)) |
| Requested feature is not supported on this hardware. | |
| #define | CYHAL_SDHC_RSLT_ERR_ERASE_CMPLT_TIMEOUT (CY_RSLT_CREATE_EX(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_ABSTRACTION_HAL, CYHAL_RSLT_MODULE_SDHC, 2)) |
| Timeout during waiting for erase complete. | |
| #define | CYHAL_SDHC_RSLT_ERR_BLOCK_COUNT_GET_FAILURE (CY_RSLT_CREATE_EX(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_ABSTRACTION_HAL, CYHAL_RSLT_MODULE_SDHC, 3)) |
| Block count cannot be retrieved. | |
| #define | CYHAL_SDHC_RSLT_ERR_SET_FREQ (CY_RSLT_CREATE_EX(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_ABSTRACTION_HAL, CYHAL_RSLT_MODULE_SDHC, 4)) |
| Cannot set desired SD bus frequency. | |
| #define | CYHAL_SDHC_RSLT_ERR_WRONG_PARAM (CY_RSLT_CREATE_EX(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_ABSTRACTION_HAL, CYHAL_RSLT_MODULE_SDHC, 5)) |
| Incorrect function parameter. | |
| #define | CYHAL_SDHC_RSLT_ERR_IO_VOLT_SWITCH_SEQ (CY_RSLT_CREATE_EX(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_ABSTRACTION_HAL, CYHAL_RSLT_MODULE_SDHC, 6)) |
| Error occured during I/O voltage switch sequence. | |
| #define | CYHAL_SDHC_RSLT_ERR_TOUT_CFG (CY_RSLT_CREATE_EX(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_ABSTRACTION_HAL, CYHAL_RSLT_MODULE_SDHC, 7)) |
| Cannot configure data timeout. | |
| #define | CYHAL_SDHC_RSLT_ERR_CLOCK (CY_RSLT_CREATE_EX(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_ABSTRACTION_HAL, CYHAL_RSLT_MODULE_SDHC, 8)) |
| Cannot make changes in user provided clock configuration or provided clock is incorrect. | |