General Description

Features

The CAT1A/CAT2 (PMG/PSoC™ 4/PSoC™ 6/XMC7™) ADC supports the following features:

Resolution: 12 bit
Only CYHAL_POWER_LEVEL_DEFAULT and CYHAL_POWER_LEVEL_OFF are defined. The default power level will automatically adjust based on smple rate.
Average counts: 2, 4, 8, 16, 32, 64, 128, 256

CAT1A supports DMA-based transfer when using cyhal_adc_read_async. When using cyhal_adc_read_async_uv, only interrupt-driven software copy is supported.

CAT1A/CAT2 support the following features:

Up to four unique acquisition times

CAT1C supports the following features:

Unique acquisition time per channel
Single-ended channels only, referenced to VREF
Internal VREF only
No external bypass

After initializing the ADC or changing the reference or bypass selection, it may be necessary to wait up to 210 us for the reference buffer to settle. See the architecture TRM (Analog Subsystem -> SAR ADC -> Architecture -> SARREF) for device specific guidance.

Note: On CAT1C devices, the cyhal_source_t object populated by cyhal_adc_enable_output is only valid as long as the last channel initialized is not disabled, and no new channels are added. If it necessary to make any of these changes, disable the output using cyhal_adc_disable_output, then re-enable

#define	CYHAL_ADC_AVG_MODE_SEQUENTIAL (1u << (CYHAL_ADC_AVG_MODE_MAX_SHIFT + 1u))
	Convert all samples to be averaged back to back, before proceeding to the next channel. More...

Macro Definition Documentation

◆ CYHAL_ADC_AVG_MODE_SEQUENTIAL

#define CYHAL_ADC_AVG_MODE_SEQUENTIAL (1u << (CYHAL_ADC_AVG_MODE_MAX_SHIFT + 1u))

Convert all samples to be averaged back to back, before proceeding to the next channel.

Interconnect

In PSoC™ each ADC has a single input trigger which, when activated, will initiate an ADC scan. Each ADC also has an output trigger which will be activated when a scan is completed. This is the default behavior.