Pin definitions and connections specific to the XMC7100 272-BGA package.
Data Structures | |
struct | cyhal_resource_pin_mapping_t |
Represents an association between a pin and a resource. More... | |
Typedefs | |
typedef cyhal_gpio_xmc7100_272_bga_t | cyhal_gpio_t |
Create generic name for the series/package specific type. | |
Enumerations | |
enum | cyhal_gpio_xmc7100_272_bga_t { NC = 0xFFFF , P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0) , P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1) , P0_2 = CYHAL_GET_GPIO(CYHAL_PORT_0, 2) , P0_3 = CYHAL_GET_GPIO(CYHAL_PORT_0, 3) , P1_0 = CYHAL_GET_GPIO(CYHAL_PORT_1, 0) , P1_1 = CYHAL_GET_GPIO(CYHAL_PORT_1, 1) , P1_2 = CYHAL_GET_GPIO(CYHAL_PORT_1, 2) , P1_3 = CYHAL_GET_GPIO(CYHAL_PORT_1, 3) , P1_4 = CYHAL_GET_GPIO(CYHAL_PORT_1, 4) , P2_0 = CYHAL_GET_GPIO(CYHAL_PORT_2, 0) , P2_1 = CYHAL_GET_GPIO(CYHAL_PORT_2, 1) , P2_2 = CYHAL_GET_GPIO(CYHAL_PORT_2, 2) , P2_3 = CYHAL_GET_GPIO(CYHAL_PORT_2, 3) , P2_4 = CYHAL_GET_GPIO(CYHAL_PORT_2, 4) , P2_5 = CYHAL_GET_GPIO(CYHAL_PORT_2, 5) , P2_6 = CYHAL_GET_GPIO(CYHAL_PORT_2, 6) , P2_7 = CYHAL_GET_GPIO(CYHAL_PORT_2, 7) , P3_0 = CYHAL_GET_GPIO(CYHAL_PORT_3, 0) , P3_1 = CYHAL_GET_GPIO(CYHAL_PORT_3, 1) , P3_2 = CYHAL_GET_GPIO(CYHAL_PORT_3, 2) , P3_3 = CYHAL_GET_GPIO(CYHAL_PORT_3, 3) , P3_4 = CYHAL_GET_GPIO(CYHAL_PORT_3, 4) , P3_5 = CYHAL_GET_GPIO(CYHAL_PORT_3, 5) , P3_6 = CYHAL_GET_GPIO(CYHAL_PORT_3, 6) , P3_7 = CYHAL_GET_GPIO(CYHAL_PORT_3, 7) , P4_0 = CYHAL_GET_GPIO(CYHAL_PORT_4, 0) , P4_1 = CYHAL_GET_GPIO(CYHAL_PORT_4, 1) , P4_2 = CYHAL_GET_GPIO(CYHAL_PORT_4, 2) , P4_3 = CYHAL_GET_GPIO(CYHAL_PORT_4, 3) , P4_4 = CYHAL_GET_GPIO(CYHAL_PORT_4, 4) , P5_0 = CYHAL_GET_GPIO(CYHAL_PORT_5, 0) , P5_1 = CYHAL_GET_GPIO(CYHAL_PORT_5, 1) , P5_2 = CYHAL_GET_GPIO(CYHAL_PORT_5, 2) , P5_3 = CYHAL_GET_GPIO(CYHAL_PORT_5, 3) , P5_4 = CYHAL_GET_GPIO(CYHAL_PORT_5, 4) , P5_5 = CYHAL_GET_GPIO(CYHAL_PORT_5, 5) , P6_0 = CYHAL_GET_GPIO(CYHAL_PORT_6, 0) , P6_1 = CYHAL_GET_GPIO(CYHAL_PORT_6, 1) , P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2) , P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3) , P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4) , P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5) , P6_6 = CYHAL_GET_GPIO(CYHAL_PORT_6, 6) , P6_7 = CYHAL_GET_GPIO(CYHAL_PORT_6, 7) , P7_0 = CYHAL_GET_GPIO(CYHAL_PORT_7, 0) , P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1) , P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2) , P7_3 = CYHAL_GET_GPIO(CYHAL_PORT_7, 3) , P7_4 = CYHAL_GET_GPIO(CYHAL_PORT_7, 4) , P7_5 = CYHAL_GET_GPIO(CYHAL_PORT_7, 5) , P7_6 = CYHAL_GET_GPIO(CYHAL_PORT_7, 6) , P7_7 = CYHAL_GET_GPIO(CYHAL_PORT_7, 7) , P8_0 = CYHAL_GET_GPIO(CYHAL_PORT_8, 0) , P8_1 = CYHAL_GET_GPIO(CYHAL_PORT_8, 1) , P8_2 = CYHAL_GET_GPIO(CYHAL_PORT_8, 2) , P8_3 = CYHAL_GET_GPIO(CYHAL_PORT_8, 3) , P8_4 = CYHAL_GET_GPIO(CYHAL_PORT_8, 4) , P9_0 = CYHAL_GET_GPIO(CYHAL_PORT_9, 0) , P9_1 = CYHAL_GET_GPIO(CYHAL_PORT_9, 1) , P9_2 = CYHAL_GET_GPIO(CYHAL_PORT_9, 2) , P9_3 = CYHAL_GET_GPIO(CYHAL_PORT_9, 3) , P10_0 = CYHAL_GET_GPIO(CYHAL_PORT_10, 0) , P10_1 = CYHAL_GET_GPIO(CYHAL_PORT_10, 1) , P10_2 = CYHAL_GET_GPIO(CYHAL_PORT_10, 2) , P10_3 = CYHAL_GET_GPIO(CYHAL_PORT_10, 3) , P10_4 = CYHAL_GET_GPIO(CYHAL_PORT_10, 4) , P10_5 = CYHAL_GET_GPIO(CYHAL_PORT_10, 5) , P10_6 = CYHAL_GET_GPIO(CYHAL_PORT_10, 6) , P10_7 = CYHAL_GET_GPIO(CYHAL_PORT_10, 7) , P11_0 = CYHAL_GET_GPIO(CYHAL_PORT_11, 0) , P11_1 = CYHAL_GET_GPIO(CYHAL_PORT_11, 1) , P11_2 = CYHAL_GET_GPIO(CYHAL_PORT_11, 2) , P12_0 = CYHAL_GET_GPIO(CYHAL_PORT_12, 0) , P12_1 = CYHAL_GET_GPIO(CYHAL_PORT_12, 1) , P12_2 = CYHAL_GET_GPIO(CYHAL_PORT_12, 2) , P12_3 = CYHAL_GET_GPIO(CYHAL_PORT_12, 3) , P12_4 = CYHAL_GET_GPIO(CYHAL_PORT_12, 4) , P12_5 = CYHAL_GET_GPIO(CYHAL_PORT_12, 5) , P12_6 = CYHAL_GET_GPIO(CYHAL_PORT_12, 6) , P12_7 = CYHAL_GET_GPIO(CYHAL_PORT_12, 7) , P13_0 = CYHAL_GET_GPIO(CYHAL_PORT_13, 0) , P13_1 = CYHAL_GET_GPIO(CYHAL_PORT_13, 1) , P13_2 = CYHAL_GET_GPIO(CYHAL_PORT_13, 2) , P13_3 = CYHAL_GET_GPIO(CYHAL_PORT_13, 3) , P13_4 = CYHAL_GET_GPIO(CYHAL_PORT_13, 4) , P13_5 = CYHAL_GET_GPIO(CYHAL_PORT_13, 5) , P13_6 = CYHAL_GET_GPIO(CYHAL_PORT_13, 6) , P13_7 = CYHAL_GET_GPIO(CYHAL_PORT_13, 7) , P14_0 = CYHAL_GET_GPIO(CYHAL_PORT_14, 0) , P14_1 = CYHAL_GET_GPIO(CYHAL_PORT_14, 1) , P14_2 = CYHAL_GET_GPIO(CYHAL_PORT_14, 2) , P14_3 = CYHAL_GET_GPIO(CYHAL_PORT_14, 3) , P14_4 = CYHAL_GET_GPIO(CYHAL_PORT_14, 4) , P14_5 = CYHAL_GET_GPIO(CYHAL_PORT_14, 5) , P14_6 = CYHAL_GET_GPIO(CYHAL_PORT_14, 6) , P14_7 = CYHAL_GET_GPIO(CYHAL_PORT_14, 7) , P15_0 = CYHAL_GET_GPIO(CYHAL_PORT_15, 0) , P15_1 = CYHAL_GET_GPIO(CYHAL_PORT_15, 1) , P15_2 = CYHAL_GET_GPIO(CYHAL_PORT_15, 2) , P15_3 = CYHAL_GET_GPIO(CYHAL_PORT_15, 3) , P16_0 = CYHAL_GET_GPIO(CYHAL_PORT_16, 0) , P16_1 = CYHAL_GET_GPIO(CYHAL_PORT_16, 1) , P16_2 = CYHAL_GET_GPIO(CYHAL_PORT_16, 2) , P16_3 = CYHAL_GET_GPIO(CYHAL_PORT_16, 3) , P16_4 = CYHAL_GET_GPIO(CYHAL_PORT_16, 4) , P16_5 = CYHAL_GET_GPIO(CYHAL_PORT_16, 5) , P16_6 = CYHAL_GET_GPIO(CYHAL_PORT_16, 6) , P16_7 = CYHAL_GET_GPIO(CYHAL_PORT_16, 7) , P17_0 = CYHAL_GET_GPIO(CYHAL_PORT_17, 0) , P17_1 = CYHAL_GET_GPIO(CYHAL_PORT_17, 1) , P17_2 = CYHAL_GET_GPIO(CYHAL_PORT_17, 2) , P17_3 = CYHAL_GET_GPIO(CYHAL_PORT_17, 3) , P17_4 = CYHAL_GET_GPIO(CYHAL_PORT_17, 4) , P17_5 = CYHAL_GET_GPIO(CYHAL_PORT_17, 5) , P17_6 = CYHAL_GET_GPIO(CYHAL_PORT_17, 6) , P17_7 = CYHAL_GET_GPIO(CYHAL_PORT_17, 7) , P18_0 = CYHAL_GET_GPIO(CYHAL_PORT_18, 0) , P18_1 = CYHAL_GET_GPIO(CYHAL_PORT_18, 1) , P18_2 = CYHAL_GET_GPIO(CYHAL_PORT_18, 2) , P18_3 = CYHAL_GET_GPIO(CYHAL_PORT_18, 3) , P18_4 = CYHAL_GET_GPIO(CYHAL_PORT_18, 4) , P18_5 = CYHAL_GET_GPIO(CYHAL_PORT_18, 5) , P18_6 = CYHAL_GET_GPIO(CYHAL_PORT_18, 6) , P18_7 = CYHAL_GET_GPIO(CYHAL_PORT_18, 7) , P19_0 = CYHAL_GET_GPIO(CYHAL_PORT_19, 0) , P19_1 = CYHAL_GET_GPIO(CYHAL_PORT_19, 1) , P19_2 = CYHAL_GET_GPIO(CYHAL_PORT_19, 2) , P19_3 = CYHAL_GET_GPIO(CYHAL_PORT_19, 3) , P19_4 = CYHAL_GET_GPIO(CYHAL_PORT_19, 4) , P20_0 = CYHAL_GET_GPIO(CYHAL_PORT_20, 0) , P20_1 = CYHAL_GET_GPIO(CYHAL_PORT_20, 1) , P20_2 = CYHAL_GET_GPIO(CYHAL_PORT_20, 2) , P20_3 = CYHAL_GET_GPIO(CYHAL_PORT_20, 3) , P20_4 = CYHAL_GET_GPIO(CYHAL_PORT_20, 4) , P20_5 = CYHAL_GET_GPIO(CYHAL_PORT_20, 5) , P20_6 = CYHAL_GET_GPIO(CYHAL_PORT_20, 6) , P20_7 = CYHAL_GET_GPIO(CYHAL_PORT_20, 7) , P21_0 = CYHAL_GET_GPIO(CYHAL_PORT_21, 0) , P21_1 = CYHAL_GET_GPIO(CYHAL_PORT_21, 1) , P21_2 = CYHAL_GET_GPIO(CYHAL_PORT_21, 2) , P21_3 = CYHAL_GET_GPIO(CYHAL_PORT_21, 3) , P21_4 = CYHAL_GET_GPIO(CYHAL_PORT_21, 4) , P21_5 = CYHAL_GET_GPIO(CYHAL_PORT_21, 5) , P21_6 = CYHAL_GET_GPIO(CYHAL_PORT_21, 6) , P21_7 = CYHAL_GET_GPIO(CYHAL_PORT_21, 7) , P22_1 = CYHAL_GET_GPIO(CYHAL_PORT_22, 1) , P22_2 = CYHAL_GET_GPIO(CYHAL_PORT_22, 2) , P22_3 = CYHAL_GET_GPIO(CYHAL_PORT_22, 3) , P22_4 = CYHAL_GET_GPIO(CYHAL_PORT_22, 4) , P22_5 = CYHAL_GET_GPIO(CYHAL_PORT_22, 5) , P22_6 = CYHAL_GET_GPIO(CYHAL_PORT_22, 6) , P22_7 = CYHAL_GET_GPIO(CYHAL_PORT_22, 7) , P23_0 = CYHAL_GET_GPIO(CYHAL_PORT_23, 0) , P23_1 = CYHAL_GET_GPIO(CYHAL_PORT_23, 1) , P23_2 = CYHAL_GET_GPIO(CYHAL_PORT_23, 2) , P23_3 = CYHAL_GET_GPIO(CYHAL_PORT_23, 3) , P23_4 = CYHAL_GET_GPIO(CYHAL_PORT_23, 4) , P23_5 = CYHAL_GET_GPIO(CYHAL_PORT_23, 5) , P23_6 = CYHAL_GET_GPIO(CYHAL_PORT_23, 6) , P23_7 = CYHAL_GET_GPIO(CYHAL_PORT_23, 7) , P24_0 = CYHAL_GET_GPIO(CYHAL_PORT_24, 0) , P24_1 = CYHAL_GET_GPIO(CYHAL_PORT_24, 1) , P24_2 = CYHAL_GET_GPIO(CYHAL_PORT_24, 2) , P24_3 = CYHAL_GET_GPIO(CYHAL_PORT_24, 3) , P24_4 = CYHAL_GET_GPIO(CYHAL_PORT_24, 4) , P25_0 = CYHAL_GET_GPIO(CYHAL_PORT_25, 0) , P25_1 = CYHAL_GET_GPIO(CYHAL_PORT_25, 1) , P25_2 = CYHAL_GET_GPIO(CYHAL_PORT_25, 2) , P25_3 = CYHAL_GET_GPIO(CYHAL_PORT_25, 3) , P25_4 = CYHAL_GET_GPIO(CYHAL_PORT_25, 4) , P25_5 = CYHAL_GET_GPIO(CYHAL_PORT_25, 5) , P25_6 = CYHAL_GET_GPIO(CYHAL_PORT_25, 6) , P25_7 = CYHAL_GET_GPIO(CYHAL_PORT_25, 7) , P26_0 = CYHAL_GET_GPIO(CYHAL_PORT_26, 0) , P26_1 = CYHAL_GET_GPIO(CYHAL_PORT_26, 1) , P26_2 = CYHAL_GET_GPIO(CYHAL_PORT_26, 2) , P26_3 = CYHAL_GET_GPIO(CYHAL_PORT_26, 3) , P26_4 = CYHAL_GET_GPIO(CYHAL_PORT_26, 4) , P26_5 = CYHAL_GET_GPIO(CYHAL_PORT_26, 5) , P26_6 = CYHAL_GET_GPIO(CYHAL_PORT_26, 6) , P26_7 = CYHAL_GET_GPIO(CYHAL_PORT_26, 7) , P27_0 = CYHAL_GET_GPIO(CYHAL_PORT_27, 0) , P27_1 = CYHAL_GET_GPIO(CYHAL_PORT_27, 1) , P27_2 = CYHAL_GET_GPIO(CYHAL_PORT_27, 2) , P27_3 = CYHAL_GET_GPIO(CYHAL_PORT_27, 3) , P27_4 = CYHAL_GET_GPIO(CYHAL_PORT_27, 4) , P27_5 = CYHAL_GET_GPIO(CYHAL_PORT_27, 5) , P27_6 = CYHAL_GET_GPIO(CYHAL_PORT_27, 6) , P27_7 = CYHAL_GET_GPIO(CYHAL_PORT_27, 7) , P28_0 = CYHAL_GET_GPIO(CYHAL_PORT_28, 0) , P28_1 = CYHAL_GET_GPIO(CYHAL_PORT_28, 1) , P28_2 = CYHAL_GET_GPIO(CYHAL_PORT_28, 2) , P28_3 = CYHAL_GET_GPIO(CYHAL_PORT_28, 3) , P28_4 = CYHAL_GET_GPIO(CYHAL_PORT_28, 4) , P28_5 = CYHAL_GET_GPIO(CYHAL_PORT_28, 5) , P28_6 = CYHAL_GET_GPIO(CYHAL_PORT_28, 6) , P28_7 = CYHAL_GET_GPIO(CYHAL_PORT_28, 7) , P29_0 = CYHAL_GET_GPIO(CYHAL_PORT_29, 0) , P29_1 = CYHAL_GET_GPIO(CYHAL_PORT_29, 1) , P29_2 = CYHAL_GET_GPIO(CYHAL_PORT_29, 2) , P29_3 = CYHAL_GET_GPIO(CYHAL_PORT_29, 3) , P29_4 = CYHAL_GET_GPIO(CYHAL_PORT_29, 4) , P29_5 = CYHAL_GET_GPIO(CYHAL_PORT_29, 5) , P29_6 = CYHAL_GET_GPIO(CYHAL_PORT_29, 6) , P29_7 = CYHAL_GET_GPIO(CYHAL_PORT_29, 7) , P30_0 = CYHAL_GET_GPIO(CYHAL_PORT_30, 0) , P30_1 = CYHAL_GET_GPIO(CYHAL_PORT_30, 1) , P30_2 = CYHAL_GET_GPIO(CYHAL_PORT_30, 2) , P30_3 = CYHAL_GET_GPIO(CYHAL_PORT_30, 3) , P31_0 = CYHAL_GET_GPIO(CYHAL_PORT_31, 0) , P31_1 = CYHAL_GET_GPIO(CYHAL_PORT_31, 1) , P31_2 = CYHAL_GET_GPIO(CYHAL_PORT_31, 2) , P32_0 = CYHAL_GET_GPIO(CYHAL_PORT_32, 0) , P32_1 = CYHAL_GET_GPIO(CYHAL_PORT_32, 1) , P32_2 = CYHAL_GET_GPIO(CYHAL_PORT_32, 2) , P32_3 = CYHAL_GET_GPIO(CYHAL_PORT_32, 3) , P32_4 = CYHAL_GET_GPIO(CYHAL_PORT_32, 4) , P32_5 = CYHAL_GET_GPIO(CYHAL_PORT_32, 5) , P32_6 = CYHAL_GET_GPIO(CYHAL_PORT_32, 6) , P32_7 = CYHAL_GET_GPIO(CYHAL_PORT_32, 7) } |
Definitions for all of the pins that are bonded out on in the 272-BGA package for the XMC7100 series. More... | |
Variables | |
const cyhal_resource_pin_mapping_t | cyhal_pin_map_audioss_clk_i2s_if [3] |
List of valid pin to peripheral connections for the audioss_clk_i2s_if signal. | |
const cyhal_resource_pin_mapping_t | cyhal_pin_map_audioss_mclk [3] |
List of valid pin to peripheral connections for the audioss_mclk signal. | |
const cyhal_resource_pin_mapping_t | cyhal_pin_map_audioss_rx_sck [3] |
List of valid pin to peripheral connections for the audioss_rx_sck signal. | |
const cyhal_resource_pin_mapping_t | cyhal_pin_map_audioss_rx_sdi [3] |
List of valid pin to peripheral connections for the audioss_rx_sdi signal. | |
const cyhal_resource_pin_mapping_t | cyhal_pin_map_audioss_rx_ws [3] |
List of valid pin to peripheral connections for the audioss_rx_ws signal. | |
const cyhal_resource_pin_mapping_t | cyhal_pin_map_audioss_tx_sck [3] |
List of valid pin to peripheral connections for the audioss_tx_sck signal. | |
const cyhal_resource_pin_mapping_t | cyhal_pin_map_audioss_tx_sdo [3] |
List of valid pin to peripheral connections for the audioss_tx_sdo signal. | |
const cyhal_resource_pin_mapping_t | cyhal_pin_map_audioss_tx_ws [3] |
List of valid pin to peripheral connections for the audioss_tx_ws signal. | |
const cyhal_resource_pin_mapping_t | cyhal_pin_map_canfd_ttcan_rx [18] |
List of valid pin to peripheral connections for the canfd_ttcan_rx signal. | |
const cyhal_resource_pin_mapping_t | cyhal_pin_map_canfd_ttcan_tx [18] |
List of valid pin to peripheral connections for the canfd_ttcan_tx signal. | |
const cyhal_resource_pin_mapping_t | cyhal_pin_map_cpuss_cal_sup_nz [3] |
List of valid pin to peripheral connections for the cpuss_cal_sup_nz signal. | |
const cyhal_resource_pin_mapping_t | cyhal_pin_map_cpuss_clk_fm_pump [1] |
List of valid pin to peripheral connections for the cpuss_clk_fm_pump signal. | |
const cyhal_resource_pin_mapping_t | cyhal_pin_map_cpuss_fault_out [8] |
List of valid pin to peripheral connections for the cpuss_fault_out signal. | |
const cyhal_resource_pin_mapping_t | cyhal_pin_map_cpuss_swj_swclk_tclk [1] |
List of valid pin to peripheral connections for the cpuss_swj_swclk_tclk signal. | |
const cyhal_resource_pin_mapping_t | cyhal_pin_map_cpuss_swj_swdio_tms [1] |
List of valid pin to peripheral connections for the cpuss_swj_swdio_tms signal. | |
const cyhal_resource_pin_mapping_t | cyhal_pin_map_cpuss_swj_swdoe_tdi [1] |
List of valid pin to peripheral connections for the cpuss_swj_swdoe_tdi signal. | |
const cyhal_resource_pin_mapping_t | cyhal_pin_map_cpuss_swj_swo_tdo [1] |
List of valid pin to peripheral connections for the cpuss_swj_swo_tdo signal. | |
const cyhal_resource_pin_mapping_t | cyhal_pin_map_cpuss_swj_trstn [1] |
List of valid pin to peripheral connections for the cpuss_swj_trstn signal. | |
const cyhal_resource_pin_mapping_t | cyhal_pin_map_cpuss_trace_clock [2] |
List of valid pin to peripheral connections for the cpuss_trace_clock signal. | |
const cyhal_resource_pin_mapping_t | cyhal_pin_map_cpuss_trace_data [8] |
List of valid pin to peripheral connections for the cpuss_trace_data signal. | |
const cyhal_resource_pin_mapping_t | cyhal_pin_map_eth_eth_tsu_timer_cmp_val [1] |
List of valid pin to peripheral connections for the eth_eth_tsu_timer_cmp_val signal. | |
const cyhal_resource_pin_mapping_t | cyhal_pin_map_eth_mdc [1] |
List of valid pin to peripheral connections for the eth_mdc signal. | |
const cyhal_resource_pin_mapping_t | cyhal_pin_map_eth_mdio [1] |
List of valid pin to peripheral connections for the eth_mdio signal. | |
const cyhal_resource_pin_mapping_t | cyhal_pin_map_eth_ref_clk [1] |
List of valid pin to peripheral connections for the eth_ref_clk signal. | |
const cyhal_resource_pin_mapping_t | cyhal_pin_map_eth_rx_clk [1] |
List of valid pin to peripheral connections for the eth_rx_clk signal. | |
const cyhal_resource_pin_mapping_t | cyhal_pin_map_eth_rx_ctl [1] |
List of valid pin to peripheral connections for the eth_rx_ctl signal. | |
const cyhal_resource_pin_mapping_t | cyhal_pin_map_eth_rx_er [1] |
List of valid pin to peripheral connections for the eth_rx_er signal. | |
const cyhal_resource_pin_mapping_t | cyhal_pin_map_eth_rxd [4] |
List of valid pin to peripheral connections for the eth_rxd signal. | |
const cyhal_resource_pin_mapping_t | cyhal_pin_map_eth_tx_clk [1] |
List of valid pin to peripheral connections for the eth_tx_clk signal. | |
const cyhal_resource_pin_mapping_t | cyhal_pin_map_eth_tx_ctl [1] |
List of valid pin to peripheral connections for the eth_tx_ctl signal. | |
const cyhal_resource_pin_mapping_t | cyhal_pin_map_eth_tx_er [1] |
List of valid pin to peripheral connections for the eth_tx_er signal. | |
const cyhal_resource_pin_mapping_t | cyhal_pin_map_eth_txd [4] |
List of valid pin to peripheral connections for the eth_txd signal. | |
const cyhal_resource_pin_mapping_t | cyhal_pin_map_lin_lin_en [29] |
List of valid pin to peripheral connections for the lin_lin_en signal. | |
const cyhal_resource_pin_mapping_t | cyhal_pin_map_lin_lin_rx [40] |
List of valid pin to peripheral connections for the lin_lin_rx signal. | |
const cyhal_resource_pin_mapping_t | cyhal_pin_map_lin_lin_tx [39] |
List of valid pin to peripheral connections for the lin_lin_tx signal. | |
const cyhal_resource_pin_mapping_t | cyhal_pin_map_pass_sar_ext_mux_en [3] |
List of valid pin to peripheral connections for the pass_sar_ext_mux_en signal. | |
const cyhal_resource_pin_mapping_t | cyhal_pin_map_pass_sar_ext_mux_sel [9] |
List of valid pin to peripheral connections for the pass_sar_ext_mux_sel signal. | |
const cyhal_resource_pin_mapping_t | cyhal_pin_map_pass_sarmux_pads [72] |
List of valid pin to peripheral connections for the pass_sarmux_pads signal. | |
const cyhal_resource_pin_mapping_t | cyhal_pin_map_peri_tr_io_input [32] |
List of valid pin to peripheral connections for the peri_tr_io_input signal. | |
const cyhal_resource_pin_mapping_t | cyhal_pin_map_peri_tr_io_output [6] |
List of valid pin to peripheral connections for the peri_tr_io_output signal. | |
const cyhal_resource_pin_mapping_t | cyhal_pin_map_scb_i2c_scl [21] |
List of valid pin to peripheral connections for the scb_i2c_scl signal. | |
const cyhal_resource_pin_mapping_t | cyhal_pin_map_scb_i2c_sda [21] |
List of valid pin to peripheral connections for the scb_i2c_sda signal. | |
const cyhal_resource_pin_mapping_t | cyhal_pin_map_scb_spi_m_clk [24] |
List of valid pin to peripheral connections for the scb_spi_m_clk signal. | |
const cyhal_resource_pin_mapping_t | cyhal_pin_map_scb_spi_m_miso [23] |
List of valid pin to peripheral connections for the scb_spi_m_miso signal. | |
const cyhal_resource_pin_mapping_t | cyhal_pin_map_scb_spi_m_mosi [22] |
List of valid pin to peripheral connections for the scb_spi_m_mosi signal. | |
const cyhal_resource_pin_mapping_t | cyhal_pin_map_scb_spi_m_select0 [25] |
List of valid pin to peripheral connections for the scb_spi_m_select0 signal. | |
const cyhal_resource_pin_mapping_t | cyhal_pin_map_scb_spi_m_select1 [21] |
List of valid pin to peripheral connections for the scb_spi_m_select1 signal. | |
const cyhal_resource_pin_mapping_t | cyhal_pin_map_scb_spi_m_select2 [20] |
List of valid pin to peripheral connections for the scb_spi_m_select2 signal. | |
const cyhal_resource_pin_mapping_t | cyhal_pin_map_scb_spi_m_select3 [8] |
List of valid pin to peripheral connections for the scb_spi_m_select3 signal. | |
const cyhal_resource_pin_mapping_t | cyhal_pin_map_scb_spi_s_clk [24] |
List of valid pin to peripheral connections for the scb_spi_s_clk signal. | |
const cyhal_resource_pin_mapping_t | cyhal_pin_map_scb_spi_s_miso [23] |
List of valid pin to peripheral connections for the scb_spi_s_miso signal. | |
const cyhal_resource_pin_mapping_t | cyhal_pin_map_scb_spi_s_mosi [22] |
List of valid pin to peripheral connections for the scb_spi_s_mosi signal. | |
const cyhal_resource_pin_mapping_t | cyhal_pin_map_scb_spi_s_select0 [25] |
List of valid pin to peripheral connections for the scb_spi_s_select0 signal. | |
const cyhal_resource_pin_mapping_t | cyhal_pin_map_scb_spi_s_select1 [21] |
List of valid pin to peripheral connections for the scb_spi_s_select1 signal. | |
const cyhal_resource_pin_mapping_t | cyhal_pin_map_scb_spi_s_select2 [20] |
List of valid pin to peripheral connections for the scb_spi_s_select2 signal. | |
const cyhal_resource_pin_mapping_t | cyhal_pin_map_scb_spi_s_select3 [8] |
List of valid pin to peripheral connections for the scb_spi_s_select3 signal. | |
const cyhal_resource_pin_mapping_t | cyhal_pin_map_scb_uart_cts [21] |
List of valid pin to peripheral connections for the scb_uart_cts signal. | |
const cyhal_resource_pin_mapping_t | cyhal_pin_map_scb_uart_rts [20] |
List of valid pin to peripheral connections for the scb_uart_rts signal. | |
const cyhal_resource_pin_mapping_t | cyhal_pin_map_scb_uart_rx [20] |
List of valid pin to peripheral connections for the scb_uart_rx signal. | |
const cyhal_resource_pin_mapping_t | cyhal_pin_map_scb_uart_tx [19] |
List of valid pin to peripheral connections for the scb_uart_tx signal. | |
const cyhal_resource_pin_mapping_t | cyhal_pin_map_sdhc_card_cmd [2] |
List of valid pin to peripheral connections for the sdhc_card_cmd signal. | |
const cyhal_resource_pin_mapping_t | cyhal_pin_map_sdhc_card_dat_3to0 [8] |
List of valid pin to peripheral connections for the sdhc_card_dat_3to0 signal. | |
const cyhal_resource_pin_mapping_t | cyhal_pin_map_sdhc_card_dat_7to4 [8] |
List of valid pin to peripheral connections for the sdhc_card_dat_7to4 signal. | |
const cyhal_resource_pin_mapping_t | cyhal_pin_map_sdhc_card_detect_n [2] |
List of valid pin to peripheral connections for the sdhc_card_detect_n signal. | |
const cyhal_resource_pin_mapping_t | cyhal_pin_map_sdhc_card_if_pwr_en [2] |
List of valid pin to peripheral connections for the sdhc_card_if_pwr_en signal. | |
const cyhal_resource_pin_mapping_t | cyhal_pin_map_sdhc_card_mech_write_prot [2] |
List of valid pin to peripheral connections for the sdhc_card_mech_write_prot signal. | |
const cyhal_resource_pin_mapping_t | cyhal_pin_map_sdhc_clk_card [2] |
List of valid pin to peripheral connections for the sdhc_clk_card signal. | |
const cyhal_resource_pin_mapping_t | cyhal_pin_map_smif_spi_clk [2] |
List of valid pin to peripheral connections for the smif_spi_clk signal. | |
const cyhal_resource_pin_mapping_t | cyhal_pin_map_smif_spi_data0 [2] |
List of valid pin to peripheral connections for the smif_spi_data0 signal. | |
const cyhal_resource_pin_mapping_t | cyhal_pin_map_smif_spi_data1 [2] |
List of valid pin to peripheral connections for the smif_spi_data1 signal. | |
const cyhal_resource_pin_mapping_t | cyhal_pin_map_smif_spi_data2 [2] |
List of valid pin to peripheral connections for the smif_spi_data2 signal. | |
const cyhal_resource_pin_mapping_t | cyhal_pin_map_smif_spi_data3 [2] |
List of valid pin to peripheral connections for the smif_spi_data3 signal. | |
const cyhal_resource_pin_mapping_t | cyhal_pin_map_smif_spi_data4 [2] |
List of valid pin to peripheral connections for the smif_spi_data4 signal. | |
const cyhal_resource_pin_mapping_t | cyhal_pin_map_smif_spi_data5 [2] |
List of valid pin to peripheral connections for the smif_spi_data5 signal. | |
const cyhal_resource_pin_mapping_t | cyhal_pin_map_smif_spi_data6 [2] |
List of valid pin to peripheral connections for the smif_spi_data6 signal. | |
const cyhal_resource_pin_mapping_t | cyhal_pin_map_smif_spi_data7 [2] |
List of valid pin to peripheral connections for the smif_spi_data7 signal. | |
const cyhal_resource_pin_mapping_t | cyhal_pin_map_smif_spi_rwds [2] |
List of valid pin to peripheral connections for the smif_spi_rwds signal. | |
const cyhal_resource_pin_mapping_t | cyhal_pin_map_smif_spi_select0 [2] |
List of valid pin to peripheral connections for the smif_spi_select0 signal. | |
const cyhal_resource_pin_mapping_t | cyhal_pin_map_smif_spi_select1 [2] |
List of valid pin to peripheral connections for the smif_spi_select1 signal. | |
const cyhal_resource_pin_mapping_t | cyhal_pin_map_tcpwm_line [168] |
List of valid pin to peripheral connections for the tcpwm_line signal. | |
const cyhal_resource_pin_mapping_t | cyhal_pin_map_tcpwm_line_compl [168] |
List of valid pin to peripheral connections for the tcpwm_line_compl signal. | |
const cyhal_resource_pin_mapping_t | cyhal_pin_map_tcpwm_tr_one_cnt_in [328] |
List of valid pin to peripheral connections for the tcpwm_tr_one_cnt_in signal. | |
struct cyhal_resource_pin_mapping_t |
Data Fields | ||
---|---|---|
uint8_t | block_num | The block number of the resource with this connection. |
uint8_t | channel_num | The channel number of the block with this connection. |
cyhal_gpio_t | pin | The GPIO pin the connection is with. |
en_hsiom_sel_t | hsiom | The HSIOM configuration value. |
Definitions for all of the pins that are bonded out on in the 272-BGA package for the XMC7100 series.