Hardware Abstraction Layer (HAL)
CAT1 Implementation Specific

General Description

This section provides details about the CAT1 implementation of the Cypress HAL.

All information within this section is platform specific and is provided for reference. Portable application code should depend only on the APIs and types which are documented in the HAL Drivers section.

HAL Resource Hardware Mapping

The following table shows a mapping of each HAL driver to the lower level firmware driver and the corresponding hardware resource. This is intended to help understand how the HAL is implemented for CAT1 and what features the underlying hardware supports.

HAL Resource PDL Driver(s) CAT1 Hardware
ADC cy_adc SAR ADC
Clock cy_sysclk All clocks (system & peripheral)
Comparator cy_ctb or cy_lpcomp CTBm or LPComp
CRC cy_crypto_core_crc Crypto
DAC cy_ctdac DAC
DMA cy_dma, cy_dmac DMA Controller
EZ-I2C cy_scb_ezi2c SCB
Flash cy_flash Flash
GPIO cy_gpio GPIO
Hardware Manager NA NA
I2C cy_scb_i2c SCB
I2S cy_i2s I2S
LPTimer cy_mcwdt MCWDT
Opamp cy_ctb CTBm
PDM/PCM cy_pdm_pcm PDM-PCM
PWM cy_pwm TCPWM
QSPI cy_smif QSPI (SMIF)
Quadrature Decoder cy_tcpwm_quaddec TCPWM
RTC cy_rtc RTC
SDHC cy_sd_host SD Host
SDIO cy_sd_host, or NA SD Host, or UDB
SPI cy_scb_spi SCB
SysPM cy_syspm System Power Resources
System cy_syslib System Resources
TDM cy_i2s I2S
Timer cy_tcpwm_counter TCPWM
TRNG cy_crypto_core_trng Crypto
UART cy_scb_uart SCB
USB Device cy_usbfs_dev_drv USB-FS
WDT cy_wdt WDT

Device Specific Errors

Error codes generated by the low level level PDL driver all use module IDs starting with CY_RSLT_MODULE_DRIVERS_PDL_BASE. The exact errors are documented for each driver in the mtb-pdl-cat1 documentation.

API Reference

 Clocks
 Implementation specific interface for using the Clock driver.
 
 DMA (Direct Memory Access)
 DW (DataWire) is one of two DMA hardware implementations for CAT1 (PSoC™ 6).
 
 GPIO
 
 HAL Driver Availability Macros
 
 CAT1 Specific Hardware Types
 Aliases for types which are part of the public HAL interface but whose representations need to vary per HAL implementation.
 
 Interconnect (Internal Digital Routing)
 The interconnect system connects the various hardware peripherals using trigger signals.
 
 Pins
 Definitions for the pinout for each supported device.
 
 System Power Management
 On CAT1 devices, the Pin based Hibernate wakeup sources (CYHAL_SYSPM_HIBERNATE_PINA_LOW, CYHAL_SYSPM_HIBERNATE_PINA_HIGH, CYHAL_SYSPM_HIBERNATE_PINB_LOW, and CYHAL_SYSPM_HIBERNATE_PINB_HIGH) are mapped to datsheet capabilities as follows:
PINA = hibernate_wakeup[0]
PINB = hibernate_wakeup[1].
 
 Timer (Timer/Counter)
 
 WDT (Watchdog Timer)
 The CAT1 WDT is only capable of supporting certain timeout ranges below its maximum timeout.
 
 ADC (Analog Digital Converter)
 
 ADC (Analog Digital Converter)
 
 COMP (Analog Comparator)
 On CAT1 & CAT2, the comparator driver can use either of two underlying hardware blocks:
 
 DAC (Digital to Analog Converter)
 
 I2S (Inter-IC Sound)
 The CAT1 (PSoC™ 6) I2S Supports the following values for word lengths:
 
 IRQ Muxing (Interrupt muxing)
 There are two situations where system interrupts do not correlate 1:1 to CPU interrupts.
 
 KeyScan
 On CAT1 devices, the KeyScan peripheral is clocked from the shared source CLK_MF.
 
 LPTimer (Low-Power Timer)
 The maximum number of ticks that can set to an LPTimer is 0xFFF0FFFF for non MCWDT-B devices.
 
 Opamp (Operational Amplifier)
 
 PDM/PCM (Pulse Density Modulation to Pulse Code Modulation Converter)
 The CAT1A PDM/PCM Supports the following conversion parameters:
 
 PWM (Pulse Width Modulator)
 
 QSPI (Quad Serial Peripheral Interface)
 
 QuadDec (Quadrature Decoder)
 
 RTC (Real Time Clock)
 Internally the CAT1 RTC only stores the year as a two digit BCD value (0-99); no century information is stored.
 
 SDHC (SD Host Controller)
 The SHDC HAL implemenation for CAT1 provides implementations for the following weak functions specified by the PDL to make their usage in SDHC HAL driver more flexible by providing user ability to use card detect, write protect, pwr en, and io select signals on custom pins instead of dedicated SDHC block pins.
 
 SPI (Serial Peripheral Interface)
 
 TDM (Time Division Multiplexing)
 The CAT1 (PSoC™ 6) TDM Supports the following values for word lengths:
 
 UDB SDIO (Secure Digital Input Output)
 The UDB based SDIO interface allows for communicating between a CAT1 and a Cypress wireless device such as the CYW4343W, CYW43438, or CYW43012.