General Description

Pin definitions and connections specific to the CYW20829 77-BGA package.

Data Structures
struct	cyhal_resource_pin_mapping_t
	Represents an association between a pin and a resource. More...

Macros
#define	CYHAL_GET_GPIO(port, pin) ((((uint8_t)(port)) << 3U) + ((uint8_t)(pin)))
	Gets a pin definition from the provided port and pin numbers.

#define	CYHAL_GET_PIN(pin) ((uint8_t)(((uint8_t)pin) & 0x07U))
	Macro that, given a gpio, will extract the pin number.

#define	CYHAL_GET_PORT(pin) ((uint8_t)(((uint8_t)pin) >> 3U))
	Macro that, given a gpio, will extract the port number.

#define	CYHAL_PIN_MAP_DRIVE_MODE_ADCMIC_CLK_PDM (CY_GPIO_DM_HIGHZ)
	Indicates that a pin map exists for adcmic_clk_pdm.

#define	CYHAL_PIN_MAP_DRIVE_MODE_ADCMIC_GPIO_ADC_IN (CY_GPIO_DM_ANALOG)
	Indicates that a pin map exists for adcmic_gpio_adc_in.

#define	CYHAL_PIN_MAP_DRIVE_MODE_ADCMIC_PDM_DATA (CY_GPIO_DM_HIGHZ)
	Indicates that a pin map exists for adcmic_pdm_data.

#define	CYHAL_PIN_MAP_DRIVE_MODE_CANFD_TTCAN_RX (CY_GPIO_DM_HIGHZ)
	Indicates that a pin map exists for canfd_ttcan_rx.

#define	CYHAL_PIN_MAP_DRIVE_MODE_CANFD_TTCAN_TX (CY_GPIO_DM_STRONG_IN_OFF)
	Indicates that a pin map exists for canfd_ttcan_tx.

#define	CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_CLK_SWJ_SWCLK_TCLK (CY_GPIO_DM_PULLDOWN)
	Indicates that a pin map exists for cpuss_clk_swj_swclk_tclk.

#define	CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_RST_SWJ_TRSTN (CY_GPIO_DM_PULLUP)
	Indicates that a pin map exists for cpuss_rst_swj_trstn.

#define	CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_SWJ_SWDIO_TMS (CY_GPIO_DM_PULLUP)
	Indicates that a pin map exists for cpuss_swj_swdio_tms.

#define	CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_SWJ_SWDOE_TDI (CY_GPIO_DM_PULLUP)
	Indicates that a pin map exists for cpuss_swj_swdoe_tdi.

#define	CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_SWJ_SWO_TDO (CY_GPIO_DM_STRONG_IN_OFF)
	Indicates that a pin map exists for cpuss_swj_swo_tdo.

#define	CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_TRACE_CLOCK (CY_GPIO_DM_STRONG_IN_OFF)
	Indicates that a pin map exists for cpuss_trace_clock.

#define	CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_TRACE_DATA (CY_GPIO_DM_STRONG_IN_OFF)
	Indicates that a pin map exists for cpuss_trace_data.

#define	CYHAL_PIN_MAP_DRIVE_MODE_KEYSCAN_KS_COL (CY_GPIO_DM_PULLUP)
	Indicates that a pin map exists for keyscan_ks_col.

#define	CYHAL_PIN_MAP_DRIVE_MODE_KEYSCAN_KS_ROW (CY_GPIO_DM_PULLUP)
	Indicates that a pin map exists for keyscan_ks_row.

#define	CYHAL_PIN_MAP_DRIVE_MODE_LIN_LIN_EN (CY_GPIO_DM_HIGHZ)
	Indicates that a pin map exists for lin_lin_en.

#define	CYHAL_PIN_MAP_DRIVE_MODE_LIN_LIN_RX (CY_GPIO_DM_HIGHZ)
	Indicates that a pin map exists for lin_lin_rx.

#define	CYHAL_PIN_MAP_DRIVE_MODE_LIN_LIN_TX (CY_GPIO_DM_STRONG_IN_OFF)
	Indicates that a pin map exists for lin_lin_tx.

#define	CYHAL_PIN_MAP_DRIVE_MODE_PDM_PDM_CLK (CY_GPIO_DM_STRONG_IN_OFF)
	Indicates that a pin map exists for pdm_pdm_clk.

#define	CYHAL_PIN_MAP_DRIVE_MODE_PDM_PDM_DATA (CY_GPIO_DM_HIGHZ)
	Indicates that a pin map exists for pdm_pdm_data.

#define	CYHAL_PIN_MAP_DRIVE_MODE_PERI_TR_IO_INPUT (CY_GPIO_DM_HIGHZ)
	Indicates that a pin map exists for peri_tr_io_input.

#define	CYHAL_PIN_MAP_DRIVE_MODE_PERI_TR_IO_OUTPUT (CY_GPIO_DM_HIGHZ)
	Indicates that a pin map exists for peri_tr_io_output.

#define	CYHAL_PIN_MAP_DRIVE_MODE_SCB_I2C_SCL (CY_GPIO_DM_OD_DRIVESLOW)
	Indicates that a pin map exists for scb_i2c_scl.

#define	CYHAL_PIN_MAP_DRIVE_MODE_SCB_I2C_SDA (CY_GPIO_DM_OD_DRIVESLOW)
	Indicates that a pin map exists for scb_i2c_sda.

#define	CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_CLK (CY_GPIO_DM_STRONG_IN_OFF)
	Indicates that a pin map exists for scb_spi_m_clk.

#define	CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_MISO (CY_GPIO_DM_HIGHZ)
	Indicates that a pin map exists for scb_spi_m_miso.

#define	CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_MOSI (CY_GPIO_DM_STRONG_IN_OFF)
	Indicates that a pin map exists for scb_spi_m_mosi.

#define	CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_SELECT0 (CY_GPIO_DM_STRONG_IN_OFF)
	Indicates that a pin map exists for scb_spi_m_select0.

#define	CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_SELECT1 (CY_GPIO_DM_STRONG_IN_OFF)
	Indicates that a pin map exists for scb_spi_m_select1.

#define	CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_SELECT2 (CY_GPIO_DM_STRONG_IN_OFF)
	Indicates that a pin map exists for scb_spi_m_select2.

#define	CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_SELECT3 (CY_GPIO_DM_STRONG_IN_OFF)
	Indicates that a pin map exists for scb_spi_m_select3.

#define	CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_CLK (CY_GPIO_DM_HIGHZ)
	Indicates that a pin map exists for scb_spi_s_clk.

#define	CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_MISO (CY_GPIO_DM_STRONG_IN_OFF)
	Indicates that a pin map exists for scb_spi_s_miso.

#define	CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_MOSI (CY_GPIO_DM_HIGHZ)
	Indicates that a pin map exists for scb_spi_s_mosi.

#define	CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_SELECT0 (CY_GPIO_DM_HIGHZ)
	Indicates that a pin map exists for scb_spi_s_select0.

#define	CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_SELECT1 (CY_GPIO_DM_HIGHZ)
	Indicates that a pin map exists for scb_spi_s_select1.

#define	CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_SELECT2 (CY_GPIO_DM_HIGHZ)
	Indicates that a pin map exists for scb_spi_s_select2.

#define	CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_SELECT3 (CY_GPIO_DM_HIGHZ)
	Indicates that a pin map exists for scb_spi_s_select3.

#define	CYHAL_PIN_MAP_DRIVE_MODE_SCB_UART_CTS (CY_GPIO_DM_HIGHZ)
	Indicates that a pin map exists for scb_uart_cts.

#define	CYHAL_PIN_MAP_DRIVE_MODE_SCB_UART_RTS (CY_GPIO_DM_STRONG_IN_OFF)
	Indicates that a pin map exists for scb_uart_rts.

#define	CYHAL_PIN_MAP_DRIVE_MODE_SCB_UART_RX (CY_GPIO_DM_HIGHZ)
	Indicates that a pin map exists for scb_uart_rx.

#define	CYHAL_PIN_MAP_DRIVE_MODE_SCB_UART_TX (CY_GPIO_DM_STRONG_IN_OFF)
	Indicates that a pin map exists for scb_uart_tx.

#define	CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_CLK (CY_GPIO_DM_STRONG)
	Indicates that a pin map exists for smif_spi_clk.

#define	CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_DATA0 (CY_GPIO_DM_STRONG)
	Indicates that a pin map exists for smif_spi_data0.

#define	CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_DATA1 (CY_GPIO_DM_STRONG)
	Indicates that a pin map exists for smif_spi_data1.

#define	CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_DATA2 (CY_GPIO_DM_STRONG)
	Indicates that a pin map exists for smif_spi_data2.

#define	CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_DATA3 (CY_GPIO_DM_STRONG)
	Indicates that a pin map exists for smif_spi_data3.

#define	CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_SELECT0 (CY_GPIO_DM_STRONG_IN_OFF)
	Indicates that a pin map exists for smif_spi_select0.

#define	CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_SELECT1 (CY_GPIO_DM_STRONG_IN_OFF)
	Indicates that a pin map exists for smif_spi_select1.

#define	CYHAL_PIN_MAP_DRIVE_MODE_TCPWM_LINE (CY_GPIO_DM_STRONG_IN_OFF)
	Indicates that a pin map exists for tcpwm_line.

#define	CYHAL_PIN_MAP_DRIVE_MODE_TCPWM_LINE_COMPL (CY_GPIO_DM_STRONG_IN_OFF)
	Indicates that a pin map exists for tcpwm_line_compl.

#define	CYHAL_PIN_MAP_DRIVE_MODE_TDM_TDM_RX_FSYNC (CY_GPIO_DM_STRONG_IN_OFF)
	Indicates that a pin map exists for tdm_tdm_rx_fsync.

#define	CYHAL_PIN_MAP_DRIVE_MODE_TDM_TDM_RX_MCK (CY_GPIO_DM_STRONG_IN_OFF)
	Indicates that a pin map exists for tdm_tdm_rx_mck.

#define	CYHAL_PIN_MAP_DRIVE_MODE_TDM_TDM_RX_SCK (CY_GPIO_DM_STRONG_IN_OFF)
	Indicates that a pin map exists for tdm_tdm_rx_sck.

#define	CYHAL_PIN_MAP_DRIVE_MODE_TDM_TDM_RX_SD (CY_GPIO_DM_HIGHZ)
	Indicates that a pin map exists for tdm_tdm_rx_sd.

#define	CYHAL_PIN_MAP_DRIVE_MODE_TDM_TDM_TX_FSYNC (CY_GPIO_DM_STRONG_IN_OFF)
	Indicates that a pin map exists for tdm_tdm_tx_fsync.

#define	CYHAL_PIN_MAP_DRIVE_MODE_TDM_TDM_TX_MCK (CY_GPIO_DM_STRONG_IN_OFF)
	Indicates that a pin map exists for tdm_tdm_tx_mck.

#define	CYHAL_PIN_MAP_DRIVE_MODE_TDM_TDM_TX_SCK (CY_GPIO_DM_STRONG_IN_OFF)
	Indicates that a pin map exists for tdm_tdm_tx_sck.

#define	CYHAL_PIN_MAP_DRIVE_MODE_TDM_TDM_TX_SD (CY_GPIO_DM_STRONG_IN_OFF)
	Indicates that a pin map exists for tdm_tdm_tx_sd.

Typedefs
typedef cyhal_gpio_cyw20829_77_bga_t	cyhal_gpio_t
	Create generic name for the series/package specific type.

Enumerations
enum	cyhal_gpio_cyw20829_77_bga_t { NC = 0xFF , P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0) , P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1) , P0_2 = CYHAL_GET_GPIO(CYHAL_PORT_0, 2) , P0_3 = CYHAL_GET_GPIO(CYHAL_PORT_0, 3) , P0_4 = CYHAL_GET_GPIO(CYHAL_PORT_0, 4) , P0_5 = CYHAL_GET_GPIO(CYHAL_PORT_0, 5) , P1_0 = CYHAL_GET_GPIO(CYHAL_PORT_1, 0) , P1_1 = CYHAL_GET_GPIO(CYHAL_PORT_1, 1) , P1_2 = CYHAL_GET_GPIO(CYHAL_PORT_1, 2) , P1_3 = CYHAL_GET_GPIO(CYHAL_PORT_1, 3) , P1_4 = CYHAL_GET_GPIO(CYHAL_PORT_1, 4) , P1_5 = CYHAL_GET_GPIO(CYHAL_PORT_1, 5) , P1_6 = CYHAL_GET_GPIO(CYHAL_PORT_1, 6) , P2_0 = CYHAL_GET_GPIO(CYHAL_PORT_2, 0) , P2_1 = CYHAL_GET_GPIO(CYHAL_PORT_2, 1) , P2_2 = CYHAL_GET_GPIO(CYHAL_PORT_2, 2) , P2_3 = CYHAL_GET_GPIO(CYHAL_PORT_2, 3) , P2_4 = CYHAL_GET_GPIO(CYHAL_PORT_2, 4) , P2_5 = CYHAL_GET_GPIO(CYHAL_PORT_2, 5) , P3_0 = CYHAL_GET_GPIO(CYHAL_PORT_3, 0) , P3_1 = CYHAL_GET_GPIO(CYHAL_PORT_3, 1) , P3_2 = CYHAL_GET_GPIO(CYHAL_PORT_3, 2) , P3_3 = CYHAL_GET_GPIO(CYHAL_PORT_3, 3) , P3_4 = CYHAL_GET_GPIO(CYHAL_PORT_3, 4) , P3_5 = CYHAL_GET_GPIO(CYHAL_PORT_3, 5) , P3_6 = CYHAL_GET_GPIO(CYHAL_PORT_3, 6) , P3_7 = CYHAL_GET_GPIO(CYHAL_PORT_3, 7) , P4_0 = CYHAL_GET_GPIO(CYHAL_PORT_4, 0) , P4_1 = CYHAL_GET_GPIO(CYHAL_PORT_4, 1) , P5_0 = CYHAL_GET_GPIO(CYHAL_PORT_5, 0) , P5_1 = CYHAL_GET_GPIO(CYHAL_PORT_5, 1) , P5_2 = CYHAL_GET_GPIO(CYHAL_PORT_5, 2) }
	Definitions for all of the pins that are bonded out on in the 77-BGA package for the CYW20829 series. More...

Variables
const cyhal_resource_pin_mapping_t	cyhal_pin_map_adcmic_clk_pdm [2]
	List of valid pin to peripheral connections for the adcmic_clk_pdm signal.

const cyhal_resource_pin_mapping_t	cyhal_pin_map_adcmic_gpio_adc_in [8]
	List of valid pin to peripheral connections for the adcmic_gpio_adc_in signal.

const cyhal_resource_pin_mapping_t	cyhal_pin_map_adcmic_pdm_data [2]
	List of valid pin to peripheral connections for the adcmic_pdm_data signal.

const cyhal_resource_pin_mapping_t	cyhal_pin_map_canfd_ttcan_rx [2]
	List of valid pin to peripheral connections for the canfd_ttcan_rx signal.

const cyhal_resource_pin_mapping_t	cyhal_pin_map_canfd_ttcan_tx [2]
	List of valid pin to peripheral connections for the canfd_ttcan_tx signal.

const cyhal_resource_pin_mapping_t	cyhal_pin_map_cpuss_clk_swj_swclk_tclk [1]
	List of valid pin to peripheral connections for the cpuss_clk_swj_swclk_tclk signal.

const cyhal_resource_pin_mapping_t	cyhal_pin_map_cpuss_rst_swj_trstn [1]
	List of valid pin to peripheral connections for the cpuss_rst_swj_trstn signal.

const cyhal_resource_pin_mapping_t	cyhal_pin_map_cpuss_swj_swdio_tms [1]
	List of valid pin to peripheral connections for the cpuss_swj_swdio_tms signal.

const cyhal_resource_pin_mapping_t	cyhal_pin_map_cpuss_swj_swdoe_tdi [1]
	List of valid pin to peripheral connections for the cpuss_swj_swdoe_tdi signal.

const cyhal_resource_pin_mapping_t	cyhal_pin_map_cpuss_swj_swo_tdo [1]
	List of valid pin to peripheral connections for the cpuss_swj_swo_tdo signal.

const cyhal_resource_pin_mapping_t	cyhal_pin_map_cpuss_trace_clock [2]
	List of valid pin to peripheral connections for the cpuss_trace_clock signal.

const cyhal_resource_pin_mapping_t	cyhal_pin_map_cpuss_trace_data [8]
	List of valid pin to peripheral connections for the cpuss_trace_data signal.

const cyhal_resource_pin_mapping_t	cyhal_pin_map_keyscan_ks_col [20]
	List of valid pin to peripheral connections for the keyscan_ks_col signal.

const cyhal_resource_pin_mapping_t	cyhal_pin_map_keyscan_ks_row [8]
	List of valid pin to peripheral connections for the keyscan_ks_row signal.

const cyhal_resource_pin_mapping_t	cyhal_pin_map_lin_lin_en [2]
	List of valid pin to peripheral connections for the lin_lin_en signal.

const cyhal_resource_pin_mapping_t	cyhal_pin_map_lin_lin_rx [2]
	List of valid pin to peripheral connections for the lin_lin_rx signal.

const cyhal_resource_pin_mapping_t	cyhal_pin_map_lin_lin_tx [2]
	List of valid pin to peripheral connections for the lin_lin_tx signal.

const cyhal_resource_pin_mapping_t	cyhal_pin_map_pdm_pdm_clk [4]
	List of valid pin to peripheral connections for the pdm_pdm_clk signal.

const cyhal_resource_pin_mapping_t	cyhal_pin_map_pdm_pdm_data [4]
	List of valid pin to peripheral connections for the pdm_pdm_data signal.

const cyhal_resource_pin_mapping_t	cyhal_pin_map_peri_tr_io_input [8]
	List of valid pin to peripheral connections for the peri_tr_io_input signal.

const cyhal_resource_pin_mapping_t	cyhal_pin_map_peri_tr_io_output [2]
	List of valid pin to peripheral connections for the peri_tr_io_output signal.

const cyhal_resource_pin_mapping_t	cyhal_pin_map_scb_i2c_scl [5]
	List of valid pin to peripheral connections for the scb_i2c_scl signal.

const cyhal_resource_pin_mapping_t	cyhal_pin_map_scb_i2c_sda [5]
	List of valid pin to peripheral connections for the scb_i2c_sda signal.

const cyhal_resource_pin_mapping_t	cyhal_pin_map_scb_spi_m_clk [3]
	List of valid pin to peripheral connections for the scb_spi_m_clk signal.

const cyhal_resource_pin_mapping_t	cyhal_pin_map_scb_spi_m_miso [4]
	List of valid pin to peripheral connections for the scb_spi_m_miso signal.

const cyhal_resource_pin_mapping_t	cyhal_pin_map_scb_spi_m_mosi [4]
	List of valid pin to peripheral connections for the scb_spi_m_mosi signal.

const cyhal_resource_pin_mapping_t	cyhal_pin_map_scb_spi_m_select0 [4]
	List of valid pin to peripheral connections for the scb_spi_m_select0 signal.

const cyhal_resource_pin_mapping_t	cyhal_pin_map_scb_spi_m_select1 [3]
	List of valid pin to peripheral connections for the scb_spi_m_select1 signal.

const cyhal_resource_pin_mapping_t	cyhal_pin_map_scb_spi_m_select2 [3]
	List of valid pin to peripheral connections for the scb_spi_m_select2 signal.

const cyhal_resource_pin_mapping_t	cyhal_pin_map_scb_spi_m_select3 [2]
	List of valid pin to peripheral connections for the scb_spi_m_select3 signal.

const cyhal_resource_pin_mapping_t	cyhal_pin_map_scb_spi_s_clk [3]
	List of valid pin to peripheral connections for the scb_spi_s_clk signal.

const cyhal_resource_pin_mapping_t	cyhal_pin_map_scb_spi_s_miso [4]
	List of valid pin to peripheral connections for the scb_spi_s_miso signal.

const cyhal_resource_pin_mapping_t	cyhal_pin_map_scb_spi_s_mosi [4]
	List of valid pin to peripheral connections for the scb_spi_s_mosi signal.

const cyhal_resource_pin_mapping_t	cyhal_pin_map_scb_spi_s_select0 [4]
	List of valid pin to peripheral connections for the scb_spi_s_select0 signal.

const cyhal_resource_pin_mapping_t	cyhal_pin_map_scb_spi_s_select1 [3]
	List of valid pin to peripheral connections for the scb_spi_s_select1 signal.

const cyhal_resource_pin_mapping_t	cyhal_pin_map_scb_spi_s_select2 [3]
	List of valid pin to peripheral connections for the scb_spi_s_select2 signal.

const cyhal_resource_pin_mapping_t	cyhal_pin_map_scb_spi_s_select3 [2]
	List of valid pin to peripheral connections for the scb_spi_s_select3 signal.

const cyhal_resource_pin_mapping_t	cyhal_pin_map_scb_uart_cts [4]
	List of valid pin to peripheral connections for the scb_uart_cts signal.

const cyhal_resource_pin_mapping_t	cyhal_pin_map_scb_uart_rts [2]
	List of valid pin to peripheral connections for the scb_uart_rts signal.

const cyhal_resource_pin_mapping_t	cyhal_pin_map_scb_uart_rx [2]
	List of valid pin to peripheral connections for the scb_uart_rx signal.

const cyhal_resource_pin_mapping_t	cyhal_pin_map_scb_uart_tx [2]
	List of valid pin to peripheral connections for the scb_uart_tx signal.

const cyhal_resource_pin_mapping_t	cyhal_pin_map_smif_spi_clk [1]
	List of valid pin to peripheral connections for the smif_spi_clk signal.

const cyhal_resource_pin_mapping_t	cyhal_pin_map_smif_spi_data0 [1]
	List of valid pin to peripheral connections for the smif_spi_data0 signal.

const cyhal_resource_pin_mapping_t	cyhal_pin_map_smif_spi_data1 [1]
	List of valid pin to peripheral connections for the smif_spi_data1 signal.

const cyhal_resource_pin_mapping_t	cyhal_pin_map_smif_spi_data2 [1]
	List of valid pin to peripheral connections for the smif_spi_data2 signal.

const cyhal_resource_pin_mapping_t	cyhal_pin_map_smif_spi_data3 [1]
	List of valid pin to peripheral connections for the smif_spi_data3 signal.

const cyhal_resource_pin_mapping_t	cyhal_pin_map_smif_spi_select0 [1]
	List of valid pin to peripheral connections for the smif_spi_select0 signal.

const cyhal_resource_pin_mapping_t	cyhal_pin_map_smif_spi_select1 [1]
	List of valid pin to peripheral connections for the smif_spi_select1 signal.

const cyhal_resource_pin_mapping_t	cyhal_pin_map_tcpwm_line [26]
	List of valid pin to peripheral connections for the tcpwm_line signal.

const cyhal_resource_pin_mapping_t	cyhal_pin_map_tcpwm_line_compl [26]
	List of valid pin to peripheral connections for the tcpwm_line_compl signal.

const cyhal_resource_pin_mapping_t	cyhal_pin_map_tdm_tdm_rx_fsync [1]
	List of valid pin to peripheral connections for the tdm_tdm_rx_fsync signal.

const cyhal_resource_pin_mapping_t	cyhal_pin_map_tdm_tdm_rx_mck [1]
	List of valid pin to peripheral connections for the tdm_tdm_rx_mck signal.

const cyhal_resource_pin_mapping_t	cyhal_pin_map_tdm_tdm_rx_sck [1]
	List of valid pin to peripheral connections for the tdm_tdm_rx_sck signal.

const cyhal_resource_pin_mapping_t	cyhal_pin_map_tdm_tdm_rx_sd [1]
	List of valid pin to peripheral connections for the tdm_tdm_rx_sd signal.

const cyhal_resource_pin_mapping_t	cyhal_pin_map_tdm_tdm_tx_fsync [1]
	List of valid pin to peripheral connections for the tdm_tdm_tx_fsync signal.

const cyhal_resource_pin_mapping_t	cyhal_pin_map_tdm_tdm_tx_mck [1]
	List of valid pin to peripheral connections for the tdm_tdm_tx_mck signal.

const cyhal_resource_pin_mapping_t	cyhal_pin_map_tdm_tdm_tx_sck [1]
	List of valid pin to peripheral connections for the tdm_tdm_tx_sck signal.

const cyhal_resource_pin_mapping_t	cyhal_pin_map_tdm_tdm_tx_sd [1]
	List of valid pin to peripheral connections for the tdm_tdm_tx_sd signal.

Data Structure Documentation

◆ cyhal_resource_pin_mapping_t

struct cyhal_resource_pin_mapping_t

Data Fields
uint8_t	block_num	The block number of the resource with this connection.
uint8_t	channel_num	The channel number of the block with this connection.
cyhal_gpio_t	pin	The GPIO pin the connection is with.
en_hsiom_sel_t	hsiom	The HSIOM configuration value.

Enumeration Type Documentation

◆ cyhal_gpio_cyw20829_77_bga_t

enum cyhal_gpio_cyw20829_77_bga_t

Definitions for all of the pins that are bonded out on in the 77-BGA package for the CYW20829 series.

Enumerator
NC	No Connect/Invalid Pin.
P0_0	Port 0 Pin 0.
P0_1	Port 0 Pin 1.
P0_2	Port 0 Pin 2.
P0_3	Port 0 Pin 3.
P0_4	Port 0 Pin 4.
P0_5	Port 0 Pin 5.
P1_0	Port 1 Pin 0.
P1_1	Port 1 Pin 1.
P1_2	Port 1 Pin 2.
P1_3	Port 1 Pin 3.
P1_4	Port 1 Pin 4.
P1_5	Port 1 Pin 5.
P1_6	Port 1 Pin 6.
P2_0	Port 2 Pin 0.
P2_1	Port 2 Pin 1.
P2_2	Port 2 Pin 2.
P2_3	Port 2 Pin 3.
P2_4	Port 2 Pin 4.
P2_5	Port 2 Pin 5.
P3_0	Port 3 Pin 0.
P3_1	Port 3 Pin 1.
P3_2	Port 3 Pin 2.
P3_3	Port 3 Pin 3.
P3_4	Port 3 Pin 4.
P3_5	Port 3 Pin 5.
P3_6	Port 3 Pin 6.
P3_7	Port 3 Pin 7.
P4_0	Port 4 Pin 0.
P4_1	Port 4 Pin 1.
P5_0	Port 5 Pin 0.
P5_1	Port 5 Pin 1.
P5_2	Port 5 Pin 2.

General Description

Data Structures

Macros

Typedefs

Enumerations

Variables

Data Structure Documentation

◆ cyhal_resource_pin_mapping_t

Enumeration Type Documentation

◆ cyhal_gpio_cyw20829_77_bga_t