Hardware Abstraction Layer (HAL)
QSPI (Quad Serial Peripheral Interface)

General Description

High level interface for interacting with the Quad-SPI interface.

QSPI is an SPI-based communication interface, often used with external memory devices. The QSPI driver supports sending and receiving commands to/from from another device via a single, dual, quad, or octal SPI interface.

Features

Code Snippets

Note
The following snippets show commands specific to the S25FL512S Cypress NOR Flash device. Refer to the datasheet of the external memory device for device specific memory commands.

Code Snippet 1: Initializing the cyhal_qspi_command_t structure

The following code snip demonstrates an example for initializing the cyhal_qspi_command_t structure for any given flash command. The cyhal_qspi_command_t.mode_bits structure has several other components which should be set as per the command. Mode bits are not required for single SPI read command, hence, mode_bits.disabled is set to TRUE in the below example code.

// Commands
#define DEVICE_SPECIFIC_READ_COMMAND (0x03)
// Defining QSPI command structure for READ command
cyhal_qspi_command_t device_specific_read_command =
{
.instruction.bus_width = CYHAL_QSPI_CFG_BUS_SINGLE, // Bus width for the instruction
.instruction.data_rate = CYHAL_QSPI_DATARATE_SDR, // Data rate for instruction
// (SDR/DDR)
.instruction.two_byte_cmd = false, // command is 1-byte value
.instruction.value = DEVICE_SPECIFIC_READ_COMMAND, // Instruction value
.instruction.disabled = false, // Instruction phase skipped if
// disabled
// set to true
.address.bus_width = CYHAL_QSPI_CFG_BUS_SINGLE, // Bus width for the address
.address.data_rate = CYHAL_QSPI_DATARATE_SDR, // Data rate for address (SDR/DDR)
.address.size = CYHAL_QSPI_CFG_SIZE_24, // Address size in bits
.address.disabled = false, // Address phase skipped if disabled
// set to true
.mode_bits.disabled = true, // Mode bits phase skipped if
// disabled set to true
.dummy_cycles.dummy_count = 0, // Dummy cycles count
.data.bus_width = CYHAL_QSPI_CFG_BUS_SINGLE, // Bus width for data
.data.data_rate = CYHAL_QSPI_DATARATE_SDR, // Data rate for data (SDR/DDR)
};
struct cyhal_qspi_command_t::@0 instruction
Instruction structure.
@ CYHAL_QSPI_CFG_SIZE_24
24 bits address
Definition: cyhal_qspi.h:153
@ CYHAL_QSPI_DATARATE_SDR
Single data rate.
Definition: cyhal_qspi.h:168
@ CYHAL_QSPI_CFG_BUS_SINGLE
Normal SPI Mode.
Definition: cyhal_qspi.h:142
QSPI command settings.
Definition: cyhal_qspi.h:174

Code Snippet 2: QSPI initialization and Reading Flash memory

This example function demonstrates the initialization of the QSPI component and use of the cyhal_qspi_read() function to complete the read operation and receive the read data in a buffer.

cy_rslt_t result;
cyhal_qspi_t qspi_object;
uint8_t rx_buf[PACKET_SIZE];
size_t length = PACKET_SIZE;
{
// Memory data lines
.io = { CYBSP_QSPI_D0, CYBSP_QSPI_D1, CYBSP_QSPI_D2, CYBSP_QSPI_D3, NC, NC, NC, NC },
// Memory slave select signal
.ssel = CYBSP_QSPI_SS_0
};
// Initialize QSPI peripheral with appropriate GPIOs
result = cyhal_qspi_init(&qspi_object, CYBSP_QSPI_SCK, &memory_pin_set, QSPI_BUS_FREQUENCY_HZ,
0, NULL);
// HAL API for read operation
result = cyhal_qspi_read(&qspi_object, &device_specific_read_command, ADDRESS, rx_buf, &length);
QSPI object.
Definition: cyhal_hw_types.h:1037
@ NC
No Connect/Invalid Pin.
Definition: cyhal_psoc6_01_104_m_csp_ble.h:53
cyhal_gpio_t io[8]
IOx lines of connected memory.
Definition: cyhal_qspi.h:218
cy_rslt_t cyhal_qspi_init(cyhal_qspi_t *obj, cyhal_gpio_t sclk, const cyhal_qspi_slave_pin_config_t *pin_set, uint32_t hz, uint8_t mode, cyhal_clock_t *clk)
Initialize QSPI peripheral.
cy_rslt_t cyhal_qspi_read(cyhal_qspi_t *obj, const cyhal_qspi_command_t *command, uint32_t address, void *data, size_t *length)
Receive a command and block of data, synchronously.
QSPI slave pin set.
Definition: cyhal_qspi.h:217
uint32_t cy_rslt_t
Provides the result of an operation as a structured bitfield.
Definition: cy_result.h:426

Code Snippet 3: Erasing Flash memory

The following code snippet demonstrates the use of cyhal_qspi_transfer() API for sending single byte instruction that may or may not need any address or data bytes. It also shows the usage of status register read command within a while loop to poll the WIP bit status.

cy_rslt_t result;
cyhal_qspi_t qspi_object;
uint8_t rx_buf[PACKET_SIZE];
uint8_t wip = 0x01;
size_t length = 1;
// HAL API for TX-RX transaction used for sending WREN command
result = cyhal_qspi_transfer(&qspi_object, &device_specific_wren_command, ADDRESS, NULL, 0,
NULL, 0);
// HAL API for TX-RX transaction used for sending SE command
result = cyhal_qspi_transfer(&qspi_object, &device_specific_se_command, ADDRESS, NULL, 0,
NULL, 0);
while (wip)
{
// Wait until the Erase operation is completed
cyhal_qspi_read(&qspi_object, &device_specific_rdsr1_command, ADDRESS, rx_buf, &length);
wip = rx_buf[0] & 0x01;
}
cy_rslt_t cyhal_qspi_transfer(cyhal_qspi_t *obj, const cyhal_qspi_command_t *command, uint32_t address, const void *tx_data, size_t tx_size, void *rx_data, size_t rx_size)
Send a command (and optionally data) and get the response.
Note
Flash memories need erase operation before programming.

Code Snippet 4: Programming Flash memory

This code snippet demonstrates the usage cyhal_qspi_write() API for executing program operation on flash memory.

cy_rslt_t result;
cyhal_qspi_t qspi_object;
uint8_t tx_buf[PACKET_SIZE];
uint8_t rx_buf[PACKET_SIZE];
size_t length = PACKET_SIZE;
uint8_t wip = 0x01;
// Initialization of tx_buffer
for (int i = 0; i < PACKET_SIZE; i++)
{
tx_buf[i] = i;
}
// HAL API for TX-RX transaction used for sending WREN command
result = cyhal_qspi_transfer(&qspi_object, &device_specific_wren_command, ADDRESS, NULL, 0,
NULL, 0);
// HAL API for write operation
result = cyhal_qspi_write(&qspi_object, &device_specific_pp_command, ADDRESS, tx_buf, &length);
while (wip)
{
// Wait until the Write operation is completed
cyhal_qspi_read(&qspi_object, &device_specific_rdsr1_command, ADDRESS, rx_buf, &length);
wip = rx_buf[0] & 0x01;
}
cy_rslt_t cyhal_qspi_write(cyhal_qspi_t *obj, const cyhal_qspi_command_t *command, uint32_t address, const void *data, size_t *length)
Send a command and block of data, synchronously.

Code Snippet 5: Configuring multiple memories

This code snippet demonstrates the usage cyhal_qspi_slave_configure() and cyhal_qspi_select_active_ssel() API for for initialization environment for additional (additional to one, that was initialized in scope of cyhal_qspi_init()) QSPI memory and switching between memories.

cy_rslt_t result;
cyhal_qspi_t qspi_object;
cyhal_qspi_slave_pin_config_t memory_0_pin_set =
{
// Memory data lines (IO0, IO1)
.io = { CYBSP_QSPI_D0, CYBSP_QSPI_D1, NC, NC, NC, NC, NC, NC },
// Memory slave select signal
.ssel = CYBSP_QSPI_SS_0
};
// Initialize QSPI peripheral with appropriate GPIOs
result = cyhal_qspi_init(&qspi_object, CYBSP_QSPI_SCK, &memory_0_pin_set, QSPI_BUS_FREQUENCY_HZ,
0, NULL);
// Perform needed transfers with memory #0
cyhal_qspi_slave_pin_config_t memory_1_pin_set =
{
// Memory data lines (IO2, IO3)
.io = { CYBSP_QSPI_D2, CYBSP_QSPI_D3, NC, NC, NC, NC, NC, NC },
// Memory slave select signal
.ssel = CYBSP_QSPI_SS_1
};
// Configure pins for memory #1
result = cyhal_qspi_slave_configure(&qspi_object, &memory_1_pin_set);
// Make memory #1 slave select active
result = cyhal_qspi_select_active_ssel(&qspi_object, memory_1_pin_set.ssel);
// Perform needed transfers with memory #1
// Make memory #0 slave select active again
result = cyhal_qspi_select_active_ssel(&qspi_object, memory_0_pin_set.ssel);
cyhal_gpio_t ssel
Slave Select line of connected memory.
Definition: cyhal_qspi.h:219
cy_rslt_t cyhal_qspi_select_active_ssel(cyhal_qspi_t *obj, cyhal_gpio_t ssel)
Selects an active slave select (SSEL) line from one of available and previously configured.
cy_rslt_t cyhal_qspi_slave_configure(cyhal_qspi_t *obj, const cyhal_qspi_slave_pin_config_t *pin_set)
Configure provided set of pins to service additional slave memory.

API Reference

 QSPI HAL Results
 QSPI specific return codes.
 

Data Structures

struct  cyhal_qspi_command_t
 QSPI command settings. More...
 
struct  cyhal_qspi_slave_pin_config_t
 QSPI slave pin set. More...
 
struct  cyhal_qspi_command_t.instruction
 
struct  cyhal_qspi_command_t.address
 
struct  cyhal_qspi_command_t.mode_bits
 
struct  cyhal_qspi_command_t.dummy_cycles
 
struct  cyhal_qspi_command_t.data
 

Typedefs

typedef void(* cyhal_qspi_event_callback_t) (void *callback_arg, cyhal_qspi_event_t event)
 Handler for QSPI callbacks.
 

Enumerations

enum  cyhal_qspi_bus_width_t {
  CYHAL_QSPI_CFG_BUS_SINGLE = 1 ,
  CYHAL_QSPI_CFG_BUS_DUAL = 2 ,
  CYHAL_QSPI_CFG_BUS_QUAD = 4 ,
  CYHAL_QSPI_CFG_BUS_OCTAL = 8
}
 QSPI Bus width. More...
 
enum  cyhal_qspi_size_t {
  CYHAL_QSPI_CFG_SIZE_8 = 8 ,
  CYHAL_QSPI_CFG_SIZE_16 = 16 ,
  CYHAL_QSPI_CFG_SIZE_24 = 24 ,
  CYHAL_QSPI_CFG_SIZE_32 = 32
}
 Address size in bits. More...
 
enum  cyhal_qspi_event_t {
  CYHAL_QSPI_EVENT_NONE = 0 ,
  CYHAL_QSPI_IRQ_TRANSMIT_DONE = 1 << 0 ,
  CYHAL_QSPI_IRQ_RECEIVE_DONE = 1 << 1
}
 QSPI interrupt triggers. More...
 
enum  cyhal_qspi_datarate_t {
  CYHAL_QSPI_DATARATE_SDR = 0 ,
  CYHAL_QSPI_DATARATE_DDR = 1
}
 QSPI data rate. More...
 

Functions

cy_rslt_t cyhal_qspi_init (cyhal_qspi_t *obj, cyhal_gpio_t sclk, const cyhal_qspi_slave_pin_config_t *pin_set, uint32_t hz, uint8_t mode, cyhal_clock_t *clk)
 Initialize QSPI peripheral. More...
 
cy_rslt_t cyhal_qspi_init_cfg (cyhal_qspi_t *obj, const cyhal_qspi_configurator_t *cfg)
 Initialize the QSPI peripheral using a configurator generated configuration struct. More...
 
void cyhal_qspi_free (cyhal_qspi_t *obj)
 Deinitilize QSPI peripheral. More...
 
cy_rslt_t cyhal_qspi_set_frequency (cyhal_qspi_t *obj, uint32_t hz)
 Set the QSPI baud rate. More...
 
uint32_t cyhal_qspi_get_frequency (cyhal_qspi_t *obj)
 Get the actual frequency that QSPI is configured for. More...
 
cy_rslt_t cyhal_qspi_slave_configure (cyhal_qspi_t *obj, const cyhal_qspi_slave_pin_config_t *pin_set)
 Configure provided set of pins to service additional slave memory. More...
 
cy_rslt_t cyhal_qspi_select_active_ssel (cyhal_qspi_t *obj, cyhal_gpio_t ssel)
 Selects an active slave select (SSEL) line from one of available and previously configured. More...
 
cy_rslt_t cyhal_qspi_read (cyhal_qspi_t *obj, const cyhal_qspi_command_t *command, uint32_t address, void *data, size_t *length)
 Receive a command and block of data, synchronously. More...
 
cy_rslt_t cyhal_qspi_read_async (cyhal_qspi_t *obj, const cyhal_qspi_command_t *command, uint32_t address, void *data, size_t *length)
 Receive a command and block of data in asynchronous mode. More...
 
cy_rslt_t cyhal_qspi_write (cyhal_qspi_t *obj, const cyhal_qspi_command_t *command, uint32_t address, const void *data, size_t *length)
 Send a command and block of data, synchronously. More...
 
cy_rslt_t cyhal_qspi_write_async (cyhal_qspi_t *obj, const cyhal_qspi_command_t *command, uint32_t address, const void *data, size_t *length)
 Send a command and block of data in asynchronous mode. More...
 
cy_rslt_t cyhal_qspi_transfer (cyhal_qspi_t *obj, const cyhal_qspi_command_t *command, uint32_t address, const void *tx_data, size_t tx_size, void *rx_data, size_t rx_size)
 Send a command (and optionally data) and get the response. More...
 
void cyhal_qspi_register_callback (cyhal_qspi_t *obj, cyhal_qspi_event_callback_t callback, void *callback_arg)
 Register a QSPI event handler. More...
 
void cyhal_qspi_enable_event (cyhal_qspi_t *obj, cyhal_qspi_event_t event, uint8_t intr_priority, bool enable)
 Configure QSPI interrupt enablement. More...
 

Data Structure Documentation

◆ cyhal_qspi_command_t

struct cyhal_qspi_command_t
Data Fields
struct cyhal_qspi_command_t.instruction instruction Instruction structure.
struct cyhal_qspi_command_t.address address Address structure.
struct cyhal_qspi_command_t.mode_bits mode_bits Mode bits structure.
struct cyhal_qspi_command_t.dummy_cycles dummy_cycles Dummy cycles structure.
struct cyhal_qspi_command_t.data data Data structure.

◆ cyhal_qspi_slave_pin_config_t

struct cyhal_qspi_slave_pin_config_t
Data Fields
cyhal_gpio_t io[8] IOx lines of connected memory.
cyhal_gpio_t ssel Slave Select line of connected memory.

◆ cyhal_qspi_command_t.instruction

struct cyhal_qspi_command_t.instruction
Data Fields
cyhal_qspi_bus_width_t bus_width Bus width for the instruction.
cyhal_qspi_datarate_t data_rate Data rate SDR/DDR.
bool two_byte_cmd Defines whether cmd is 2-byte value, or 1-byte (if false)
uint16_t value Instruction value.
bool disabled Instruction phase skipped if disabled is set to true.

◆ cyhal_qspi_command_t.address

struct cyhal_qspi_command_t.address
Data Fields
cyhal_qspi_bus_width_t bus_width Bus width for the address.
cyhal_qspi_datarate_t data_rate Data rate SDR/DDR.
cyhal_qspi_size_t size Address size.
bool disabled Address phase skipped if disabled is set to true.

◆ cyhal_qspi_command_t.mode_bits

struct cyhal_qspi_command_t.mode_bits
Data Fields
cyhal_qspi_bus_width_t bus_width Bus width for mode bits
cyhal_qspi_datarate_t data_rate Data rate SDR/DDR.
cyhal_qspi_size_t size Mode bits size.
uint32_t value Mode bits value.
bool disabled Mode bits phase skipped if disabled is set to true.

◆ cyhal_qspi_command_t.dummy_cycles

struct cyhal_qspi_command_t.dummy_cycles
Data Fields
cyhal_qspi_bus_width_t bus_width Bus width for mode bits
cyhal_qspi_datarate_t data_rate Data rate SDR/DDR.
uint32_t dummy_count Dummy cycles count.

◆ cyhal_qspi_command_t.data

struct cyhal_qspi_command_t.data
Data Fields
cyhal_qspi_bus_width_t bus_width Bus width for data.
cyhal_qspi_datarate_t data_rate Data rate SDR/DDR.

Enumeration Type Documentation

◆ cyhal_qspi_bus_width_t

QSPI Bus width.

Some parts of commands provide variable bus width.

Enumerator
CYHAL_QSPI_CFG_BUS_SINGLE 

Normal SPI Mode.

CYHAL_QSPI_CFG_BUS_DUAL 

Dual SPI Mode.

CYHAL_QSPI_CFG_BUS_QUAD 

Quad SPI Mode.

CYHAL_QSPI_CFG_BUS_OCTAL 

Octal SPI Mode.

◆ cyhal_qspi_size_t

Address size in bits.

Enumerator
CYHAL_QSPI_CFG_SIZE_8 

8 bits address

CYHAL_QSPI_CFG_SIZE_16 

16 bits address

CYHAL_QSPI_CFG_SIZE_24 

24 bits address

CYHAL_QSPI_CFG_SIZE_32 

32 bits address

◆ cyhal_qspi_event_t

QSPI interrupt triggers.

Enumerator
CYHAL_QSPI_EVENT_NONE 

No event.

CYHAL_QSPI_IRQ_TRANSMIT_DONE 

Async transmit done.

CYHAL_QSPI_IRQ_RECEIVE_DONE 

Async receive done.

◆ cyhal_qspi_datarate_t

QSPI data rate.

Enumerator
CYHAL_QSPI_DATARATE_SDR 

Single data rate.

CYHAL_QSPI_DATARATE_DDR 

Double data rate.

Function Documentation

◆ cyhal_qspi_init()

cy_rslt_t cyhal_qspi_init ( cyhal_qspi_t obj,
cyhal_gpio_t  sclk,
const cyhal_qspi_slave_pin_config_t pin_set,
uint32_t  hz,
uint8_t  mode,
cyhal_clock_t clk 
)

Initialize QSPI peripheral.

It should initialize QSPI pins (io0-io7, sclk and ssel), set frequency, clock polarity and phase mode. The clock for the peripheral should be enabled

Parameters
[out]objPointer to a QSPI object. The caller must allocate the memory for this object but the init function will initialize its contents.
[in]sclkThe clock pin
[in]pin_setSet of pins, that will primarily be used for communication with memory. Depends on device, QSPI HAL can service multiple memories which can be registered and controlled using cyhal_qspi_slave_configure and cyhal_qspi_select_active_ssel functions. There is no need to call cyhal_qspi_select_active_ssel after this function - provided ssel pin as part of pin_set parameter become active.
[in]hzThe bus frequency
[in]modeClock polarity and phase mode (0 - 3)
[in]clkThe clock to use can be shared, if not provided a new clock will be allocated
Note
QSPI HAL cannot make changes into provided clock configuration. In this case cyhal_qspi_set_frequency function cannot be used and will return error once called. With provided clock only user application can configure QSPI bus frequency by configuring parameters of shared clock.
Returns
The status of the init request

◆ cyhal_qspi_init_cfg()

cy_rslt_t cyhal_qspi_init_cfg ( cyhal_qspi_t obj,
const cyhal_qspi_configurator_t cfg 
)

Initialize the QSPI peripheral using a configurator generated configuration struct.

This function may not support all features, that can be configured via configurator. For limitations list please refer to Configurator-generated features limitations section.

Parameters
[in]objThe QSPI peripheral to configure
[in]cfgConfiguration structure generated by a configurator.
Returns
The status of the operation

◆ cyhal_qspi_free()

void cyhal_qspi_free ( cyhal_qspi_t obj)

Deinitilize QSPI peripheral.

It should release pins that are associated with the QSPI object, and disable clocks for QSPI peripheral module that was associated with the object

Parameters
[in,out]objQSPI object

◆ cyhal_qspi_set_frequency()

cy_rslt_t cyhal_qspi_set_frequency ( cyhal_qspi_t obj,
uint32_t  hz 
)

Set the QSPI baud rate.

Actual frequency may differ from the desired frequency due to available dividers and the bus clock. Function will apply achieved frequency only if it is in +0% /-10% deviation bounds from desired. Use cyhal_qspi_get_frequency function to get actual frequency value that was achieved and set.

Parameters
[in]objThe QSPI object to configure
[in]hzThe baud rate in Hz
Returns
The status of the set_frequency request

◆ cyhal_qspi_get_frequency()

uint32_t cyhal_qspi_get_frequency ( cyhal_qspi_t obj)

Get the actual frequency that QSPI is configured for.

Parameters
[in]objThe QSPI object
Returns
Frequency in Hz

◆ cyhal_qspi_slave_configure()

cy_rslt_t cyhal_qspi_slave_configure ( cyhal_qspi_t obj,
const cyhal_qspi_slave_pin_config_t pin_set 
)

Configure provided set of pins to service additional slave memory.

Multiple pins can be configured as QSPI slave select pins as well as IO pins may be (or may not be) shared and used to service multiple connected slave memories. This function can be called multiple times - each call for each additional slave memory. Please refer to device datasheet for details. Switching between configured slave select pins is done by cyhal_qspi_select_active_ssel function. Unless modified with this function, the SSEL pin provided as part of cyhal_qspi_init is the default. Please refer to Code Snippet 5: Configuring multiple memories for example of configuration multiple memory devices and switching between them.

Note
Provided IO pins can overlap with those, that are configured in scope of cyhal_qspi_init function.
Parameters
[in]objThe QSPI object to configure
[in]pin_setSet of pins, that will be used to service additional slave memory.
Returns
The status of pin configuration

◆ cyhal_qspi_select_active_ssel()

cy_rslt_t cyhal_qspi_select_active_ssel ( cyhal_qspi_t obj,
cyhal_gpio_t  ssel 
)

Selects an active slave select (SSEL) line from one of available and previously configured.

Slave memories (in addition to one, that was configured in scope of cyhal_qspi_init) can be added with help of cyhal_qspi_slave_configure function.

Parameters
[in]objThe QSPI object to configure
[in]sselSSEL pin to be set as active
Returns
CY_RSLT_SUCCESS if slave select was switched successfully, otherwise - CYHAL_QSPI_RSLT_ERR_CANNOT_SWITCH_SSEL

◆ cyhal_qspi_read()

cy_rslt_t cyhal_qspi_read ( cyhal_qspi_t obj,
const cyhal_qspi_command_t command,
uint32_t  address,
void *  data,
size_t *  length 
)

Receive a command and block of data, synchronously.

This will read either length bytes or the number of bytes that are currently available in the receive buffer, whichever is less, then return. The value pointed to by length will be updated to reflect the number of bytes that were actually read.

Parameters
[in]objQSPI object
[in]commandQSPI command
[in]addressAddress to access to
[out]dataRX buffer
[in]lengthRX buffer length in bytes
Returns
The status of the read request

◆ cyhal_qspi_read_async()

cy_rslt_t cyhal_qspi_read_async ( cyhal_qspi_t obj,
const cyhal_qspi_command_t command,
uint32_t  address,
void *  data,
size_t *  length 
)

Receive a command and block of data in asynchronous mode.

This will transfer length bytes into the buffer pointed to by data in the background. When the requested quantity of data has been read, the CYHAL_QSPI_IRQ_RECEIVE_DONE event will be raised. See cyhal_qspi_register_callback and cyhal_qspi_enable_event.

Parameters
[in]objQSPI object
[in]commandQSPI command
[in]addressAddress to access to
[out]dataRX buffer
[in]lengthRX buffer length in bytes
Returns
The status of the read request

◆ cyhal_qspi_write()

cy_rslt_t cyhal_qspi_write ( cyhal_qspi_t obj,
const cyhal_qspi_command_t command,
uint32_t  address,
const void *  data,
size_t *  length 
)

Send a command and block of data, synchronously.

This will write either length bytes or until the write buffer is full, whichever is less, then return. The value pointed to by length will be updated to reflect the number of bytes that were actually written.

Parameters
[in]objQSPI object
[in]commandQSPI command
[in]addressAddress to access to
[in]dataTX buffer
[in]lengthTX buffer length in bytes
Returns
The status of the write request

◆ cyhal_qspi_write_async()

cy_rslt_t cyhal_qspi_write_async ( cyhal_qspi_t obj,
const cyhal_qspi_command_t command,
uint32_t  address,
const void *  data,
size_t *  length 
)

Send a command and block of data in asynchronous mode.

This will transfer length bytes into the tx buffer in the background. When the requested quantity of data has been queued in the transmit buffer, the CYHAL_QSPI_IRQ_TRANSMIT_DONE event will be raised. See cyhal_qspi_register_callback and cyhal_qspi_enable_event.

Parameters
[in]objQSPI object
[in]commandQSPI command
[in]addressAddress to access to
[in]dataTX buffer
[in]lengthTX buffer length in bytes
Returns
The status of the write request

◆ cyhal_qspi_transfer()

cy_rslt_t cyhal_qspi_transfer ( cyhal_qspi_t obj,
const cyhal_qspi_command_t command,
uint32_t  address,
const void *  tx_data,
size_t  tx_size,
void *  rx_data,
size_t  rx_size 
)

Send a command (and optionally data) and get the response.

Can be used to send/receive device specific commands

Parameters
[in]objQSPI object
[in]commandQSPI command
[in]addressAddress to access to
[in]tx_dataTX buffer
[in]tx_sizeTX buffer length in bytes
[out]rx_dataRX buffer
[in]rx_sizeRX buffer length in bytes
Returns
The status of the transfer request

◆ cyhal_qspi_register_callback()

void cyhal_qspi_register_callback ( cyhal_qspi_t obj,
cyhal_qspi_event_callback_t  callback,
void *  callback_arg 
)

Register a QSPI event handler.

This function will be called when one of the events enabled by cyhal_qspi_enable_event occurs.

Parameters
[in]objThe QSPI object
[in]callbackThe callback handler which will be invoked when the interrupt fires
[in]callback_argGeneric argument that will be provided to the handler when called

◆ cyhal_qspi_enable_event()

void cyhal_qspi_enable_event ( cyhal_qspi_t obj,
cyhal_qspi_event_t  event,
uint8_t  intr_priority,
bool  enable 
)

Configure QSPI interrupt enablement.

When an enabled event occurs, the function specified by cyhal_qspi_register_callback will be called.

Parameters
[in]objThe QSPI object
[in]eventThe QSPI event type
[in]intr_priorityThe priority for NVIC interrupt events
[in]enableTrue to turn on interrupts, False to turn off