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ModusToolbox Safety Test Library
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ModusToolbox Safety Test Library
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| ADC Configuration Test (ADC Configuration Protection STL module) | This module provides APIs to capture and verify CRC-protected snapshots of SAR ADC and shared PASS-level configuration registers |
| Analog (Analog STL module) | This module carries out 4 tests: 1) SAR ADC 2) OPAMP 3) LPCOMP 4) DAC |
| APSR (APSR register STL module) | The APSR (Application Program Status Register) test detects stuck-at faults in the APSR bits that are implemented and writable on the core: the condition flags N, Z, C, and V, and, where the core has them, the sticky saturation flag Q and the greater-than-or-equal flags GE[3:0] |
| ATOP ADC Core (ATOP ADC Core STL module) | The ATOP ADC Core self-test validates the 12-bit SAR ADC by performing a conversion of a known internal reference voltage and comparing the result against an expected value: the input is connected to a reference whose nominal value is known, sampled through the converter datapath, and the read-back code is verified to lie within a specified tolerance of the expected code |
| ATOP ADC Filter (ATOP ADC digital filter STL module) | The ATOP ADC Filter self-test validates the digital filter chain that post-processes the ADC converted-data stream: the Median filter, the Linear Interpolation filter (LINTP), the Low-Pass filter (LP), the 3rd-order Comb filter (CIC3), the configurable Average filter (AVG) and the MIN/MAX detection logic |
| ATOP AFE (ATOP AFE STL module) | PPCA ATOP AFE (Analog Front End) programmable-gain verification self-test |
| ATOP DAC (ATOP DAC STL module) | PPCA ATOP DAC R2R internal loopback self-test |
| ATOP DCMP (ATOP Digital Comparator STL module) | PPCA ATOP DCMP self-test |
| ATOP DCSG (ATOP DCSG STL module) | ATOP DCSG (Digital Comparator and Slope Generator) self-test for PPCA block |
| CAN (CAN STL module) | The CAN block is tested using the internal loopback capability |
| CAN-FD (CAN-FD STL module) | The CAN-FD block is tested using the internal loopback capability |
| CLB (CLB STL module) | The CLB (Custom Logic Block) self-test validates the DICO (Digital Current Observer) sub-block and the MACO (Matrix Commutation) sub-block of the PPCA subsystem |
| Clock (Clock STL module) | The clock test implements independent time-slot monitoring and verifies the reliability of the internal main oscillator (IMO) system clock, specifically, that the system clock is neither too fast nor too slow within the tolerance of the internal low-speed oscillator (ILO) |
| CONTROL (CONTROL register STL module) | The CONTROL register test detects stuck-at faults in the CONTROL register bits that are implemented and writable on the core |
| CORDIC (CORDIC STL module) | To meet Class B requirement, Cordic must be tested for sine and cosine trignometric functions: |
| CPU (CPU STL module) | CPU Module does 3 tests: 1) CPU register Test 2) Program Counter Test 3) Program Flow Test |
| CPU instructions (CPU Instructions STL module) | The CPU instruction self-test verifies correct operation of core CPU/ALU instructions, such as arithmetic, logic, shift, and bit manipulation instructions |
| CRC (CRC STL module) | The CRC test implements the CRC16 implementation according to CCITT standards |
| DMA (DMA STL module) | The DMA test performs test on DMA block using DW transfers |
| DMAC (DMAC STL module) | The DMAC test performs tests on Direct Memory Access Controller using a fixed size of DMAC transfer |
| ECC (ECC STL module) | ECC hardware can correct single-bit (correctable) memory errors and report double-bit (non-correctable) memory errors through SysFault |
| eFuse Test (eFuse STL module) | Provides a read-only CRC32 check for safety-relevant bits in the eFuse customer region on XMC7000 devices |
| EPU (EPU STL module) | The EPU (Event Processing Unit) self-test validates that the processing unit signal path within the PPCA subsystem is functional |
| Flash (Flash STL module) | To complete a full diagnostic of the Flash memory, a checksum of all used Flash needs to be calculated |
| FPU (FPU STL module) | The FPU registers test detects stuck-at faults in the FPU by using the checkerboard test |
| HWFILT3P3Z (HW3P3Z filter STL module) | The HWFILT3P3Z (Hardware 3-Pole / 3-Zero Filter) self-test validates a single HW3P3Z filter channel by verifying its low-pass frequency response |
| INTR (INTR STL module) | To meet the Class B requirement, check the interrupt for “incorrect frequency” |
| GPIO (GPIO STL module) | Digital I/Os are arranged into ports with up-to-eight pins per port |
| IPC (IPC STL module) | This module performs a check on each free IPC channel with all free IPC interrupts |
| PPCA IPC (PPCA IPC STL module) | This module tests the PPCA IPC block on PSOC Control C3 M8 in loopback mode from the Main CM33 |
| MOTIF (MOTIF STL module) | The MOTIF self test implements the Quadrature Decoder mode and validates the functionality |
| MPU (ARM core MPU STL module) | Functional self-test for the ARM Cortex-M core MPU (CMSIS MPU->RBAR/RASR, ARM_MPU_*) |
| PPU (Peripheral Protection Unit STL module) | Functional self-test for the Peripheral Protection Unit (PPU) of the PERI_MS block (CAT1C / XMC7000) |
| PRIMASK (PRIMASK register STL module) | The PRIMASK register test detects stuck-at faults in the PM bit (bit 0) of the PRIMASK register, which masks all exceptions with configurable priority |
| PWM (PWM STL module) | This module performs PWM test and verifies that the duty cycle set is actually achieved in the output |
| PWM GateKill (PWM GateKill STL module) | The Gate Kill function is used in motor controllers and multi-level power converters |
| RAM (RAM STL module) | To meet the Class B requirement, SRAM test must be checked for DC fault |
| Startup Register (Startup Register STL module) | This test describes and shows an example of how to check the startup configuration registers: 1) Test digital clock configuration registers 2) Test analog configuration registers (set to default values after startup) 3) Test the GPIO configuration and HSIOM registers |
| I2C (I2C STL module) | This test requires connecting the I2C Master and Slave externally |
| SPI (SPI STL module) | This test implements the SPI internal data loopback test |
| UART (UART STL module) | This test implements the UART internal data loopback test |
| UART Data Transfer (UART Data Transfer STL module) | The UART SCB Components are used to physically generate signals |
| STL return status codes | Return status codes used by the mtb-stl self-test APIs |
| SMPU (CPUSS shared memory protection STL module) | Functional self-test for the CPUSS SMPU (shared memory protection unit) programmed through the PDL Cy_Prot_*SmpuSlaveStruct() API |
| Stack (Stack STL module) | This Module checks for the stack overflow or underflow condition |
| Timer/Counter (Timer/Counter STL module) | This test uses the timer function to ensure that the counter is incrementing correctly |
| WDT (WDT STL module) | This function implements the watchdog functional test |
| WWDT (WWDT STL module) | Windowed WDTs allow adjusting the watchdog timeout period to provide more flexibility for the different processor timing requirements |