Macros

General Description

API Reference
	CSV Clock Supervisor
	Functional self-test for the CLK_HF CSV (Clock Supervisor) comparators.
	Functions

Data Structures
struct	stl_clock_csv_entry_t
	CSV self-test entry. More...

Macros
#define	STL_CLOCK_SOURCE_HFCLOCK   (3u)
	High-frequency clock source selection used by the Clock self-test timer on PSOC Control C3 devices.
#define	CLOCK_TICKS_LO   (20u)
	Lower possible clock count for WDT depending on the accuracy of oscillator.
#define	CLOCK_TICKS_HI   (80u)
	Higher possible clock count for WDT depending on the accuracy of oscillator.
#define	CLOCK_TEST_TIME   (1000u)
	Clock self-test interval in microseconds.
#define	CLOCK_TEST_TIME_TIMER_PERIOD    (((CY_CFG_SYSCLK_IMO_FREQ_HZ/(1000000uL)) * (CLOCK_TEST_TIME)) / CLOCK_TEST_TIMER_CLK_DIV)
	Number of timer/source-clock cycles corresponding to CLOCK_TEST_TIME.

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Data Structure Documentation

stl_clock_csv_entry_t

struct stl_clock_csv_entry_t

Data Fields
uint32_t	clkHf	CLK_HF index (1..N; CLK_HF0 unsupported since it requires RESET fault action).
cy_en_clkhf_csv_ref_clk_t	refClk	CSV reference clock. Written by the test to SRSS_CSV_REF_SEL, which is shared by all CLK_HF CSVs.
FAULT_STRUCT_Type *	faultStruct	App's fault structure receiving CY_SYSFAULT_SRSS_CSV.
IRQn_Type	nvicMux	NvicMuxN_IRQn the app routed the fault-struct interrupt to.

Macro Definition Documentation

CLOCK_TICKS_LO

#define CLOCK_TICKS_LO   (20u)

Lower possible clock count for WDT depending on the accuracy of oscillator.

• PSOC 4 devices: 20u, calculated for PSOC 4100S Max with ILO = 40 kHz: 40 * (1 - 50%) = 20
• PSOC 61 Programmable Line, PSOC 62 Performance Line, PSOC Control C3, and XMC7000 devices: 31u, calculated with WCO = 32 kHz: 32 * (1 - 0.015%) = 31
• XMC5000 devices: 30u, calculated with WCO = 32.77 kHz: 32.77 * (1 - 7%) = 30

CLOCK_TICKS_HI

#define CLOCK_TICKS_HI   (80u)

Higher possible clock count for WDT depending on the accuracy of oscillator.

• PSOC 4 devices: 80u, calculated for PSOC 4100S Max with ILO = 40 kHz: 40 * (1 + 100%) = 80
• PSOC 61 Programmable Line, PSOC 62 Performance Line, PSOC Control C3, and XMC7000 devices: 33u, calculated with WCO = 32 kHz: 32 * (1 + 0.015%) = 33
• XMC5000 devices: 36u, calculated with WCO = 32.77 kHz: 32.77 * (1 + 7%) = 36

CLOCK_TEST_TIME_TIMER_PERIOD

#define CLOCK_TEST_TIME_TIMER_PERIOD    (((CY_CFG_SYSCLK_IMO_FREQ_HZ/(1000000uL)) * (CLOCK_TEST_TIME)) / CLOCK_TEST_TIMER_CLK_DIV)

Number of timer/source-clock cycles corresponding to CLOCK_TEST_TIME.

This macro is used on PSOC 4 devices. PSOC 61 Programmable Line, PSOC 62 Performance Line, PSOC Control C3, XMC7000, and XMC5000 devices calculate the equivalent period at runtime from the peripheral or high-frequency clock and its divider.