General Description

Functions
uint8_t	SelfTest_DMA_DW (DW_Type base, uint32_t channel, cy_stc_dma_descriptor_t descriptor0, cy_stc_dma_descriptor_t descriptor1, const cy_stc_dma_descriptor_config_t des0_config, const cy_stc_dma_descriptor_config_t des1_config, cy_stc_dma_channel_config_t const channelConfig, uint32_t trigLine)
	This function writes a pattern (66 bytes) to the destination using the DMA, and the destination block is verified to contain the correct pattern.

Function Documentation

uint8_t SelfTest_DMA_DW	(	DW_Type *	base,
		uint32_t	channel,
		cy_stc_dma_descriptor_t *	descriptor0,
		cy_stc_dma_descriptor_t *	descriptor1,
		const cy_stc_dma_descriptor_config_t *	des0_config,
		const cy_stc_dma_descriptor_config_t *	des1_config,
		cy_stc_dma_channel_config_t const *	channelConfig,
		uint32_t	trigLine )

This function writes a pattern (66 bytes) to the destination using the DMA, and the destination block is verified to contain the correct pattern.

Parameters

base	The pointer to the hardware DMA block.
channel	The channel number.
descriptor0	The descriptor to associate with the channel (transfer 0's to destination).
descriptor1	The descriptor to associate with the channel (transfer pattern to destination).
des0_config	The configuration structure with all initialization information for the descriptor.
des1_config	The configuration structure with all initialization information for the descriptor.
channelConfig	The structure that contains the initialization information for the channel.
trigLine	The input of the trigger mux. -> Bit 30 represents if the signal is an input/output. When this bit is set, the trigger activation is for an output trigger from the trigger multiplexer. When this bit is reset, the trigger activation is for an input trigger to the trigger multiplexer. -> Bits 12:8 represent the trigger group selection. -> For the output trigger line (bit 30 is set): For PERI_ver1: -> Bits 6:0 select the output trigger number in the trigger group. For PERI_ver2: -> Bits 7:0 select the output trigger number in the trigger group. In case of input trigger line (bit 30 is unset): -> Bits 7:0 select the input trigger signal for the trigger multiplexer

Note: Applicable only for PSOC 61 Programmable Line, PSOC 62 Performance Line, PSOC Control C3, XMC7000 and XMC5000 devices. Use a DMA channel, descriptors, and trigger line dedicated to this self-test. The function initializes the descriptors and channel, sets the descriptor source/destination addresses, and enables the selected DMA channel.