CLB (CLB STL module)

General Description

The CLB (Custom Logic Block) self-test validates the DICO (Digital Current Observer) sub-block and the MACO (Matrix Commutation) sub-block of the PPCA subsystem.

Six independent sub-tests are provided and can be selected via a bitmask:

Test A - DICO kill-path / safe-state transition

Confirms the kill override actually drives the DICO output state rather than reading the default-asserted SAFE_STATE bit (which reads 1 out of reset). The test procedure:

 1) Save all CLB and DICO registers that are modified.
 2) Enable CLB (select DICO output) and DICO; load a known SAFE_REG
    pattern; start timer-driven phase switching so the PCO actively
    drives the outputs (no ADC data required).
 3) Confirm DICO leaves the safe state (SAFE_STATE clears to 0).
 4) Assert a software Kill event; confirm the hardware forces the safe
    state back on (KILL_STATE and SAFE_STATE both set).
 5) Exit Kill; confirm KILL_STATE clears.
 6) Restore all saved registers.

Test B - DICO interrupt path functional test

The test procedure:

 1) Enable CLB and DICO; disable all DICO interrupt sources (INTR_MASK = 0)
    to prevent spurious ISR delivery during the test.
 2) Clear any pending interrupt flags in INTR.
 3) INTR_MASK round-trip: write 0xFF to INTR_MASK and verify all 8 bits are
    set; write 0x00 and verify all 8 bits cleared.
 4) INTR_SET path: software-assert one interrupt bit via the INTR_SET
    register; read INTR and verify the bit is set; write the same bit back to
    INTR (write-1-to-clear); read INTR and verify the bit is cleared.
 5) INTR_MASKED path: enable one bit in INTR_MASK; software-assert the same
    bit via INTR_SET; read INTR_MASKED and verify the bit is present (= INTR
    AND INTR_MASK); clear the INTR bit and disable the mask bit; read
    INTR_MASKED and verify the bit is absent.
 6) Restore the original DICO control and interrupt-mask registers; restore
    CLB control.

Test C - DICO autonomous switching verification

The test procedure:

 1) Save original CLB and DICO register values.
 2) Enable CLB and DICO; disable all DICO interrupt sources.
 3) Configure DICO Phase 1: IMINL = 0, IMAXL = large, numPeriod = 4,
    small pwmMaxOnTime (forces rapid timer-driven switching).
 4) Clear any pending DICO interrupt flags.
 5) Enable Phase 1 - DICO state machine begins autonomous switching.
 6) Poll DICO INTR until any interrupt bit is set (hardware-generated,
    timer-driven) or a timeout expires.  Any DICO interrupt confirms
    the control logic and interrupt path are functional; the specific
    source (PS, PCO, or PE) depends on silicon revision and
    phase-enabler configuration and is not material to the test.
 7) Restore all saved registers.

Note

ADC data is not required. DICO switches autonomously on the internal pwmMaxOnTime timer. No external EPU or power converter is needed.

Test D - DICO IL data path (ADC test-mode + AFLT[0] + DICO)

Validates the signal chain: ADC (test mode) -> AFLT[0] Median -> FILT_OUT0 -> DICO IL_ACCU

The test procedure:

 1) Enable PPCA and AREF; bring up ADC channel 0 with a full
    Cy_PPCA_ADC_Init() and configure AFLT[0] (PPCA_ATOPSS_ADC_GRP0_AFLT0)
    with the Median stage active (a 1-sample median is a transparent
    pass-through that drives the AFLT pipeline clock so FILT_OUT0 tracks
    ADC channel 0).  Save all modified registers.
 2) Enable ADC test mode with calibration gain bypassed so known values
    can be injected via Cy_PPCA_ADC_Write_Test_data().
 3) Changing-results check: inject a low (0) then a high value, reading
    back the channel-0 ADC result after each, and confirm the result
    tracks the input (high > low) - proving the path produces changing
    results rather than a stuck constant.  The high value is injected
    last and remains latched in FILT_OUT0.
 4) Enable DICO Phase 1 with IL1 = CY_ADC_GROUP_0_FILT_OUT0 and confirm
    IL_ACCU becomes non-zero, proving the latched FILT_OUT0 value reaches
    and accumulates in the DICO observer.  The sub-test passes only when
    both (3) and (4) hold.
 5) Restore all saved registers.

Note

No external EPU or power converter is needed.

Test E - DICO limit / threshold detection

The test procedure:

 1) INCORR_SETTING: program an illegal limit pair (IMINL > IMAXL) and
    confirm STAT.INCORR_SETTING is set; restore a legal IMIN < IMAX
    ordering and confirm it clears once a switching cycle latches the
    new limits.
 2) MAX_ON_REACHED: with a small MAX_ON_TIME and autonomous switching,
    confirm the on-time limiter asserts STAT.MAX_ON_REACHED.
 3) Restore all saved registers.

Note

No analog stimulus or external hardware is needed.

Test F - MACO sequencer functional test

The test procedure:

 1) Save original CLB and MACO control register values; reset MACO to a
    clean state and initialize three identical minimal sectors in
    manual-transition mode.
 2) Enable CLB (select MACO output) and MACO; confirm the sequencer
    starts scanning (CY_SCAN_IN_PROGRESS) and is not in safe state.
 3) Issue SelectNextPattern(NEXT_SECTOR) + TransitPattern; confirm the
    FSM advances to Sector 1 (current-scanning field = Sector 1).
 4) Assert software KillEvent; verify STATUS shows both CY_MACO_KILL_STATE
    and CY_MACO_SAFE_STATE; call KillExit to restore normal operation.
 5) Restore original CLB and MACO control register values.

Note

No external hardware is required. MACO is configured with minimal sector patterns that complete within a few clock cycles.

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