UART Data Transfer (UART Data Transfer STL module)

General Description

The UART SCB Components are used to physically generate signals.

The software CRC-16 calculation is applied to every sent/received byte (except STX and the CRC itself). To detect an unsuccessful packet transaction, the timer is used.

Three interrupts implemented in this project provide a fully interrupt-driven background process:
1) The transmit interrupt in the UART is configured for a FIFO not-full event to take the new data from the RAM and place it into the TX buffer, and for a transmit complete event to start or stop the CRC calculation.
2) The receive interrupt in the UART is configured for a FIFO not-empty event to analyze the received data, calculate the CRC, and store the received data into RAM.
3) The timer interrupt is used to detect the end of an unsuccessful transmission.

More Information

Protocol description Master(A) slave(B) communication:

|---|    --- Request send --->    |---| 

| A |    {Wait for respond}       | B | 

|---|    <--- Respond send ---    |---| 

Packet format:
1)

<STX><ADDR><DL><[Data bytes length equal DL]><CRCH><CRCL> 

  a) STX        - 0x02 starts the packet marker. The unique byte of the start packet.
  b) ADDR       - The device address.
  c) DL         - The data length in bytes [1..255].
  d) CRCH       - MSB of CRC-16 calculated from ADDR to the last data byte.
  e) CRCL       - LSB of CRC-16 calculated from ADDR to the last data byte.

2) If there is a byte

<ADDR> <DL> <[Data]> or <[CRC]> 

that equals STX, then it is exchanged with the two-byte sequence

<ESC><STX+1>. 

3) If there is a byte

<ADDR> <DL> <[Data]> or <[CRC]> 

that equals ESC, then it is exchanged with the two-byte sequence

<ESC><ESC+1>. 

API Reference
	Master
	Slave