ATOP ADC Core (ATOP ADC Core STL module)

General Description

The ATOP ADC Core self-test validates the 12-bit SAR ADC by performing a conversion of a known internal reference voltage and comparing the result against an expected value: the input is connected to a reference whose nominal value is known, sampled through the converter datapath, and the read-back code is verified to lie within a specified tolerance of the expected code.

The device exposes four independent ADC groups, but only group 0 provides an on-chip reference (the 1.2 V VREF) reachable by the SAR through its AUX multiplexer. The self-test therefore covers ADC group 0 only; the other groups have no internal stimulus that the SAR can convert and would require an external known voltage, which is out of scope for this test.

The test exercises, on ADC group 0:

• The SAR conversion of a known voltage.
• The internal 1.2 V reference path.
• The AUX channel multiplexer routing (channel 7).
• The ADC trigger / busy / result data path.

More Information

The test procedure for ADC group 0:

 1) Save the ADC and AFE configuration registers that are modified
    by the test.
 2) Initialise the ADC in manual-trigger, AUX-only mode and route the
    internal reference (VREF = 1.2 V) to the AUX slot on channel 7,
    with AFE in unity / pass-through gain.
 3) Trigger one conversion, poll the ADC busy status with a defensive
    timeout, and read the AUX result register.
 4) Compare the read-back code against the pre-computed expected code
    within a fixed tolerance.
 5) If the ERROR_IN_ATOP_ADC error-injection flag is set, corrupt the
    measured code by more than the tolerance so that a fault-free run is
    forced outside the acceptance window and reported as failed.
 6) Restore the original ADC / AFE configuration and return the
    result.

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