Performs an ADC self-test by issuing a firmware SAR trigger and verifying that the measured result falls within the expected range.
HPPASS subsystem configuration and signal routing:
The test uses the CSG VDAC (pass[0].csg[0].slice[0]) as an internally generated stimulus so that no external reference voltage is required on any device pin. The complete analog signal path through the HPPASS block is:
CSG Group 0, Slice 0 (VDAC, buffered, 10-bit) → CSG analog router (dacOutSelLoc = 1) → SAR muxed sampler input → SAR channel CSG_VDAC_OUT_CHAN_IDX (defined in cycfg_peripherals.h)
The following HPPASS configurations are required:
- CSG[0]: Group 0 power enabled (grpPwrEn0 = true), CSG AROUTE mux not used (arouteMuxSel0 = CY_HPPASS_CSG_AROUTE_NONE), DAC output location 1 (dacOutSelLoc = 1, routes the VDAC output to the HPPASS analog router so the SAR muxed sampler can reach it).
- CSG[0] Slice 0: mode = CY_HPPASS_DAC_MODE_BUFFERED (10-bit VDAC with output buffer).
- HPPASS input trigger 2 (pass[0].input_trigger[2]): CY_HPPASS_TR_FW_PULSE — used to fire the SAR sequencer group that samples the DAC output (passed as
trig_in = CY_HPPASS_TRIG_2_MSK).
- SAR[0]: Vref = CY_HPPASS_SAR_VREF_VDDA, 12-bit result, right-aligned, unsigned. Muxed sampler 0 (pass[0].sar[0].muxed_sampler[0]) connected to the CSG VDAC analog router output.
- SAR[0] sequencer group (pass[0].sar[0].seq[0].grp[N]): muxed sampler 0 enabled (muxSampEn0 = true), mux input select pointing to the CSG VDAC output, trigger = CY_HPPASS_SAR_TRIG_2 (corresponding to
trig_in). The result is stored in SAR channel CSG_VDAC_OUT_CHAN_IDX.
- Autonomous Controller (pass[0].ac[0]): the HPPASS AC must be started (Cy_HPPASS_AC_Start()) before any SAR conversion can be triggered. The AC Finite State Automaton (FSA) must be configured with at least one state (pass[0].ac[0].stt[0].vstate[0]) that keeps the subsystem running, e.g. action = CY_HPPASS_ACTION_STOP with count = 1. The AC holds the HPPASS clock and power rails active; without it the SAR trigger is ignored.
The caller must pre-stage the DAC stimulus before calling this function: program the desired 10-bit code with Cy_HPPASS_DAC_SetValue(), start the DAC slice with Cy_HPPASS_DAC_Start() in HW mode, and wait for the DAC to settle before invoking SelfTests_ADC_TrigIn(). This function then issues the SAR trigger specified by trig_in and reads the conversion result from channel.
- Parameters
-
| group | SAR group instance (0 for SAR[0]). |
| channel | SAR channel index where the DAC stimulus is sampled. Use the macro CSG_VDAC_OUT_CHAN_IDX generated in cycfg_peripherals.h for the target BSP. |
| expected_res | Expected ADC result in counts (12-bit, Vref = VDDA). |
| accuracy | Acceptable deviation from expected_res in counts (ANALOG_ADC_ACCURACY). |
| trig_in | HPPASS input trigger mask that fires the SAR sequencer group containing the muxed sampler channel (e.g. CY_HPPASS_TRIG_2_MSK). |
- Returns
- OK_STATUS (0) - Test passed
ERROR_STATUS (1) - Test failed