Macros | |
| #define | STL_ADC_CONFIG_MAX_CHAN (32u) |
| Number of per-channel register slots covered by the snapshot/mask structures. | |
| #define | STL_ADC_CONFIG_TR_SEL_NUM (4u) |
Number of shared generic trigger input/output selector registers in PASS_EPASS_MMIO_Type (one slot per possible SAR ADC instance). | |
| #define STL_ADC_CONFIG_MAX_CHAN (32u) |
Number of per-channel register slots covered by the snapshot/mask structures.
Matches the fixed CH[32] array size of PASS_SAR_Type.