Macros

General Description

Macros
#define	ATOP_ADC_CORE_GROUP_0   (0U)
	ATOP ADC group 0 index.
#define	ATOP_ADC_CORE_GROUP_1   (1U)
	ATOP ADC group 1 index.
#define	ATOP_ADC_CORE_GROUP_2   (2U)
	ATOP ADC group 2 index.
#define	ATOP_ADC_CORE_GROUP_3   (3U)
	ATOP ADC group 3 index.
#define	ATOP_ADC_CORE_GROUP_COUNT   (4U)
	Number of ADC groups.
#define	ATOP_ADC_CORE_CHANNEL_COUNT   (8U)
	Number of SAR channels on ADC groups 0 and 3 (single-ended channels 0..7).
#define	ATOP_ADC_CORE_CHANNEL_COUNT_GRP12   (4U)
	Number of SAR channels on ADC groups 1 and 2 (single-ended channels 0..3).
#define	ATOP_ADC_CORE_AUX_CHANNEL   (7U)
	ADC channel index (7) onto which the AUX multiplexer is routed; this is the channel that carries the internal reference.
#define	ATOP_ADC_CORE_MAX_CODE   (4095U)
	Maximum 12-bit SAR conversion code.
#define	ATOP_ADC_CORE_VREF_EXPECTED_CODE   (1490U)
	Expected 12-bit code for the internal 1.2 V bandgap VREF, converted ratiometrically against VDDA and assuming VDDA = 3.3 V (round(1.2 / 3.3 * 4095) = 1490).
#define	ATOP_ADC_CORE_VREF_TOLERANCE_CODE   (200U)
	Acceptance window (+/- codes) around the VREF expected code.

Macro Definition Documentation

ATOP_ADC_CORE_AUX_CHANNEL

#define ATOP_ADC_CORE_AUX_CHANNEL   (7U)

ADC channel index (7) onto which the AUX multiplexer is routed; this is the channel that carries the internal reference.

The AUX source itself (e.g. VREF) is selected separately via the PDL cy_en_aux_channel_t.

ATOP_ADC_CORE_VREF_EXPECTED_CODE

#define ATOP_ADC_CORE_VREF_EXPECTED_CODE   (1490U)

Expected 12-bit code for the internal 1.2 V bandgap VREF, converted ratiometrically against VDDA and assuming VDDA = 3.3 V (round(1.2 / 3.3 * 4095) = 1490).

On boards with a different VDDA rail, pass a supply-specific expectedCode in stl_atop_adc_core_config_t instead of using this default.