PWM (PWM STL module)

General Description

This module performs PWM test and verifies that the duty cycle set is actually achieved in the output.

More Information

A 16-bit PWM is configured to a 33% duty cycle with a 1ms period and the output is continuously polled in the loop for 5ms. The test is successful if the off/on ratio is between 1.875(1 7/8) to 2.125(2 1/8). A range is used because the CPU polling loop is asynchronous to the PWM timing.

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