Functions | |
cy_en_sysclk_status_t | Cy_SysClk_PllConfigure (uint32_t clkPath, const cy_stc_pll_config_t *config) |
Configures a given PLL. More... | |
cy_en_sysclk_status_t | Cy_SysClk_PllManualConfigure (uint32_t clkPath, const cy_stc_pll_manual_config_t *config) |
Manually configures a PLL based on user inputs. More... | |
cy_en_sysclk_status_t | Cy_SysClk_PllGetConfiguration (uint32_t clkPath, cy_stc_pll_manual_config_t *config) |
Reports configuration settings for a PLL. More... | |
cy_en_sysclk_status_t | Cy_SysClk_PllEnable (uint32_t clkPath, uint32_t timeoutus) |
Enables the PLL. More... | |
bool | Cy_SysClk_PllIsEnabled (uint32_t clkPath) |
Reports whether or not the selected PLL is enabled. More... | |
bool | Cy_SysClk_PllLocked (uint32_t clkPath) |
Reports whether or not the selected PLL is locked. More... | |
bool | Cy_SysClk_PllLostLock (uint32_t clkPath) |
Reports whether or not the selected PLL lost its lock since the last time this function was called. More... | |
cy_en_sysclk_status_t | Cy_SysClk_PllDisable (uint32_t clkPath) |
Disables the selected PLL. More... | |
uint32_t | Cy_SysClk_PllGetFrequency (uint32_t clkPath) |
Returns the output frequency of the PLL. More... | |
cy_en_sysclk_status_t | Cy_SysClk_DpllLpConfigure (uint32_t pllNum, const cy_stc_pll_config_t *config) |
Configures DPLL-LP. More... | |
cy_en_sysclk_status_t | Cy_SysClk_DpllLpManualConfigure (uint32_t pllNum, const cy_stc_pll_manual_config_t *config) |
Manually configures a DPLL-LP based on user inputs. More... | |
cy_en_sysclk_status_t | Cy_SysClk_DpllLpGetConfiguration (uint32_t pllNum, cy_stc_pll_manual_config_t *config) |
Reports configuration settings for DPLL-LP. More... | |
cy_en_sysclk_status_t | Cy_SysClk_DpllLpEnable (uint32_t pllNum, uint32_t timeoutus) |
Enables the DPLL-LP. More... | |
bool | Cy_SysClk_DpllLpIsEnabled (uint32_t pllNum) |
Reports whether or not the selected DPLL-LP is enabled. More... | |
bool | Cy_SysClk_DpllLpLocked (uint32_t pllNum) |
Reports whether or not the selected DPLL-LP is locked. More... | |
bool | Cy_SysClk_DpllLpLostLock (uint32_t pllNum) |
Reports whether or not the selected DPLL-LP lost its lock since the last time this function was called. More... | |
cy_en_sysclk_status_t | Cy_SysClk_DpllLpDisable (uint32_t pllNum) |
Disables the selected DPLL-LP. More... | |
uint32_t | Cy_SysClk_DpllLpGetFrequency (uint32_t pllNum) |
Gets the frequency of DPLL-LP. More... | |
cy_en_sysclk_status_t | Cy_SysClk_DpllHpConfigure (uint32_t pllNum, const cy_stc_pll_config_t *config) |
Configures DPLL-HP. More... | |
cy_en_sysclk_status_t | Cy_SysClk_DpllHpManualConfigure (uint32_t pllNum, const cy_stc_pll_manual_config_t *config) |
Manually configures a DPLL-HP based on user inputs. More... | |
cy_en_sysclk_status_t | Cy_SysClk_DpllHpGetConfiguration (uint32_t pllNum, cy_stc_pll_manual_config_t *config) |
Reports configuration settings for DPLL-HP. More... | |
cy_en_sysclk_status_t | Cy_SysClk_DpllHpEnable (uint32_t pllNum, uint32_t timeoutus) |
Enables the DPLL-HP. More... | |
bool | Cy_SysClk_DpllHpIsEnabled (uint32_t pllNum) |
Reports whether or not the selected DPLL-HP is enabled. More... | |
bool | Cy_SysClk_DpllHpLocked (uint32_t pllNum) |
Reports whether or not the selected DPLL-HP is locked. More... | |
bool | Cy_SysClk_DpllHpLostLock (uint32_t pllNum) |
Reports whether or not the selected DPLL-HP lost its lock since the last time this function was called. More... | |
cy_en_sysclk_status_t | Cy_SysClk_DpllHpDisable (uint32_t pllNum) |
Disables the selected DPLL-HP. More... | |
uint32_t | Cy_SysClk_DpllHpGetFrequency (uint32_t pllNum) |
Gets the frequency of DPLL-HP. More... | |
cy_en_sysclk_status_t | Cy_SysClk_Pll200MConfigure (uint32_t pllNum, const cy_stc_pll_config_t *config) |
Configures 200M PLL. More... | |
cy_en_sysclk_status_t | Cy_SysClk_Pll200MManualConfigure (uint32_t pllNum, const cy_stc_pll_manual_config_t *config) |
Manually configures a 200M PLL based on user inputs. More... | |
cy_en_sysclk_status_t | Cy_SysClk_Pll200MGetConfiguration (uint32_t pllNum, cy_stc_pll_manual_config_t *config) |
Reports configuration settings for 200M PLL. More... | |
cy_en_sysclk_status_t | Cy_SysClk_Pll200MEnable (uint32_t pllNum, uint32_t timeoutus) |
Enables the 200M PLL. More... | |
bool | Cy_SysClk_Pll200MIsEnabled (uint32_t pllNum) |
Reports whether or not the selected 200M PLL is enabled. More... | |
bool | Cy_SysClk_Pll200MLocked (uint32_t pllNum) |
Reports whether or not the selected 200M PLL is locked. More... | |
bool | Cy_SysClk_Pll200MLostLock (uint32_t pllNum) |
Reports whether or not the selected 200M PLL lost its lock since the last time this function was called. More... | |
cy_en_sysclk_status_t | Cy_SysClk_Pll200MDisable (uint32_t pllNum) |
Disables the selected 200M PLL. More... | |
uint32_t | Cy_SysClk_Pll200MGetFrequency (uint32_t pllNum) |
Gets the frequency of PLL200M. More... | |
cy_en_sysclk_status_t Cy_SysClk_PllConfigure | ( | uint32_t | clkPath, |
const cy_stc_pll_config_t * | config | ||
) |
Configures a given PLL.
The configuration formula used is: Fout = pll_clk * (P / Q / div_out), where: Fout is the desired output frequency pll_clk is the frequency of the input source P is the feedback divider. Its value is in bitfield FEEDBACK_DIV. Q is the reference divider. Its value is in bitfield REFERENCE_DIV. div_out is the reference divider. Its value is in bitfield OUTPUT_DIV.
clkPath | Selects which PLL to configure. 1 is the first PLL; 0 is invalid. |
config | cy_stc_pll_config_t |
cy_en_sysclk_status_t Cy_SysClk_PllManualConfigure | ( | uint32_t | clkPath, |
const cy_stc_pll_manual_config_t * | config | ||
) |
Manually configures a PLL based on user inputs.
clkPath | Selects which PLL to configure. 1 is the first PLL; 0 is invalid. |
config | cy_stc_pll_manual_config_t |
cy_en_sysclk_status_t Cy_SysClk_PllGetConfiguration | ( | uint32_t | clkPath, |
cy_stc_pll_manual_config_t * | config | ||
) |
Reports configuration settings for a PLL.
clkPath | Selects which PLL to report. 1 is the first PLL; 0 is invalid. |
config | cy_stc_pll_manual_config_t |
cy_en_sysclk_status_t Cy_SysClk_PllEnable | ( | uint32_t | clkPath, |
uint32_t | timeoutus | ||
) |
Enables the PLL.
The PLL should be configured before calling this function.
clkPath | Selects which PLL to enable. 1 is the first PLL; 0 is invalid. |
timeoutus | amount of time in microseconds to wait for the PLL to lock. If the lock doesn't occur, PLL is stopped. To avoid waiting for lock, set this to 0 and manually check for lock using Cy_SysClk_PllLocked. |
bool Cy_SysClk_PllIsEnabled | ( | uint32_t | clkPath | ) |
Reports whether or not the selected PLL is enabled.
clkPath | Selects which PLL to check. 1 is the first PLL; 0 is invalid. |
bool Cy_SysClk_PllLocked | ( | uint32_t | clkPath | ) |
Reports whether or not the selected PLL is locked.
clkPath | Selects which PLL to check. 1 is the first PLL; 0 is invalid. |
bool Cy_SysClk_PllLostLock | ( | uint32_t | clkPath | ) |
Reports whether or not the selected PLL lost its lock since the last time this function was called.
Clears the lost lock indicator.
clkPath | Selects which PLL to check. 1 is the first PLL; 0 is invalid. |
cy_en_sysclk_status_t Cy_SysClk_PllDisable | ( | uint32_t | clkPath | ) |
Disables the selected PLL.
clkPath | Selects which PLL to disable. 1 is the first PLL; 0 is invalid. |
uint32_t Cy_SysClk_PllGetFrequency | ( | uint32_t | clkPath | ) |
Returns the output frequency of the PLL.
clkPath | Selects the path on which the PLL frequency has to be obtained. |
cy_en_sysclk_status_t Cy_SysClk_DpllLpConfigure | ( | uint32_t | pllNum, |
const cy_stc_pll_config_t * | config | ||
) |
Configures DPLL-LP.
The configuration formula used is: Fout = pll_clk * (P / Q / div_out), where: Fout is the desired output frequency pll_clk is the frequency of the input source P is the feedback divider. Its value is in bitfield FEEDBACK_DIV. Q is the reference divider. Its value is in bitfield REFERENCE_DIV. div_out is the reference divider. Its value is in bitfield OUTPUT_DIV.
pllNum | Selects which DPLL-LP to configure |
config | cy_stc_pll_config_t |
cy_en_sysclk_status_t Cy_SysClk_DpllLpManualConfigure | ( | uint32_t | pllNum, |
const cy_stc_pll_manual_config_t * | config | ||
) |
Manually configures a DPLL-LP based on user inputs.
pllNum | Selects which DPLL-LP to configure. |
config | cy_stc_pll_manual_config_t |
cy_en_sysclk_status_t Cy_SysClk_DpllLpGetConfiguration | ( | uint32_t | pllNum, |
cy_stc_pll_manual_config_t * | config | ||
) |
Reports configuration settings for DPLL-LP.
pllNum | Selects which DPLL-LP to report. |
config | cy_stc_pll_manual_config_t |
cy_en_sysclk_status_t Cy_SysClk_DpllLpEnable | ( | uint32_t | pllNum, |
uint32_t | timeoutus | ||
) |
Enables the DPLL-LP.
The PLL should be configured before calling this function.
pllNum | Selects which DPLL-LP to enable. |
timeoutus | amount of time in microseconds to wait for the PLL to lock. If the lock doesn't occur, PLL is stopped. To avoid waiting for lock, set this to 0 and manually check for lock using Cy_SysClk_PllLocked. |
bool Cy_SysClk_DpllLpIsEnabled | ( | uint32_t | pllNum | ) |
Reports whether or not the selected DPLL-LP is enabled.
pllNum | Selects which DPLL-LP to check. |
bool Cy_SysClk_DpllLpLocked | ( | uint32_t | pllNum | ) |
Reports whether or not the selected DPLL-LP is locked.
pllNum | Selects which DPLL-LP to check. |
bool Cy_SysClk_DpllLpLostLock | ( | uint32_t | pllNum | ) |
Reports whether or not the selected DPLL-LP lost its lock since the last time this function was called.
Clears the lost lock indicator.
pllNum | Selects which DPLL-LP to check. |
cy_en_sysclk_status_t Cy_SysClk_DpllLpDisable | ( | uint32_t | pllNum | ) |
Disables the selected DPLL-LP.
pllNum | Selects which DPLL-LP to disable. |
uint32_t Cy_SysClk_DpllLpGetFrequency | ( | uint32_t | pllNum | ) |
Gets the frequency of DPLL-LP.
pllNum | Selects which DPLL-LP to check. |
cy_en_sysclk_status_t Cy_SysClk_DpllHpConfigure | ( | uint32_t | pllNum, |
const cy_stc_pll_config_t * | config | ||
) |
Configures DPLL-HP.
The configuration formula used is: Fout = (pll_clk * NDIV) / (PDIV * KDIV), where: Fout is the desired output frequency pll_clk is the frequency of the input source NDIV is the Ratio between DCO frequency and reference frequency. PDIV is the reference divider. KDIV is the post divider.
pllNum | Selects which DPLL-HP to configure |
config | cy_stc_pll_config_t |
cy_en_sysclk_status_t Cy_SysClk_DpllHpManualConfigure | ( | uint32_t | pllNum, |
const cy_stc_pll_manual_config_t * | config | ||
) |
Manually configures a DPLL-HP based on user inputs.
pllNum | Selects which DPLL-HP to configure. |
config | cy_stc_pll_manual_config_t |
cy_en_sysclk_status_t Cy_SysClk_DpllHpGetConfiguration | ( | uint32_t | pllNum, |
cy_stc_pll_manual_config_t * | config | ||
) |
Reports configuration settings for DPLL-HP.
pllNum | Selects which DPLL-HP to report. |
config | cy_stc_pll_manual_config_t |
cy_en_sysclk_status_t Cy_SysClk_DpllHpEnable | ( | uint32_t | pllNum, |
uint32_t | timeoutus | ||
) |
Enables the DPLL-HP.
The PLL should be configured before calling this function.
pllNum | Selects which DPLL-HP to enable. |
timeoutus | amount of time in microseconds to wait for the PLL to lock. If the lock doesn't occur, PLL is stopped. To avoid waiting for lock, set this to 0 and manually check for lock using Cy_SysClk_PllLocked. |
bool Cy_SysClk_DpllHpIsEnabled | ( | uint32_t | pllNum | ) |
Reports whether or not the selected DPLL-HP is enabled.
pllNum | Selects which DPLL-HP to check. |
bool Cy_SysClk_DpllHpLocked | ( | uint32_t | pllNum | ) |
Reports whether or not the selected DPLL-HP is locked.
pllNum | Selects which DPLL-HP to check. |
bool Cy_SysClk_DpllHpLostLock | ( | uint32_t | pllNum | ) |
Reports whether or not the selected DPLL-HP lost its lock since the last time this function was called.
Clears the lost lock indicator.
pllNum | Selects which DPLL-HP to check. |
cy_en_sysclk_status_t Cy_SysClk_DpllHpDisable | ( | uint32_t | pllNum | ) |
Disables the selected DPLL-HP.
pllNum | Selects which DPLL-HP to disable. |
uint32_t Cy_SysClk_DpllHpGetFrequency | ( | uint32_t | pllNum | ) |
Gets the frequency of DPLL-HP.
pllNum | Selects which DPLL-HP to check. |
cy_en_sysclk_status_t Cy_SysClk_Pll200MConfigure | ( | uint32_t | pllNum, |
const cy_stc_pll_config_t * | config | ||
) |
Configures 200M PLL.
The configuration formula used is: Fout = pll_clk * (P / Q / div_out), where: Fout is the desired output frequency pll_clk is the frequency of the input source P is the feedback divider. Its value is in bitfield FEEDBACK_DIV. Q is the reference divider. Its value is in bitfield REFERENCE_DIV. div_out is the reference divider. Its value is in bitfield OUTPUT_DIV.
pllNum | Selects which PLL to configure |
config | cy_stc_pll_config_t |
cy_en_sysclk_status_t Cy_SysClk_Pll200MManualConfigure | ( | uint32_t | pllNum, |
const cy_stc_pll_manual_config_t * | config | ||
) |
Manually configures a 200M PLL based on user inputs.
pllNum | Selects which PLL to configure. |
config | cy_stc_pll_manual_config_t |
cy_en_sysclk_status_t Cy_SysClk_Pll200MGetConfiguration | ( | uint32_t | pllNum, |
cy_stc_pll_manual_config_t * | config | ||
) |
Reports configuration settings for 200M PLL.
pllNum | Selects which PLL to report. |
config | cy_stc_pll_manual_config_t |
cy_en_sysclk_status_t Cy_SysClk_Pll200MEnable | ( | uint32_t | pllNum, |
uint32_t | timeoutus | ||
) |
Enables the 200M PLL.
The PLL should be configured before calling this function.
pllNum | Selects which PLL to enable. |
timeoutus | amount of time in microseconds to wait for the PLL to lock. If the lock doesn't occur, PLL is stopped. To avoid waiting for lock, set this to 0 and manually check for lock using Cy_SysClk_PllLocked. |
bool Cy_SysClk_Pll200MIsEnabled | ( | uint32_t | pllNum | ) |
Reports whether or not the selected 200M PLL is enabled.
pllNum | Selects which PLL to check. |
bool Cy_SysClk_Pll200MLocked | ( | uint32_t | pllNum | ) |
Reports whether or not the selected 200M PLL is locked.
pllNum | Selects which PLL to check. |
bool Cy_SysClk_Pll200MLostLock | ( | uint32_t | pllNum | ) |
Reports whether or not the selected 200M PLL lost its lock since the last time this function was called.
Clears the lost lock indicator.
pllNum | Selects which PLL to check. |
cy_en_sysclk_status_t Cy_SysClk_Pll200MDisable | ( | uint32_t | pllNum | ) |
Disables the selected 200M PLL.
pllNum | Selects which PLL to disable. |
uint32_t Cy_SysClk_Pll200MGetFrequency | ( | uint32_t | pllNum | ) |
Gets the frequency of PLL200M.
pllNum | Selects which PLL to check. |