General Description

Functions
cy_en_sysclk_status_t	Cy_SysClk_ClkHfEnable (uint32_t clkHf)
	Enables the selected clkHf. More...

bool	Cy_SysClk_ClkHfIsEnabled (uint32_t clkHf)
	Reports the Enabled/Disabled status of clkHf. More...

cy_en_sysclk_status_t	Cy_SysClk_ClkHfDisable (uint32_t clkHf)
	Disables the selected clkHf. More...

cy_en_sysclk_status_t	Cy_SysClk_ClkHfSetSource (uint32_t clkHf, cy_en_clkhf_in_sources_t source)
	Selects the source of the selected clkHf. More...

cy_en_clkhf_in_sources_t	Cy_SysClk_ClkHfGetSource (uint32_t clkHf)
	Reports the source of the selected clkHf. More...

cy_en_sysclk_status_t	Cy_SysClk_ClkHfSetDivider (uint32_t clkHf, cy_en_clkhf_dividers_t divider)
	Sets the pre-divider for a clkHf. More...

cy_en_clkhf_dividers_t	Cy_SysClk_ClkHfGetDivider (uint32_t clkHf)
	Reports the pre-divider value for a clkHf. More...

uint32_t	Cy_SysClk_ClkHfGetFrequency (uint32_t clkHf)
	Reports the frequency of the selected clkHf. More...

cy_en_sysclk_status_t	Cy_SysClk_ClkHfDirectSel (uint32_t clkHf, bool enable)
	Enable/Disable the direct source selection as IMO for CLK_HF[[n]]. More...

bool	Cy_SysClk_IsClkHfDirectSelEnabled (uint32_t clkHf)
	Checks if direct source selection as IMO for CLK_HF[[n]] is enabled/disabled. More...

uint32_t	Cy_SysClk_ClkHfGetMaskOnPath (cy_en_clkhf_in_sources_t clkPath)
	Get Mask value for the HF Clocks selected and enabled for clkPath as source e.g. More...

uint32_t	Cy_SysClk_ClkHfAllGetMask (void)
	Get Mask value for the all HF Clocks e.g. More...

void	Cy_SysClk_ClkHfEnableDividerWithMask (uint32_t clkHfMask, cy_en_clkhf_dividers_t divider)
	Divide all the enabled CLK_HF's with the divider value. More...

void	Cy_SysClk_ClkHfEnableDirectMuxWithMask (uint32_t clkHfMask, bool enable)
	Enable/ Disable the clock path for the HF Clocks in clkHfMask in disable case ROOT path will be enabled in enable case ROOT path will be disabled. More...

Function Documentation

◆ Cy_SysClk_ClkHfEnable()

cy_en_sysclk_status_t Cy_SysClk_ClkHfEnable ( uint32_t clkHf )

Enables the selected clkHf.

Parameters

clkHf Selects which clkHf to enable.

Returns: cy_en_sysclk_status_t CY_PRA_STATUS_* - For the PSoC 64 devices there are possible situations when function returns the PRA error status code cy_en_pra_status_t instead of cy_en_sysclk_status_t. This is because for PSoC 64 devices the function uses the PRA driver to change the protected registers. Refer to cy_en_pra_status_t for more details.

Function Usage: /* Scenario: ECO needs to source HFCLK2 through Path 2. The ECO is
configured through its function calls. */
#define CLKPATH2 (2UL)
#define HFCLK2 (2UL)
uint32_t clkPathMuxFreq = 0UL; /* Variable to store the Clock Path Mux output frequency */
/* Set the clock path 2 mux to be sourced from ECO */
if(CY_SYSCLK_SUCCESS == Cy_SysClk_ClkPathSetSource(CLKPATH2, CY_SYSCLK_CLKPATH_IN_ECO))
{
clkPathMuxFreq = Cy_SysClk_ClkPathMuxGetFrequency(CLKPATH2);
/* Now clkPathMuxFreq contains the Clock Path Mux output frequency */
}
else
{
/* Perform error handling */
}
/* Set the HFCLK2 source to clock path 2 and enable HFCLK2 */
(void)Cy_SysClk_ClkHfSetSource(HFCLK2, CY_SYSCLK_CLKHF_IN_CLKPATH2);
/* Enable HFCLK2 */
(void)Cy_SysClk_ClkHfEnable(HFCLK2);

◆ Cy_SysClk_ClkHfIsEnabled()

bool Cy_SysClk_ClkHfIsEnabled ( uint32_t clkHf )

Reports the Enabled/Disabled status of clkHf.

Parameters

clkHf Selects which clkHf to check.

Returns: Boolean status of clkHf: true - Enabled, false - Disabled.

Function Usage: /* Scenario: HFCLK1 is no longer required in the application and can be
switched off.
Note: HFCLK0 cannot be disabled */
#define HFCLK1 (1UL)
if (Cy_SysClk_ClkHfIsEnabled(HFCLK1))
{
/* Disable HFCLK1 */
(void)Cy_SysClk_ClkHfDisable(HFCLK1);
}

Note: This API is available for CAT1A devices.

◆ Cy_SysClk_ClkHfDisable()

cy_en_sysclk_status_t Cy_SysClk_ClkHfDisable ( uint32_t clkHf )

Disables the selected clkHf.

Parameters

clkHf Selects which clkHf to enable.

Returns: cy_en_sysclk_status_t

Note: clkHf[0] cannot be disabled.

Function Usage: /* Scenario: HFCLK1 is no longer required in the application and can be
switched off.
Note: HFCLK0 cannot be disabled */
#define HFCLK1 (1UL)
if (Cy_SysClk_ClkHfIsEnabled(HFCLK1))
{
/* Disable HFCLK1 */
(void)Cy_SysClk_ClkHfDisable(HFCLK1);
}

◆ Cy_SysClk_ClkHfSetSource()

cy_en_sysclk_status_t Cy_SysClk_ClkHfSetSource	(	uint32_t	clkHf,
		cy_en_clkhf_in_sources_t	source
	)

Selects the source of the selected clkHf.

Parameters

clkHf	selects which clkHf mux to configure.
source	cy_en_clkhf_in_sources_t

Returns: cy_en_sysclk_status_t CY_PRA_STATUS_* - For the PSoC 64 devices there are possible situations when function returns the PRA error status code cy_en_pra_status_t instead of cy_en_sysclk_status_t. This is because for PSoC 64 devices the function uses the PRA driver to change the protected registers. Refer to cy_en_pra_status_t for more details.

Note: Call SystemCoreClockUpdate after this function calling if it affects the CLK_HF0 frequency.; Call Cy_SysLib_SetWaitStates before calling this function if CLK_HF0 frequency is increasing.; Call Cy_SysLib_SetWaitStates after calling this function if CLK_HF0 frequency is decreasing.

Function Usage: /* Scenario: HFCLK1 source may have been updated to Path 0 somewhere in the
application. Check if it was and change the source to Path 1. */
if(CY_SYSCLK_CLKHF_IN_CLKPATH0 == Cy_SysClk_ClkHfGetSource(1UL))
{
/* Set the HFCLK1 source to Path 1 clock */
(void)Cy_SysClk_ClkHfDisable(1UL);
(void)Cy_SysClk_ClkHfSetSource(1UL, CY_SYSCLK_CLKHF_IN_CLKPATH1);
(void)Cy_SysClk_ClkHfEnable(1UL);
}

Note: Take into account the possible platform specific clkHf (and further clocking chain links) frequency limitations while using this API.; It takes four cycles of the originally selected clock to switch away from it. Do not disable the original clock during this time.

◆ Cy_SysClk_ClkHfGetSource()

cy_en_clkhf_in_sources_t Cy_SysClk_ClkHfGetSource ( uint32_t clkHf )

Reports the source of the selected clkHf.

Parameters

clkHf selects which clkHf to get the source of.

Returns: cy_en_clkhf_in_sources_t

Function Usage: /* Scenario: HFCLK1 source may have been updated to Path 0 somewhere in the
application. Check if it was and change the source to Path 1. */
if(CY_SYSCLK_CLKHF_IN_CLKPATH0 == Cy_SysClk_ClkHfGetSource(1UL))
{
/* Set the HFCLK1 source to Path 1 clock */
(void)Cy_SysClk_ClkHfDisable(1UL);
(void)Cy_SysClk_ClkHfSetSource(1UL, CY_SYSCLK_CLKHF_IN_CLKPATH1);
(void)Cy_SysClk_ClkHfEnable(1UL);
}

◆ Cy_SysClk_ClkHfSetDivider()

cy_en_sysclk_status_t Cy_SysClk_ClkHfSetDivider	(	uint32_t	clkHf,
		cy_en_clkhf_dividers_t	divider
	)

Sets the pre-divider for a clkHf.

Parameters

clkHf	selects which clkHf divider to configure.
divider	cy_en_clkhf_dividers_t

Returns: cy_en_sysclk_status_t CY_PRA_STATUS_* - For the PSoC 64 devices there are possible situations when function returns the PRA error status code cy_en_pra_status_t instead of cy_en_sysclk_status_t. This is because for PSoC 64 devices the function uses the PRA driver to change the protected registers. Refer to cy_en_pra_status_t for more details.

Note: Also call Cy_SysClk_ClkHfSetSource to set the clkHf source.; Call SystemCoreClockUpdate after this function calling if it affects the CLK_HF0 frequency.; Call Cy_SysLib_SetWaitStates before calling this function if CLK_HF0 frequency is increasing.; Call Cy_SysLib_SetWaitStates after calling this function if CLK_HF0 frequency is decreasing.; Take into account the possible platform specific clkHf (and further clocking chain links) frequency limitations while using this API.

Function Usage: /* Scenario: Set HFCLK0 divider to 8, to reduce frequency and save power */
if(CY_SYSCLK_CLKHF_DIVIDE_BY_8 != Cy_SysClk_ClkHfGetDivider(0UL))
{
/* Set the HFCLK0 divider to 8 */
(void)Cy_SysClk_ClkHfSetDivider(0UL, CY_SYSCLK_CLKHF_DIVIDE_BY_8);
}
/* Check the HFCLK0 frequency */
uint32_t clkHf0freq = Cy_SysClk_ClkHfGetFrequency(0UL);

◆ Cy_SysClk_ClkHfGetDivider()

cy_en_clkhf_dividers_t Cy_SysClk_ClkHfGetDivider ( uint32_t clkHf )

Reports the pre-divider value for a clkHf.

Parameters

clkHf selects which clkHf to check divider of.

Returns: cy_en_clkhf_dividers_t

Function Usage: /* Scenario: Set HFCLK0 divider to 8, to reduce frequency and save power */
if(CY_SYSCLK_CLKHF_DIVIDE_BY_8 != Cy_SysClk_ClkHfGetDivider(0UL))
{
/* Set the HFCLK0 divider to 8 */
(void)Cy_SysClk_ClkHfSetDivider(0UL, CY_SYSCLK_CLKHF_DIVIDE_BY_8);
}
/* Check the HFCLK0 frequency */
uint32_t clkHf0freq = Cy_SysClk_ClkHfGetFrequency(0UL);

◆ Cy_SysClk_ClkHfGetFrequency()

uint32_t Cy_SysClk_ClkHfGetFrequency ( uint32_t clkHf )

Reports the frequency of the selected clkHf.

Parameters

clkHf Selects the clkHf

Returns: The frequency, in Hz.

Note: The reported frequency may be zero, which indicates unknown. This happens if the source input is dsi_out or clk_altlf.; Calculates the HF frequency irrespective of whether HF is enabled or not.

Function Usage: /* Scenario: Set HFCLK0 divider to 8, to reduce frequency and save power */
if(CY_SYSCLK_CLKHF_DIVIDE_BY_8 != Cy_SysClk_ClkHfGetDivider(0UL))
{
/* Set the HFCLK0 divider to 8 */
(void)Cy_SysClk_ClkHfSetDivider(0UL, CY_SYSCLK_CLKHF_DIVIDE_BY_8);
}
/* Check the HFCLK0 frequency */
uint32_t clkHf0freq = Cy_SysClk_ClkHfGetFrequency(0UL);

◆ Cy_SysClk_ClkHfDirectSel()

cy_en_sysclk_status_t Cy_SysClk_ClkHfDirectSel	(	uint32_t	clkHf,
		bool	enable
	)

Enable/Disable the direct source selection as IMO for CLK_HF[[n]].

Parameters

clkHf	Selects the clkHf
enable	True - Selects IMO for CAT1B/CAT1C or IHO for CAT1D, False - Selects Root Mux

Returns: cy_en_sysclk_status_t CY_SYSCLK_BAD_PARAM - If clkhf is incorrect. CY_SYSCLK_SUCCESS - If successfully Enabled/Disabled.

Note: This API is available for CAT1A (TVIIBE only), CAT1B, CAT1C and CAT1D devices.

◆ Cy_SysClk_IsClkHfDirectSelEnabled()

bool Cy_SysClk_IsClkHfDirectSelEnabled ( uint32_t clkHf )

Checks if direct source selection as IMO for CLK_HF[[n]] is enabled/disabled.

Parameters

clkHf Selects the clkHf

Returns: True - IMO selected for CAT1A/CAT1B/CAT1C or IHO for CAT1D, False - Root Mux is selected.

Note: This API is available for CAT1A (TVIIBE only), CAT1B, CAT1C and CAT1D devices.

◆ Cy_SysClk_ClkHfGetMaskOnPath()

uint32_t Cy_SysClk_ClkHfGetMaskOnPath ( cy_en_clkhf_in_sources_t clkPath )

Get Mask value for the HF Clocks selected and enabled for clkPath as source e.g.

Mask return will have Bit 0 set if HFCLK0 is enabled and source is clkPath

Parameters

clkPath clock path

Returns: mask of CLKHF for which clock path is set

Note: This API is available CAT1D for LP PLL

◆ Cy_SysClk_ClkHfAllGetMask()

uint32_t Cy_SysClk_ClkHfAllGetMask ( void )

Get Mask value for the all HF Clocks e.g.

Mask return will have Bit 0 set if HFCLK0 is enabled

Returns: mask of CLKHF

Note: This API is available only for CAT1D devices

◆ Cy_SysClk_ClkHfEnableDividerWithMask()

void Cy_SysClk_ClkHfEnableDividerWithMask	(	uint32_t	clkHfMask,
		cy_en_clkhf_dividers_t	divider
	)

Divide all the enabled CLK_HF's with the divider value.

Parameters

clkHfMask	CLKHF mask for of the Clocks
divider	Divider Value cy_en_clkhf_dividers_t

Note: This API is available for CAT1D devices

◆ Cy_SysClk_ClkHfEnableDirectMuxWithMask()

void Cy_SysClk_ClkHfEnableDirectMuxWithMask	(	uint32_t	clkHfMask,
		bool	enable
	)

Enable/ Disable the clock path for the HF Clocks in clkHfMask in disable case ROOT path will be enabled in enable case ROOT path will be disabled.

Parameters

clkHfMask	CLKHF mask for of the Clocks
enable	to enable or disable direct path

Note: This API is available CAT1D for LP PLL, CDT_005549-196

General Description

Functions

Function Documentation

◆ Cy_SysClk_ClkHfEnable()

◆ Cy_SysClk_ClkHfIsEnabled()

◆ Cy_SysClk_ClkHfDisable()

◆ Cy_SysClk_ClkHfSetSource()

◆ Cy_SysClk_ClkHfGetSource()

◆ Cy_SysClk_ClkHfSetDivider()

◆ Cy_SysClk_ClkHfGetDivider()

◆ Cy_SysClk_ClkHfGetFrequency()

◆ Cy_SysClk_ClkHfDirectSel()

◆ Cy_SysClk_IsClkHfDirectSelEnabled()

◆ Cy_SysClk_ClkHfGetMaskOnPath()

◆ Cy_SysClk_ClkHfAllGetMask()

◆ Cy_SysClk_ClkHfEnableDividerWithMask()

◆ Cy_SysClk_ClkHfEnableDirectMuxWithMask()