Structure containing information for manual configuration of a PLL.
Data Fields | |
| uint8_t | feedbackDiv |
| CLK_PLL_CONFIG register, FEEDBACK_DIV (P) bits. | |
| uint8_t | referenceDiv |
| CLK_PLL_CONFIG register, REFERENCE_DIV (Q) bits. | |
| uint8_t | outputDiv |
| CLK_PLL_CONFIG register, OUTPUT_DIV bits. | |
| bool | lfMode |
| CLK_PLL_CONFIG register, PLL_LF_MODE bit. | |
| cy_en_fll_pll_output_mode_t | outputMode |
| CLK_PLL_CONFIG register, BYPASS_SEL bits. | |
| uint32_t | fracDiv |
| CLK_PLL_CONFIG2 register, FRAC_DIV bits, only for CAT1C devices. | |
| bool | fracDitherEn |
| CLK_PLL_CONFIG2 register, FRAC_DITHER_EN bit, only for CAT1C devices. | |
| bool | fracEn |
| CLK_PLL_CONFIG2 register, FRAC_EN bit, only for CAT1C devices. | |
| uint32_t | sscgDepth |
| CLK_PLL_CONFIG3 register, SSCG_DEPTH bits, only for CAT1C devices. | |
| uint8_t | sscgRate |
| CLK_PLL_CONFIG3 register, SSCG_RATE bits, only for CAT1C devices. | |
| bool | sscgEn |
| CLK_PLL_CONFIG3 register, SSCG_EN bit, only for CAT1C devices. | |
| cy_stc_dpll_lp_config_t * | lpPllCfg |
| DPLL-LP configuration. | |
| cy_stc_dpll_hp_config_t * | hpPllCfg |
| DPLL-HP configuration. | |