MTB CAT1 Peripheral driver library
Data Fields
cy_stc_pll_config_t Struct Reference
SysClk (System Clock) » Phase Locked Loop (PLL) » Data Structures

Description

Structure containing information for configuration of a PLL.

Data Fields

uint32_t inputFreq
 frequency of PLL source, in Hz
 
uint32_t outputFreq
 frequency of PLL output, in Hz
 
bool lfMode
 CLK_PLL_CONFIG register, PLL_LF_MODE bit.
 
cy_en_fll_pll_output_mode_t outputMode
 CLK_PLL_CONFIG register, BYPASS_SEL bits.