General Description

Functions
cy_en_sysclk_status_t	Cy_SysClk_ClkPathSetSource (uint32_t clkPath, cy_en_clkpath_in_sources_t source)
	Configures the source for the specified clock path. More...

cy_en_clkpath_in_sources_t	Cy_SysClk_ClkPathGetSource (uint32_t clkPath)
	Reports which source is selected for the path mux. More...

uint32_t	Cy_SysClk_ClkPathMuxGetFrequency (uint32_t clkPath)
	Returns the output frequency of the clock path mux. More...

uint32_t	Cy_SysClk_ClkPathGetFrequency (uint32_t clkPath)
	Returns the output frequency of the clock path mux. More...

Function Documentation

cy_en_sysclk_status_t Cy_SysClk_ClkPathSetSource	(	uint32_t	clkPath,
		cy_en_clkpath_in_sources_t	source
	)

Configures the source for the specified clock path.

Parameters

clkPath	Selects which clock path to configure; 0 is the first clock path, which is the FLL.
source	cy_en_clkpath_in_sources_t

Returns: cy_en_sysclk_status_t CY_PRA_STATUS_* - For the PSoC 64 devices there are possible situations when function returns the PRA error status code cy_en_pra_status_t instead of cy_en_sysclk_status_t. This is because for PSoC 64 devices the function uses the PRA driver to change the protected registers. Refer to cy_en_pra_status_t for more details.

Note: If calling this function changes an FLL or PLL input frequency, disable the FLL or PLL before calling this function. After calling this function, call the FLL or PLL configure function, for example Cy_SysClk_FllConfigure().; Call SystemCoreClockUpdate after this function calling if it affects the CLK_HF0 frequency.; Call Cy_SysLib_SetWaitStates before calling this function if it affects the CLK_HF0 frequency and the frequency is increasing.; Call Cy_SysLib_SetWaitStates after calling this function if it affects the CLK_HF0 frequency and the frequency is decreasing.

Function Usage: /* Scenario: ECO needs to source HFCLK2 through Path 2. The ECO is
configured through its function calls. */
#define CLKPATH2 (2UL)
#define HFCLK2 (2UL)
uint32_t clkPathMuxFreq = 0UL; /* Variable to store the Clock Path Mux output frequency */
/* Set the clock path 2 mux to be sourced from ECO */
if(CY_SYSCLK_SUCCESS == Cy_SysClk_ClkPathSetSource(CLKPATH2, CY_SYSCLK_CLKPATH_IN_ECO))
{
clkPathMuxFreq = Cy_SysClk_ClkPathMuxGetFrequency(CLKPATH2);
/* Now clkPathMuxFreq contains the Clock Path Mux output frequency */
}
else
{
/* Perform error handling */
}
/* Set the HFCLK2 source to clock path 2 and enable HFCLK2 */
(void)Cy_SysClk_ClkHfSetSource(HFCLK2, CY_SYSCLK_CLKHF_IN_CLKPATH2);
/* Enable HFCLK2 */
(void)Cy_SysClk_ClkHfEnable(HFCLK2);

Note: Take into account the possible platform specific clkHf (and further clocking chain links) frequency limitations while using this API.; It takes four cycles of the originally selected clock to switch away from it. Do not disable the original clock during this time.

cy_en_clkpath_in_sources_t Cy_SysClk_ClkPathGetSource ( uint32_t clkPath )

Reports which source is selected for the path mux.

Parameters

clkPath Selects which clock path to report; 0 is the first clock path, which is the FLL.

Function Usage: /* Scenario: A peripheral derived off of Path 1 clock is not clocking at the
expected frequency and accuracy. Need to confirm that the source
of the Path 1 mux is the ECO. */
/* Get the source of the clock path 1 mux */
if(CY_SYSCLK_CLKPATH_IN_ECO != Cy_SysClk_ClkPathGetSource(1UL))
{
/* Insert error handling */
}

uint32_t Cy_SysClk_ClkPathMuxGetFrequency ( uint32_t clkPath )

Returns the output frequency of the clock path mux.

Note

If the return value equals zero, that means either:

the selected path mux source signal frequency is unknown (e.g. dsi_out, etc.) or
the selected path mux source is not configured/enabled/stable (e.g. ECO, EXTCLK, etc.).

Function Usage: /* Scenario: ECO needs to source HFCLK2 through Path 2. The ECO is
configured through its function calls. */
#define CLKPATH2 (2UL)
#define HFCLK2 (2UL)
uint32_t clkPathMuxFreq = 0UL; /* Variable to store the Clock Path Mux output frequency */
/* Set the clock path 2 mux to be sourced from ECO */
if(CY_SYSCLK_SUCCESS == Cy_SysClk_ClkPathSetSource(CLKPATH2, CY_SYSCLK_CLKPATH_IN_ECO))
{
clkPathMuxFreq = Cy_SysClk_ClkPathMuxGetFrequency(CLKPATH2);
/* Now clkPathMuxFreq contains the Clock Path Mux output frequency */
}
else
{
/* Perform error handling */
}
/* Set the HFCLK2 source to clock path 2 and enable HFCLK2 */
(void)Cy_SysClk_ClkHfSetSource(HFCLK2, CY_SYSCLK_CLKHF_IN_CLKPATH2);
/* Enable HFCLK2 */
(void)Cy_SysClk_ClkHfEnable(HFCLK2);

uint32_t Cy_SysClk_ClkPathGetFrequency ( uint32_t clkPath )

Returns the output frequency of the clock path mux.

Note

If the return value equals zero, that means either:

the selected path mux source signal frequency is unknown (e.g. dsi_out, etc.) or
the selected path mux source is not configured/enabled/stable (e.g. ECO, EXTCLK, etc.).

Function Usage: /* Scenario: FLL is configured and needs to be enabled within 2 ms */
#define CLKPATH0 (0UL)
uint32_t clkPathFreq = 0UL; /* Variable to store the Clock Path output frequency */
/* Enable the FLL with a timeout of 2000 microseconds */
if (CY_SYSCLK_SUCCESS == Cy_SysClk_FllEnable(2000UL))
{
clkPathFreq = Cy_SysClk_ClkPathGetFrequency(CLKPATH0);
/* Now clkPathFreq contains an actual FLL frequency */
}
else
{
/* Insert error handling */
}