MTB CAT1 Peripheral driver library

General Description

This driver provides API functions to configure the Comparator Slope Generator within High Power Programmable Analog Sub-System.

The CSG is a flexible block which compares a 10-bit DAC value with a selected analog input signal or compares two analog inputs. The output of this block is the 1-bit digital compare value that can be used for controlling the behavior of the TCPWM in a motor control, power conversion and other applications.

The CSG block contains 5 CSG slices (for PSOC C3 devices), each of which can be configured and used independently. Each slice contains a DAC and a comparator with the dedicated control logic. The internal structure and external HW interface of the CSG slice are shown below.

hppass_csg_slice.png

DAC

The user has various options to control the DAC data:

DAC data update can be triggered by either a HW or FW trigger. Available HW DAC trigger sources:

Comparator

The Comparator can be configured to compare a signal from the dedicated analog input or from the DAC output to another selected analog input.

The CSG comparator output signal has the following post-processing options:

CSG Configuration

To configure the CSG, the driver uses a configuration structure of type cy_stc_hppass_csg_t that must be predefined. This structure holds the pointer to the array of CSG slices configuration structures cy_stc_hppass_slice_t, as well the pointer to the array of the CSG LUT configuration structures cy_stc_hppass_lut_t. Also, this structure contains the DAC output selector field cy_en_hppass_dac_out_t, which routes the selected DAC output to the HPPASS SAR input for debugging purposes.

Note
The total number of LUTs is 2 for the PSOC C3 devices, but the same LUT can be used by multiple CSG slices. LUT 0 can be used by CSG slices 0, 1, and 2; LUT 1 by slices 3 and 4.

Each instance of the cy_stc_hppass_slice_t contains the comparator configuration structure cy_stc_hppass_comp_t and the DAC configuration structure cy_stc_hppass_dac_t.

Refer to the Technical Reference Manual for detailed information.

Code Snippets

CSG Analog to PWM conversion

The example below shows how to configure the CSG slice to generate PWM signal on P7_0 with the duty cycle proportional to the analog input voltage on the AN_A0 pin.

{
/* Comparator configuration */
.comp =
{
.pos = CY_HPPASS_COMP_POS_A, /* Positive comparator input - input A (AN_A0 for CSG 0) */
.neg = CY_HPPASS_COMP_NEG_DAC, /* Negative comparator input - DAC output */
.blank = CY_HPPASS_COMP_BLANK_DISABLED, /* No comparator blanking */
.trig = CY_HPPASS_COMP_TRIG_DISABLED, /* No comparator blanking trigger */
.edge = CY_HPPASS_COMP_EDGE_DISABLED, /* No comparator event generation */
.invert = false, /* No output inversion */
},
/* DAC configuration */
.dac =
{
.start = CY_HPPASS_DAC_START_DISABLED, /* Software DAC start */
.update = CY_HPPASS_DAC_UPDATE_PERIOD_TC, /* Update DAC on period terminal count */
.mode = CY_HPPASS_DAC_MODE_SLOPE_RISING, /* Generate rising slope */
.continuous = true, /* Generate slope continuously */
.skipTrig = false, /* Only for HW triggers */
.cascade = false, /* No cascade sync */
.paramSync = false, /* No DAC parameter sync */
.stepSize = 1U, /* DAC step size = 1 */
.deGlitch = 0U, /* No DAC deglitch */
.valBuffA = 0U, /* Slope min value */
.valBuffB = 1023U, /* Slope max value */
.period = /* DAC update frequency is 1024 kHz (for CSG clock = 120 MHz) */
{
.frac = 23U,
.intg = 11U,
},
}
};
Note
The cy_stc_hppass_slice_t::dac::period field is calculated to update the DAC at the frequency of 10240 kHz for CSG clock = 120 MHz. For the the 1024 rising slope values (0 to 1023), the slope period will be 10240 kHz / 1024 = 10 kHz. The HPPASS CSG Slice Personality in the Device Configurator includes the calculator for the DAC period value.
{
.slice = {&slice0Cfg, NULL, NULL, NULL, NULL}, /* Initialize only slice 0 */
.dacOut = 0U, /* Do not use DAC Output and LUT features */
.lut = {NULL, NULL}
};
const cy_stc_hppass_ac_stt_t stateTransitionTable[MY_HPPASS_STT_NUM_ENTRIES] =
{
{ /* STATE0: Initialize CSG Slice 0 and stop the AC */
.branchStateIdx = 0U,
.interrupt = false,
.count = 1U,
.gpioOutUnlock = false,
.gpioOutMsk = 0U,
.csgUnlock = {true, false, false, false, false}, /* Unlock only CSG Slice 0 */
.csgEnable = {true, false, false, false, false}, /* Enable only CSG Slice 0 */
.csgDacTrig = {false, false, false, false, false},
.sarUnlock = false,
.sarEnable = false,
.sarGrpMsk = 0U,
.sarMux = {{0}, {0}, {0}, {0}}
}
};
const cy_stc_hppass_cfg_t hppassCfg =
{
.ac =
{
.sttEntriesNum = MY_HPPASS_STT_NUM_ENTRIES,
.stt = stateTransitionTable,
.gpioOutEnMsk = 0U,
.startupClkDiv = 24U,
.startup =
{
{
.count = 200U,
.sar = true,
.csgChan = true,
.csgSlice = false,
.csgReady = false,
},
{
.count = 50U,
.sar = false,
.csgChan = false,
.csgSlice = true,
.csgReady = false,
},
{
.count = 1U,
.sar = false,
.csgChan = false,
.csgSlice = false,
.csgReady = true,
},
{
.count = 0U,
.sar = false,
.csgChan = false,
.csgSlice = false,
.csgReady = false,
},
},
},
.csg = &csgCfg,
.sar = NULL,
.trigIn = {{0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}},
.trigLevel =
{
{
.syncBypass = false,
.compMsk = CY_HPPASS_TRIG_CMP_0, /* Use Trigger 0 to connect CSG Comparator 0 singal to GPIO */
.limitMsk = CY_HPPASS_DEINIT
},
{0}, {0}, {0}, {0}, {0}, {0}, {0}
}
};
Note
Only usage of the startup parameters recommended by the vendor guarantees the reliable operation of the Autonomous Controller.
Please use the Device Configurator tool to make configurations or refer to the Technical Reference Manual for detailed information.

API Reference

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