| Enumerator |
|---|
| CY_HPPASS_CONDITION_FALSE | Hardcoded FALSE value.
|
| CY_HPPASS_CONDITION_TRUE | Hardcoded TRUE value.
|
| CY_HPPASS_CONDITION_BLOCK_READY | Enabled SAR, CSG block(s) are ready for use.
When this option is used in conjunction with ACTION = CY_HPPASS_ACTION_WAIT_FOR, AC will stay in current state, until enabled block(s) are ready for use, and then go to the next state.
|
| CY_HPPASS_CONDITION_CNT_DONE | Runout for an interval timer if the ACTION is WAIT_FOR or runout for a loop counter, if the ACTION is BRANCH IF.
|
| CY_HPPASS_CONDITION_SAR_GROUP_0_DONE | SAR Sequencer Group 0 DONE.
|
| CY_HPPASS_CONDITION_SAR_GROUP_1_DONE | SAR Sequencer Group 1 DONE.
|
| CY_HPPASS_CONDITION_SAR_GROUP_2_DONE | SAR Sequencer Group 2 DONE.
|
| CY_HPPASS_CONDITION_SAR_GROUP_3_DONE | SAR Sequencer Group 3 DONE.
|
| CY_HPPASS_CONDITION_SAR_GROUP_4_DONE | SAR Sequencer Group 4 DONE.
|
| CY_HPPASS_CONDITION_SAR_GROUP_5_DONE | SAR Sequencer Group 5 DONE.
|
| CY_HPPASS_CONDITION_SAR_GROUP_6_DONE | SAR Sequencer Group 6 DONE.
|
| CY_HPPASS_CONDITION_SAR_GROUP_7_DONE | SAR Sequencer Group 7 DONE.
|
| CY_HPPASS_CONDITION_SAR_LIMIT_0 | SAR Limit Crossing Detector 0.
|
| CY_HPPASS_CONDITION_SAR_LIMIT_1 | SAR Limit Crossing Detector 1.
|
| CY_HPPASS_CONDITION_SAR_LIMIT_2 | SAR Limit Crossing Detector 2.
|
| CY_HPPASS_CONDITION_SAR_LIMIT_3 | SAR Limit Crossing Detector 3.
|
| CY_HPPASS_CONDITION_SAR_LIMIT_4 | SAR Limit Crossing Detector 4.
|
| CY_HPPASS_CONDITION_SAR_LIMIT_5 | SAR Limit Crossing Detector 5.
|
| CY_HPPASS_CONDITION_SAR_LIMIT_6 | SAR Limit Crossing Detector 6.
|
| CY_HPPASS_CONDITION_SAR_LIMIT_7 | SAR Limit Crossing Detector 7.
|
| CY_HPPASS_CONDITION_SAR_BUSY | SAR Busy status.
|
| CY_HPPASS_CONDITION_SAR_FIR_0_DONE | SAR FIR0 result done.
|
| CY_HPPASS_CONDITION_SAR_FIR_1_DONE | SAR FIR1 result done.
|
| CY_HPPASS_CONDITION_SAR_QUEUE_HI_EMPTY | SAR Sequencer Hi Priority Queue is empty.
|
| CY_HPPASS_CONDITION_SAR_QUEUE_LO_EMPTY | SAR Sequencer Low Priority Queue is empty.
|
| CY_HPPASS_CONDITION_SAR_QUEUES_EMPTY | SAR Sequencer both Queues are empty.
|
| CY_HPPASS_CONDITION_TRIG_0 | HW/FW Trigger 0.
|
| CY_HPPASS_CONDITION_TRIG_1 | HW/FW Trigger 1.
|
| CY_HPPASS_CONDITION_TRIG_2 | HW/FW Trigger 2.
|
| CY_HPPASS_CONDITION_TRIG_3 | HW/FW Trigger 3.
|
| CY_HPPASS_CONDITION_TRIG_4 | HW/FW Trigger 4.
|
| CY_HPPASS_CONDITION_TRIG_5 | HW/FW Trigger 5.
|
| CY_HPPASS_CONDITION_TRIG_6 | HW/FW Trigger 6.
|
| CY_HPPASS_CONDITION_TRIG_7 | HW/FW Trigger 7.
|
| CY_HPPASS_CONDITION_FIFO_0_LEVEL | FIFO Level 0 trigger.
|
| CY_HPPASS_CONDITION_FIFO_1_LEVEL | FIFO Level 1 trigger.
|
| CY_HPPASS_CONDITION_FIFO_2_LEVEL | FIFO Level 2 trigger.
|
| CY_HPPASS_CONDITION_FIFO_3_LEVEL | FIFO Level 3 trigger.
|
| CY_HPPASS_CONDITION_CSG_0_DAC_DONE | CSG0 DAC Slope/LUT waveform Done.
|
| CY_HPPASS_CONDITION_CSG_1_DAC_DONE | CSG1 Slope/LUT waveform Done.
|
| CY_HPPASS_CONDITION_CSG_2_DAC_DONE | CSG2 Slope/LUT waveform Done.
|
| CY_HPPASS_CONDITION_CSG_3_DAC_DONE | CSG3 Slope/LUT waveform Done.
|
| CY_HPPASS_CONDITION_CSG_4_DAC_DONE | CSG4 Slope/LUT waveform Done.
|
| CY_HPPASS_CONDITION_CSG_0_COMP | CSG0 Comparator Trip.
|
| CY_HPPASS_CONDITION_CSG_1_COMP | CSG1 Comparator Trip.
|
| CY_HPPASS_CONDITION_CSG_2_COMP | CSG2 Comparator Trip.
|
| CY_HPPASS_CONDITION_CSG_3_COMP | CSG3 Comparator Trip.
|
| CY_HPPASS_CONDITION_CSG_4_COMP | CSG4 Comparator Trip.
|
