Description

The DAC configuration structure.

Data Fields
cy_en_hppass_dac_start_t	start
	DAC trigger start. More...

cy_en_hppass_dac_update_t	update
	DAC trigger update. More...

cy_en_hppass_dac_mode_t	mode
	DAC mode.

bool	continuous
	Continuous mode. More...

bool	skipTrig
	Skip the first DAC hardware update trigger after the proper cy_stc_hppass_dac_t::mode is enabled.

bool	cascade
	Synchronize parameter update with previous CSG slice in the case of multi-phase operation.

bool	paramSync
	Parameter Synchronization enable. More...

uint8_t	deGlitch
	DAC de-glitch time in clock cycles. More...

uint8_t	stepSize
	Static value of 6 bit DAC Step Size. More...

uint16_t	valBuffA
	DAC A value, usage depends on cy_stc_hppass_dac_t::mode. More...

uint16_t	valBuffB
	DAC B value, usage depends on cy_stc_hppass_dac_t::mode. More...

cy_stc_hppass_dac_period_t	period
	DAC Period divider, clocked from CSG clock.

Field Documentation

◆ start

cy_en_hppass_dac_start_t cy_stc_hppass_dac_t::start

DAC trigger start.

If input trigger is selected, it should be in the pulse mode.

◆ update

cy_en_hppass_dac_update_t cy_stc_hppass_dac_t::update

DAC trigger update.

If input trigger is selected, it should be in the pulse mode

◆ continuous

bool cy_stc_hppass_dac_t::continuous

Continuous mode.

(Only valid for Slope and LUT modes)

◆ paramSync

bool cy_stc_hppass_dac_t::paramSync

Parameter Synchronization enable.

If set, the DAC parameters will be set only after Cy_HPPASS_DAC_SetParamSyncReady function call

◆ deGlitch

uint8_t cy_stc_hppass_dac_t::deGlitch

DAC de-glitch time in clock cycles.

Valid range 0..7 (0 means de-glitching is disabled, 1..7 - de-glitching period in cycles). The de-glitch period should be not grater than the DAC update period.

◆ stepSize

uint8_t cy_stc_hppass_dac_t::stepSize

Static value of 6 bit DAC Step Size.

Valid range: 1..64

◆ valBuffA

uint16_t cy_stc_hppass_dac_t::valBuffA

DAC A value, usage depends on cy_stc_hppass_dac_t::mode.

Buffered mode - DAC value
Hysteretic Buffered mode - DAC high threshold
Slope modes - DAC start value
LUT modes - LUT start address

◆ valBuffB

uint16_t cy_stc_hppass_dac_t::valBuffB

DAC B value, usage depends on cy_stc_hppass_dac_t::mode.

Buffered mode - DAC value
Hysteretic Buffered mode - DAC low threshold
Slope modes - DAC stop value
LUT modes - LUT stop address