Functions

General Description

Functions
cy_en_trigmux_status_t	Cy_TrigMux_Connect (uint32_t inTrig, uint32_t outTrig, bool invert, en_trig_type_t trigType)
	Connects an input trigger source and output trigger. More...
cy_en_trigmux_status_t	Cy_TrigMux_Select (uint32_t outTrig, bool invert, en_trig_type_t trigType)
	Enables and configures the specified 1-to-1 trigger line. More...
cy_en_trigmux_status_t	Cy_TrigMux_Deselect (uint32_t outTrig)
	Disables the specified 1-to-1 trigger line. More...
cy_en_trigmux_status_t	Cy_TrigMux_SetDebugFreeze (uint32_t outTrig, bool enable)
	Enables/disables the Debug Freeze feature for the specified trigger multiplexer or 1-to-1 trigger line. More...

Function Documentation

Cy_TrigMux_Connect()

cy_en_trigmux_status_t Cy_TrigMux_Connect	(	uint32_t	inTrig,
		uint32_t	outTrig,
		bool	invert,
		en_trig_type_t	trigType
	)

Connects an input trigger source and output trigger.

Parameters

inTrig	An input selection for the trigger mux. Bit 30 should be cleared. Bit 12 should be cleared. Bits 11:8 represent the trigger group selection. Bits 7:0 select the input trigger signal for the specified trigger multiplexer.
outTrig	The output of the trigger mux. This refers to the consumer of the trigger mux. Bit 30 should be set. Bit 12 should be cleared. Bits 11:8 represent the trigger group selection. For PERI_ver1: Bits 6:0 select the output trigger number in the trigger group. For PERI_ver2: Bits 7:0 select the output trigger number in the trigger group.
invert	true: The output trigger is inverted. false: The output trigger is not inverted.
trigType	The trigger signal type. TRIGGER_TYPE_EDGE: The trigger is synchronized to the consumer blocks clock and a two-cycle pulse is generated on this clock. TRIGGER_TYPE_LEVEL: The trigger is a simple level output.

Returns

status:

• CY_TRIGMUX_SUCCESS: The connection is made successfully.
• CY_TRIGMUX_BAD_PARAM: Some parameter is invalid.

Function Usage

    
    /* Scenario: Setup a trigger multiplexer connection from TCPWM0 counter 0 overflow output to DataWire 0 channel 0 trigger input.
     * Also for trigger signal evidence setup two additional trigger multiplexer connections:
     * - from the same TCPWM0 counter 0 overflow output to HSIOM trigger IO output 0 (GPIO port 0.4)
     * - from the DataWire 0 channel 0 trigger output to HSIOM trigger IO output 1 (GPIO port 0.5)
     */
#if (CY_IP_MXPERI_VERSION == 1U)
    (void)Cy_TrigMux_Connect(TRIG11_IN_TCPWM0_TR_OVERFLOW0, TRIG11_OUT_TR_GROUP0_INPUT9, false, TRIGGER_TYPE_LEVEL);
    (void)Cy_TrigMux_Connect(TRIG0_IN_TR_GROUP11_OUTPUT0, TRIG0_OUT_CPUSS_DW0_TR_IN0, false, TRIGGER_TYPE_EDGE);

    (void)Cy_TrigMux_Connect(TRIG11_IN_TCPWM0_TR_OVERFLOW0, TRIG11_OUT_TR_GROUP8_INPUT9, false, TRIGGER_TYPE_LEVEL);
    (void)Cy_TrigMux_Connect(TRIG8_IN_TR_GROUP11_OUTPUT0, TRIG8_OUT_PERI_TR_IO_OUTPUT0, false, TRIGGER_TYPE_EDGE);

    (void)Cy_TrigMux_Connect(TRIG10_IN_CPUSS_DW0_TR_OUT0, TRIG10_OUT_TR_GROUP8_INPUT1, false, TRIGGER_TYPE_LEVEL);
    (void)Cy_TrigMux_Connect(TRIG8_IN_TR_GROUP10_OUTPUT0, TRIG8_OUT_PERI_TR_IO_OUTPUT1, false, TRIGGER_TYPE_EDGE);
#else /* CY_IP_MXPERI_VERSION > 1 */
    (void)Cy_TrigMux_Connect(TRIG_IN_MUX_0_TCPWM0_TR_OVERFLOW0, TRIG_OUT_MUX_0_PDMA0_TR_IN0, false, TRIGGER_TYPE_EDGE);
    (void)Cy_TrigMux_Connect(TRIG_IN_MUX_4_TCPWM0_TR_OVERFLOW0, TRIG_OUT_MUX_4_HSIOM_TR_IO_OUTPUT0, false, TRIGGER_TYPE_EDGE);
    (void)Cy_TrigMux_Connect(TRIG_IN_MUX_4_PDMA0_TR_OUT0, TRIG_OUT_MUX_4_HSIOM_TR_IO_OUTPUT1, false, TRIGGER_TYPE_EDGE);
#endif /* CY_IP_MXPERI_VERSION */
    /* Note: the Cy_TrigMux_Connect return status is ignored here because the provided parameters are correct.
     * It is made here just to reduce the code snippet redundancy, it is not recommended to do so in the user code.
     */

    /* Now initialize the correspondent GPIO pins */
    Cy_GPIO_Pin_FastInit(GPIO_PRT0, 4UL, CY_GPIO_DM_STRONG_IN_OFF, 0UL, P0_4_PERI_TR_IO_OUTPUT0);
    Cy_GPIO_Pin_FastInit(GPIO_PRT0, 5UL, CY_GPIO_DM_STRONG_IN_OFF, 0UL, P0_5_PERI_TR_IO_OUTPUT1);
    
    /* Now the TCPWM0 counter 0 periodically triggers the DW0 channel 0 (each time when overflow event occurs).
     * Also the TCPWM and DMA output trigger signals can be observed with oscilloscope on pins P0.4 and P0.5 correspondingly.
     */
    

Cy_TrigMux_Select()

cy_en_trigmux_status_t Cy_TrigMux_Select	(	uint32_t	outTrig,
		bool	invert,
		en_trig_type_t	trigType
	)

Enables and configures the specified 1-to-1 trigger line.

For PERI_ver2 only.

Parameters

outTrig	The 1to1 trigger line. Bit 30 should be set. Bit 12 should be set. Bits 11:8 represent the 1-to-1 trigger group selection. Bits 7:0 select the trigger line number in the trigger group.
invert	true: The trigger signal is inverted. false: The trigger signal is not inverted.
trigType	The trigger signal type. TRIGGER_TYPE_EDGE: The trigger is synchronized to the consumer blocks clock and a two-cycle pulse is generated on this clock. TRIGGER_TYPE_LEVEL: The trigger is a simple level output.

Returns

status:

• CY_TRIGMUX_SUCCESS: The selection is made successfully.
• CY_TRIGMUX_BAD_PARAM: Some parameter is invalid.

Function Usage

    
    /* Scenario: Set up a 1 to 1 connection between two peripherals; in this case from SCB0 TX Trigger Output to DW0 channel 16 */
    if (CY_TRIGMUX_SUCCESS != Cy_TrigMux_Select(TRIG_OUT_1TO1_0_SCB0_TX_TO_PDMA0_TR_IN16, false, TRIGGER_TYPE_LEVEL))
    {
        /* Insert error handling */
    }

Cy_TrigMux_Deselect()

cy_en_trigmux_status_t Cy_TrigMux_Deselect

(

uint32_t

outTrig

)

Disables the specified 1-to-1 trigger line.

For PERI_ver2 only.

Parameters

outTrig

The 1to1 trigger line. Bit 30 should be set. Bit 12 should be set. Bits 11:8 represent the 1-to-1 trigger group selection. Bits 7:0 select the trigger line number in the trigger group.

Returns

status:

• CY_TRIGMUX_SUCCESS: The deselection is made successfully.
• CY_TRIGMUX_BAD_PARAM: Some parameter is invalid.

Function Usage

    
    /* Scenario: Disable a 1 to 1 connection, using SCB0 TX Trigger Output to DataWire 0 channel 16 */
    if (CY_TRIGMUX_SUCCESS != Cy_TrigMux_Deselect(TRIG_OUT_1TO1_0_SCB0_TX_TO_PDMA0_TR_IN16))
    {
        /* Insert error handling */
    }
    

Cy_TrigMux_SetDebugFreeze()

cy_en_trigmux_status_t Cy_TrigMux_SetDebugFreeze	(	uint32_t	outTrig,
		bool	enable
	)

Enables/disables the Debug Freeze feature for the specified trigger multiplexer or 1-to-1 trigger line.

For PERI_ver2 only.

Parameters

outTrig	The output of the trigger mux or dedicated 1-to-1 trigger line. Bit 30 should be set. For PERI_ver1 Bits 11:8 represent the trigger group selection. For PERI_ver2 Bits 12:8 represent the trigger group selection. Bits 7:0 select the output trigger number in the trigger group.
enable	true: The Debug Freeze feature is enabled. false: The Debug Freeze feature is disabled.

Returns

status:

• CY_TRIGMUX_SUCCESS: The operation is made successfully.
• CY_TRIGMUX_BAD_PARAM: The outTrig parameter is invalid.

Function Usage

    
    /* Scenario: Enable a Debug Freeze feature using DW0 channel 0 trigger input */
    if (CY_TRIGMUX_SUCCESS != Cy_TrigMux_SetDebugFreeze(TRIG_OUT_MUX_0_PDMA0_TR_IN0, true))
    {
        /* Insert error handling */
    }
    
    /* Now the DW0 channel 0 trigger input will be frozen when
     * the tr_dbg_freeze signal is activated.
     * Usually the tr_dbg_freeze signal is intended to be activated from
     * the cpuss.cti_tr_out[x] signal, for example:
     */
    Cy_TrigMux_Connect(TRIG_IN_MUX_7_CTI_TR_OUT0, TRIG_OUT_MUX_7_DEBUG_FREEZE_TR_IN, false, TRIGGER_TYPE_LEVEL);
    /* However it can be activated just with software triggering: */
    Cy_TrigMux_SwTrigger(TRIG_OUT_MUX_7_DEBUG_FREEZE_TR_IN, CY_TRIGGER_INFINITE);

    /* Scenario: Disable a Debug Freeze feature using DW0 channel 0 trigger input */
    if (CY_TRIGMUX_SUCCESS != Cy_TrigMux_SetDebugFreeze(TRIG_OUT_MUX_0_PDMA0_TR_IN0, false))
    {
        /* Insert error handling */
    }