SAR ADC (Successive-Approximation Register Analog to Digital Converter)

General Description

This driver provides the API functions to configure the successive approximation register analog-to-digital converter (SAR ADC) subsystem of the Autonomous Analog.

The versatile SAR ADC is an analog-to-digital converter with a dual-core 12-bit successive approximation register. The SAR ADC (hereafter ADC) contains a High Speed (HS) Core that can operate in Active mode with the SRSS clock up to 80 MHz and a Low Power (LP) Core based on the 4.096 MHz LPOSC from the Autonomous Analog. The HS Core is not available in DeepSleep while the LP Core is available in all power modes.

Note

Only one core can be active at a time.

For more information on the ADC, refer to the device Architecture Technical Reference Manual (TRM).
For the exact location of the pins, see the device datasheet.

The key components of the ADC are:

• The inputs selector for routing signals from external pins (GPIO) or analog-capable internal IOs (MUX);
• A pair of Hi-Z buffers, which are in the MUX path only and can be bypassed;
• The sampler with sample and hold circuits (S/H) for simultaneous sampling from multiple sources:
  • 8 single-ended S/H circuits directly connected to the GPIO and available in Active mode only;
  • 2 single-ended S/H circuits connected to the MUX IOs and available in Active mode only;
  • 1 fully differential sampler for all sources, available in Active and Deep Sleep modes;
• The source of reference voltages for HS/LP ADC Cores;
• Post-processing of the ADC output;

Channel Configuration

The signal path to the ADC input is controlled by the logical channel (a high-level abstraction). The configuration of the ADC logical channel includes the following settings (common for HS//LP modes):

• assign the source for the ADC input (refer to cy_en_autanalog_sar_pin_hs_t for GPIO sources and cy_en_autanalog_sar_pin_mux_t for MUX sources accordingly);
• configuration of the allowable range for the ADC (refer to cy_en_autanalog_sar_limit_t);
• signed/unsigned the format for the ADC output data (refer to Signed/Unsigned Output chapter);
• enable the averaging of the conversion result in HW;
• store the conversion result in the FIFO (refer to cy_en_autanalog_fifo_sel_t)
• correct the linearity of the channel - channel gain and offset (refer to cy_en_autanalog_sar_ch_coeff_t and Cy_AutAnalog_SAR_LoadOffsetGainCorr)

Also:

• enable the pseudo differential sampling for the single-ended ADC in HS mode (refer to cy_stc_autanalog_sar_hs_chan_t::hsDiffEn and cy_stc_autanalog_sar_seq_tab_hs_t::muxMode);

  Note

  Negative input correction coefficient is applicable only for the second channel in Pseudo Differential sampling mode

• support Single-ended mode for ADC in LP mode of operation (refer to cy_stc_autanalog_sar_sta_lp_t::lpDiffEn);
• bypass the Hi-Z buffers for MUX channels (refer to cy_stc_autanalog_sar_mux_chan_t::buffBypass)

8 individually-configurable logical channels are available to the ADC in HS mode and 16 logical channels are available to the ADC in LP mode.

The logical channels configuration is a part of the ADC Static Configuration (refer to cy_stc_autanalog_sar_sta_hs_t::hsGpioChan for GPIO inputs and cy_stc_autanalog_sar_sta_t::intMuxChan for MUX inputs accordingly).

Static Configuration

The static configuration contains application-specific settings intended to remain static for any ADC application. The Autonomous Controller (AC) will NOT change the static configuration during operation.

The diagram below shows the static configuration for ADC in HS mode.

The diagram below shows the static configuration for ADC in LP mode.

The diagram below shows the static configuration for LP ADC in Single Ended mode.

The static configuration for the whole ADC consists of static configurations for the HS and LP parts (refer to cy_stc_autanalog_sar_sta_hs_t, cy_stc_autanalog_sar_sta_lp_t) and includes the following settings in total (refer to cy_stc_autanalog_sar_sta_t):

• the reference voltage source for the HS and LP Cores of the ADC (refer to cy_stc_autanalog_sar_sta_hs_t::hsVref and cy_stc_autanalog_sar_sta_lp_t::lpVref);
• a set of sample times for the ADC input (refer to cy_stc_autanalog_sar_sta_hs_t::hsSampleTime and cy_stc_autanalog_sar_sta_lp_t::lpSampleTime);
• average mode settings (refer to cy_stc_autanalog_sar_sta_t::accMode and cy_stc_autanalog_sar_sta_t::shiftMode);
• the notification of the conversion result for the selected input of the ADC or the output of the FIR filter (refer to cy_stc_autanalog_sar_sta_hs_t::hsGpioResultMask and cy_stc_autanalog_sar_sta_t::muxResultMask for the GPIO inputs and MUX inputs accordingly or cy_stc_autanalog_sar_sta_t::firResultMask for the FIR filter output);
• a set of conditions for the allowable range of the ADC (refer to cy_stc_autanalog_sar_sta_t::limitCond);
• the presence of the logical channel ID in FIFO data (refer to cy_stc_autanalog_sar_sta_t::chanID);
• the ADC calibration during start-up (refer to cy_stc_autanalog_sar_sta_t::startupCal);

Also:

• Power mode for the Hi-Z buffers (refer to cy_stc_autanalog_sar_sta_t::posBufPwr and cy_stc_autanalog_sar_sta_t::negBufPwr);

Sequencer and State Transition Table

The sequencer is used to control the ADC to perform an automatic scan on all enabled logical channels without MCU intervention. Each ADC Core has its own sequencer, refer to cy_stc_autanalog_sar_seq_tab_hs_t for HS mode and refer to cy_stc_autanalog_sar_seq_tab_lp_t for LP mode. Both sequencers contain up to 32 states. Each state of the sequencer defines a single step in the ADC scan.

The Autonomous Controller is able to trigger the ADC. It points to a particular step (Entry State) of the sequencer in runtime using the State Transition Table, refer to cy_stc_autanalog_stt_sar_t. The next step of the sequencer is defined in the nextAction field of the sequencer configuration structure (refer to e.g. cy_stc_autanalog_sar_seq_tab_hs_t::nextAction):

• NEXT - Go to the next sequencer state to proceed to the next step in a given ADC scan;
• ENTRY_ADDR - Assert the SAR_EOS condition and jump to Entry State for continuous ADC scanning;
• STOP - Assert the SAR_DONE and SAR_EOS conditions and go to Idle to indicate the end of a scan;

The remaining fields of the sequencer are (common for HS//LP modes):

• enable and select the appropriate sample time configuration for a particular logical channel (refer to e.g. cy_stc_autanalog_sar_seq_tab_hs_t::sampleTimeEn and cy_stc_autanalog_sar_seq_tab_hs_t::sampleTime);
• enable the averaging for the ADC conversion result and define the average count (refer to e.g. cy_stc_autanalog_sar_seq_tab_hs_t::accEn and cy_stc_autanalog_sar_seq_tab_hs_t::accCount);

Also, the HS sequencer allows you to configure the following:

• enable and select specific GPIO channels, refer to cy_stc_autanalog_sar_seq_tab_hs_t::chanEn with their configurations provided in the cy_stc_autanalog_sar_sta_hs_t::hsGpioChan;
• enable and select the operation mode for specific MUX channels, refer to cy_stc_autanalog_sar_seq_tab_hs_t::muxMode. Select the configurations for the enabled MUX channels cy_stc_autanalog_sar_seq_tab_hs_t::mux0Sel, cy_stc_autanalog_sar_seq_tab_hs_t::mux1Sel provided in the cy_stc_autanalog_sar_sta_t::intMuxChan;

Also, the LP sequencer allows you to configure the following:

• enable the operation for the LP sampler cy_stc_autanalog_sar_seq_tab_lp_t::chanEn and select the configuration for the MUX channel cy_stc_autanalog_sar_seq_tab_lp_t::mux0Sel provided in the cy_stc_autanalog_sar_sta_t::intMuxChan;

The ADC scan can be started by the Autonomous Controller (AC) in runtime per settings provided in the sequencer (refer to cy_stc_autanalog_sar_seq_tab_hs_t, cy_stc_autanalog_sar_seq_tab_lp_t) and State Transition Table (refer to cy_stc_autanalog_stt_sar_t structure).

Note

When ADC is powered down, the ADC logic and FIRs are reset, ADC/FIR clocks are gated, and all ADC AC conditions are cleared. The ADC configuration and sequencer tables are retained. The FIFO status and content are not cleared, i.e. the FIFO contents can still be read if the ADC is disabled.

Clock and Throughput

The ADC in HS mode is clocked from the SRSS peripheral clock (Clk_HF9, up to 80MHz, refer to General Configuration Considerations) in chip Active mode using Peri 0 Clock Group 2 8-bit divider in the clock chain.
The ADC in LP mode is clocked from the local Low Power Oscillator (LPOSC, 4096kHz, refer to cy_en_autanalog_timer_clk_src_t) in chip Deep Sleep mode.

ADC mode	Clock source	Clock frequency, MHz	Throughput, samples/s
High Speed	Clk_HF9	80	5Msps
Low Power	LPOSC	4.096	200ksps

Sample Time

The sample time can be set separately for each HS\LP ADC Cores.

For HS mode, enable this option in the corresponding ADC sequencer, refer to cy_stc_autanalog_sar_seq_tab_hs_t::sampleTimeEn, cy_stc_autanalog_sar_seq_tab_hs_t::sampleTime. And the selection of a particular value of the acquisition time is defined in the corresponding Static configuration, refer to cy_stc_autanalog_sar_sta_hs_t::hsSampleTime.

For LP mode, enable this option in the corresponding ADC sequencer, refer to cy_stc_autanalog_sar_seq_tab_lp_t::sampleTimeEn, cy_stc_autanalog_sar_seq_tab_lp_t::sampleTime. The selection of a particular value of the acquisition time is defined in the corresponding Static configuration, refer to cy_stc_autanalog_sar_sta_lp_t::lpSampleTime.

Note

15us is the recommended sampling time for Die temperature measurement in LP mode.

12us is the recommended sampling time for Die temperature measurement in HS mode.

Reference Voltage

The level of the reference voltage can be defined separately for each HS\LP ADC Cores in the corresponding parts of the Static configuration, refer to cy_stc_autanalog_sar_sta_hs_t::hsVref and cy_stc_autanalog_sar_sta_lp_t::lpVref.

For the PRB configuration settings, refer to cy_stc_autanalog_prb_t structure.

Note

Vdda is 1.8V and Vbgr is 0.9V

Buffer Input and Output Ranges

The input range of the buffer can be rail-to-rail if the charge pump is enabled. Without the charge pump, the input range is 0 V to VDDA - 1.5 V. The output range of the buffer is typically 0.2 V to VDDA - 1.0 V. See the device datasheet for more details.

Charge Pump	Input Range	Output Range
Enabled	0 V to VDDA	0.2 V to VDDA - 0.2 V
Disabled	0 V to VDDA - 1.5 V	0.2 V to VDDA - 1.0 V

Note

The charge pump nominal clock is 4MHz

For the configuration settings, see cy_en_autanalog_sar_buf_pwr_t.

Signed/Unsigned Output

The ADC conversion result and the FIR//FIFO output are represented as 32-bit width integer, (zero or sign extended) regardless of the actual resolution of the ADC.

For the configuration settings, refer to cy_stc_autanalog_sar_hs_chan_t::sign and cy_stc_autanalog_sar_mux_chan_t::sign.

Handling of the Result

The results of the ADC conversion or FIR filtering can be stored with further notification about update, or sent directly to the FIFO buffer. To save the result for a specific logical channel or FIR filter, use the following settings in the Static configuration:

• GPIO channels result mask, refer to cy_stc_autanalog_sar_sta_hs_t::hsGpioResultMask;
• MUX channels result mask, refer to cy_stc_autanalog_sar_sta_t::muxResultMask;
• FIR filters result mask, refer to cy_stc_autanalog_sar_sta_t::firResultMask;

Averaging

The ADC subsystem includes an accumulator and shift registers to support the averaging at the hardware level.

To configure the averaging for the ADC conversion result, use:

• enable the averaging (applies to all channels enabled in the sequencer) in the sequencer configuration (refer e.g. to cy_stc_autanalog_sar_seq_tab_hs_t::accEn);
• enable and select Averaging mode in the Static configuration (refer to cy_stc_autanalog_sar_sta_t::accMode)
  • ACCUNDUMP - the enabled channels will be sampled, converted, and accumulated back to back. After e.g. cy_stc_autanalog_sar_seq_tab_hs_t::accCount times, the accumulated results for each enabled channels are optionally shifted (refer to e.g. cy_stc_autanalog_sar_hs_chan_t::accShift);
• define the average count in the sequencer configuration (refer to e.g. cy_stc_autanalog_sar_seq_tab_hs_t::accCount);
• enable the averaging execution in HW (refer to e.g. cy_stc_autanalog_sar_hs_chan_t::accShift);
• define the mode of the average shift (result resolution) if the averaging is carried out by the HW (refer to cy_stc_autanalog_sar_sta_t::shiftMode):
  • TWELVE - after the last accumulation, the result is shifted back to 12 bits;
  • SIXTEEN - after the last accumulation, if the average count >= 32, the result will be shifted back to 16-bits, if the average count < 32, no shift will be done as the result is already guaranteed to fit in 16 bits.

FIR Filter

Two instances of the 64-tap FIR filters are available for the ADC post-processing.

The FIR filter configuration (refer to cy_stc_autanalog_sar_fir_cfg_t) includes:

• the source for the FIR filter input defined in cy_en_autanalog_sar_fir_channel_t;
• the FIR filter order, refer to cy_stc_autanalog_sar_fir_cfg_t::tapSel;
• the array of FIR filter coefficients, refer to cy_stc_autanalog_sar_fir_cfg_t::coeff.
  The coefficient values may range from -1 + 1/2^15 to 1 - 1/2^15, with a resolution of 1/2^15.
  The coefficient uses the two-complement notation and the decimal point is fixed to the right of the most significant bit.
  Example: -0.25 = 0xE000 and 0.25 = 0x2000
• the FIR filter output scaling, refer to cy_stc_autanalog_sar_fir_cfg_t::shiftSel;
• the FIR filter output init delay, refer to cy_stc_autanalog_sar_fir_cfg_t::waitTapInit;
• routing the FIR filter output to the FIFO, refer to cy_stc_autanalog_sar_fir_cfg_t::fifoSel;
• range detection, refer to refer to cy_stc_autanalog_sar_fir_cfg_t::firLimit;

Interrupts, Triggers and STT Events

The following internal events of the ADC can be configured to generate an interrupt or trigger or used as the STT event in the Autonomous Analog (refer to cy_en_autanalog_ac_out_trigger_mask_t and cy_en_autanalog_stt_ac_condition_t):

• SAR_EOS - Indicates the end of the scanning of the logical ADC channels by the sequencer;
• SAR_RESULT (interrupt only) - Indicates an updated ADC conversion result;
• SAR_DONE - Indicates that the sequencer stopped scanning the ADC;
• SAR_RANGE - Indicates range detection conditions;
• SAR_FIR_RESULT (interrupt only) - Indicates an updated FIR filter calculation result;
• SAR_BUSY (STT event only) - Indicates that the ADC is in conversion;
• SAR_FIR_DONE (STT event only) - Indicates an updated FIR filter result;
• SAR_FIFO_DONE (STT event only) - Indicates SAR_DONE ANDED with FIFO writing complete;
• SAR_FIR_FIFO_DONE (STT event only) - Indicates that the FIR filter result is sent to the FIFO;

Refer to Interrupts, Triggers and STT Events chapter for the FIFO events.

Sample use case: Die Temperature

 
/* Scenario 1:
 * This example illustrates the use of the SAR ADC to measure the chip temperature in High speed mode.
 */
 

 
#include "autanalog_sar.h"
 

 
/* Define the index for the ADC0 instance within the Autonomous Analog */
#define ADC0IDX                                                   (0U)
 

/* The GPIO channels are NOT USED */
 

 
/* The MUX channels configuration structure */
static cy_stc_autanalog_sar_mux_chan_t intMuxChan0 =
{
    .posPin     = CY_AUTANALOG_SAR_PIN_MUX_TEMP_SENSOR,           // The temperature sensor in differential connection
    .sign       = true,                                           // Signed result is used for die temperature
    .posCoeff   = CY_AUTANALOG_SAR_CH_COEFF_DISABLED,             // The correction coefficient is not used
    .negPin     = CY_AUTANALOG_SAR_PIN_MUX_TEMP_SENSOR,           // The temperature sensor in differential connection
    .buffBypass = true,                                           // The output of the temperature sensor is bypassed
    .accShift   = false,                                          // The averaging is not used
    .negCoeff   = CY_AUTANALOG_SAR_CH_COEFF_DISABLED,             // The correction coefficient is not used
    .muxLimit   = CY_AUTANALOG_SAR_LIMIT_STATUS_DISABLED,         // The range is not checked
    .fifoSel    = CY_AUTANALOG_FIFO_DISABLED,                     // FIFO is not used
};
 

 
/* The HS mode static configuration structure */
static cy_stc_autanalog_sar_sta_hs_t sarStaHsCfg =
{
    .hsVref           = CY_AUTANALOG_SAR_VREF_VBGR,               // Vbgr is used as a reference voltage
    .hsSampleTime     = {1023U, 0U, 0U, 0U},                      // Define recommended sample time: (1/80MHz) * 1024 = 12us
    .hsGpioChan       = {NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL},
    .hsGpioResultMask = CY_AUTANALOG_SAR_CHAN_MASK_GPIO_DISABLED, // Not used
};
 

 
/* Compleate static configuration structure */
static cy_stc_autanalog_sar_sta_t sarStaCfg =
{
    .lpStaCfg      = NULL,
    .hsStaCfg      = &sarStaHsCfg,
    .posBufPwr     = CY_AUTANALOG_SAR_BUF_PWR_OFF,                // The temperature sensor output is unbuffered
    .negBufPwr     = CY_AUTANALOG_SAR_BUF_PWR_OFF,                // The temperature sensor output is unbuffered
    .accMode       = CY_AUTANALOG_SAR_ACC_DISABLED,               // The temperature sensor value is not averaged
    .startupCal    = CY_AUTANALOG_SAR_CAL_DISABLED,               // Not used
    .chanID        = false,                                       // Not used
    .shiftMode     = false,                                       // The temperature sensor value is not averaged
    .intMuxChan    = {&intMuxChan0, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL},
    .limitCond     = {NULL, NULL, NULL, NULL},                    // The range is not checked
    .muxResultMask = CY_AUTANALOG_SAR_CHAN_MASK_MUX0,             // The conversion result is stored for MUX channel #0
    .firResultMask = CY_AUTANALOG_SAR_MASK_FIR_DISABLED,          // Not used
};
 

 
/* The HS sequencer configuration structure */
static cy_stc_autanalog_sar_seq_tab_hs_t sarHsSeqTabCfg =
{
    .chanEn       = CY_AUTANALOG_SAR_CHAN_MASK_GPIO_DISABLED,     // Not used
    .muxMode      = CY_AUTANALOG_SAR_CHAN_CFG_MUX0_PSEUDO_DIFF,   // Enable MUX channel #0 in the pseudo differential configuration
    .mux0Sel      = CY_AUTANALOG_SAR_CHAN_CFG_MUX0,               // Enable MUX channel #0
    .mux1Sel      = CY_AUTANALOG_SAR_CHAN_CFG_MUX0,               // Enable MUX channel #0
    .sampleTimeEn = true,                                         // Enable the sample time for the temperature sensor
    .sampleTime   = CY_AUTANALOG_SAR_SAMPLE_TIME0,                // Use the sample time from cy_stc_autanalog_sar_sta_hs_t::hsSampleTime
    .accEn        = false,                                        // The temperature sensor value is not averaged
    .accCount     = CY_AUTANALOG_SAR_ACC_CNT2,                    // The temperature sensor value is not averaged
    .calReq       = CY_AUTANALOG_SAR_CAL_DISABLED,                // Not used
    .nextAction   = CY_AUTANALOG_SAR_NEXT_ACTION_STATE_STOP,      // The ADC mode of operation is single scan
};
 

 
/* The ADC configuration structure */
cy_stc_autanalog_sar_t sarCfg =
{
    .sarStaCfg   = &sarStaCfg,
 
    .hsSeqTabNum = 1U,                                            // The ADC LP Core sequencer contains one state
    .hsSeqTabArr = &sarHsSeqTabCfg,
 
    .lpSeqTabNum = 0U,                                            // The ADC LP Core sequencer is not used but is mandatory
    .lpSeqTabArr = NULL,
 
    .firNum      = 0U,                                            // The FIR filtering is not used
    .firCfg      = NULL,
 
    .fifoCfg     = NULL,                                          // The FIFO buffer is not used
};
 

 
/* The ADC State Transition Table */
cy_stc_autanalog_stt_sar_t sarStt[] =
{
    /* State#0, start-up/settling delay */
    {
        .unlock     = true,
        .enable     = true,
        .trigger    = false,
        .entryState = 0U,
    },
    /* State#1, wait for external trigger to start conversion */
    {
        .unlock     = true,
        .enable     = true,
        .trigger    = false,
        .entryState = 0U,
    },
    /* State#2, temperature measurement (ADC conversion) */
    {
        .unlock     = true,
        .enable     = true,
        .trigger    = true,                                       // Trigger is active
        .entryState = 0U,                                         // Sequencer Entry State value
    },
    /* State#3, return to state #1 */
    {
        .unlock     = true,
        .enable     = true,
        .trigger    = false,
        .entryState = 0U,
    },
};
 

 
    cy_en_autanalog_status_t status;
 

 
    status = Cy_AutAnalog_SAR_LoadConfig(ADC0IDX, &sarCfg);
    if (CY_AUTANALOG_SUCCESS != status)
    {
        /* Error handling */
    }
 

Warning

The first reading of the die temperature in HS mode may be incorrect.

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