General Description

Data Structures
struct	cy_stc_autanalog_sar_limit_t
	The channel range detection configuration structure. More...

struct	cy_stc_autanalog_sar_hs_chan_t
	The GPIO channel configuration structure, refer to Channel Configuration chapter. More...

struct	cy_stc_autanalog_sar_mux_chan_t
	The MUX channel configuration structure, refer to Channel Configuration chapter. More...

struct	cy_stc_autanalog_sar_sta_hs_t
	The part of the Static configuration for ADC HS mode, refer to Static Configuration chapter. More...

struct	cy_stc_autanalog_sar_sta_lp_t
	The part of the Static configuration for ADC LP mode, refer to Static Configuration chapter. More...

struct	cy_stc_autanalog_sar_sta_t
	The ADC static configuration structure, refer to Static Configuration chapter. More...

struct	cy_stc_autanalog_sar_seq_tab_hs_t
	The ADC Sequencer Table configuration structure for HS mode, refer to Sequencer and State Transition Table chapter. More...

struct	cy_stc_autanalog_sar_seq_tab_lp_t
	The ADC Sequencer Table configuration structure for LP mode, refer to Sequencer and State Transition Table chapter. More...

struct	cy_stc_autanalog_sar_fir_cfg_t
	The FIR filter configuration structure, refer to FIR Filter chapter. More...

struct	cy_stc_autanalog_sar_t
	The configuration structure to set up the entire ADC. More...

struct	cy_stc_autanalog_stt_sar_t
	The ADC section in the State Transition Table state. More...

Data Structure Documentation

◆ cy_stc_autanalog_sar_limit_t

struct cy_stc_autanalog_sar_limit_t

Data Fields
cy_en_autanalog_sar_cond_t	cond	Range detection condition.
int32_t	low	Low threshold for range detection.
int32_t	high	High threshold for range detection.

◆ cy_stc_autanalog_sar_hs_chan_t

struct cy_stc_autanalog_sar_hs_chan_t

Data Fields
cy_en_autanalog_sar_pin_hs_t	posPin	Positive pin assignment.
bool	hsDiffEn	Enable Pseudo differential mode for the single-ended ADC. FALSE - Pseudo differential mode is disabled; TRUE - Pseudo differential mode is enabled;
bool	sign	Output data as a unsigned/signed value, for more details, refer to Signed/Unsigned Output chapter. FALSE - unsigned number; TRUE - signed number;
cy_en_autanalog_sar_ch_coeff_t	posCoeff	Configuration of the positive input correction coefficient.
cy_en_autanalog_sar_pin_hs_t	negPin	The negative pin assignment. Note Only applicable in Pseudo Differential mode, refer to cy_stc_autanalog_sar_hs_chan_t::hsDiffEn
bool	accShift	Enable the averaging in the HW: Enable the right shift of the accumulated result for cy_stc_autanalog_sar_seq_tab_hs_t::accCount, refer to Averaging chapter. FALSE - shift is disabled; TRUE - shift is enabled;
cy_en_autanalog_sar_ch_coeff_t	negCoeff	Configuration of the negative input correction coefficient. Note Only applicable in Pseudo Differential mode, refer to cy_stc_autanalog_sar_hs_chan_t::hsDiffEn
cy_en_autanalog_sar_limit_t	hsLimit	The status selector for the ADC output range.
cy_en_autanalog_fifo_sel_t	fifoSel	Define use of FIFO and select buffer if required, refer to FIFO (The buffer block to store collected data) chapter.

◆ cy_stc_autanalog_sar_mux_chan_t

struct cy_stc_autanalog_sar_mux_chan_t

Data Fields
cy_en_autanalog_sar_pin_mux_t	posPin	Positive pin assignment.
bool	sign	Output data as a unsigned/signed value, for more details, refer to Signed/Unsigned Output chapter. FALSE - unsigned number; TRUE - signed number;
cy_en_autanalog_sar_ch_coeff_t	posCoeff	Configuration of the positive input correction coefficient.
cy_en_autanalog_sar_pin_mux_t	negPin	Negative pin assignment. Note Only applicable in Low Power mode OR in High Speed mode and for MUX channel configured in Pseudo Differential mode, refer to cy_stc_autanalog_sar_seq_tab_hs_t::muxMode
bool	buffBypass	Bypass MUX channels buffers. FALSE - buffers are enabled; TRUE - buffers are bypassed;
bool	accShift	Enable the averaging in the HW: Enable the right shift of the accumulated result for cy_stc_autanalog_sar_seq_tab_lp_t::accCount, refer to Averaging chapter. FALSE - shift is disabled; TRUE - shift is enabled;
cy_en_autanalog_sar_ch_coeff_t	negCoeff	Configuration of the negative input correction coefficient. Note Only applicable in Low Power mode OR in High Speed mode and for MUX channel configured in Pseudo Differential mode, refer to cy_stc_autanalog_sar_seq_tab_hs_t::muxMode
cy_en_autanalog_sar_limit_t	muxLimit	The status selector for the ADC output range.
cy_en_autanalog_fifo_sel_t	fifoSel	Define use of FIFO and select buffer if required, refer to FIFO (The buffer block to store collected data) chapter.

◆ cy_stc_autanalog_sar_sta_hs_t

struct cy_stc_autanalog_sar_sta_hs_t

Data Fields
cy_en_autanalog_sar_vref_t	hsVref	Select ADC voltage reference, refer to Reference Voltage chapter.
uint16_t	hsSampleTime[CY_AUTANALOG_SAR_SAMPLE_TIME_NUM]	The array of sample time settings represented in clock cycles for ADC HS mode, actual value is SAMPLE_TIME + 1, valid range 1...1024. Refer to Sample Time chapter. Note 12us (SAMPLE_TIME: 1023) is the recommended sampling time for Die temperature measurement.
cy_stc_autanalog_sar_hs_chan_t *	hsGpioChan[PASS_SAR_SAR_GPIO_CHANNELS]	The array of pointers to configuration structures for GPIO channels, NULL means the channel is not configured.
uint8_t	hsGpioResultMask	GPIO channels result mask, valid range 0x0...0xFF. Refer to Handling of the Result chapter

◆ cy_stc_autanalog_sar_sta_lp_t

struct cy_stc_autanalog_sar_sta_lp_t

Data Fields

bool

lpDiffEn

Enable ADC channel differential mode.

FALSE - differential mode is disabled;
TRUE - differential mode is enabled;

cy_en_autanalog_sar_vref_t lpVref Select ADC voltage reference, refer to Reference Voltage chapter.

uint16_t

lpSampleTime[CY_AUTANALOG_SAR_SAMPLE_TIME_NUM]

The array of sample time settings represented in clock cycles for ADC LP mode, actual value is SAMPLE_TIME + 1, valid range 1...1024.

Refer to Sample Time chapter.

Note: 15us (SAMPLE_TIME: 61) is the recommended sampling time for Die temperature measurement.

◆ cy_stc_autanalog_sar_sta_t

struct cy_stc_autanalog_sar_sta_t

Data Fields
cy_stc_autanalog_sar_sta_lp_t *	lpStaCfg	LP part of static configuration. Note This part is optional, NULL pointer allowed for this field
cy_stc_autanalog_sar_sta_hs_t *	hsStaCfg	HS part of static configuration. Note This part is optional, NULL pointer allowed for this field
cy_en_autanalog_sar_buf_pwr_t	posBufPwr	The power mode of the buffer in the ADC positive input.
cy_en_autanalog_sar_buf_pwr_t	negBufPwr	The power mode of the buffer in the ADC negative input.
cy_en_autanalog_sar_acc_mode_t	accMode	Enable ADC result averaging and configure averaging mode, refer to Averaging chapter.
cy_en_autanalog_sar_calibrate_t	startupCal	Enable the ADC calibration during startup. This field is used to request calibration Process whenever the ADC is powered up (refer to cy_stc_autanalog_stt_sar_t::enable)
bool	chanID	Enable channel number identifier for data stored in FIFO, refer to Cy_AutAnalog_FIFO_ReadDataChanId function.
bool	shiftMode	Set the resolution of the averaging result if averaging performed by HW, refer to Averaging chapter. FALSE - 12 bit; TRUE - 16 bit;
cy_stc_autanalog_sar_mux_chan_t *	intMuxChan[PASS_SAR_SAR_MUX_CHANNELS]	The array of pointers to configuration structures for MUX channels, NULL means the channel is not configured.
cy_stc_autanalog_sar_limit_t *	limitCond[CY_AUTANALOG_SAR_LIMIT_CFG_NUM]	The array of pointers to the configuration structures for the ADC output range detection, a NULL element means that the range detection is not configured.
uint16_t	muxResultMask	MUX channels result mask, valid range 0x0...0xFFFF. Refer to Handling of the Result chapter
uint8_t	firResultMask	FIR filter result mask, valid range 0x0...0x3. Refer to Handling of the Result chapter

◆ cy_stc_autanalog_sar_seq_tab_hs_t

struct cy_stc_autanalog_sar_seq_tab_hs_t

Data Fields
uint8_t	chanEn	GPIO channels enable mask, valid range 0x0...0xFF, see High Speed Channels and Masks macros. Refer to cy_stc_autanalog_sar_sta_hs_t::hsGpioChan for channels configurations
uint8_t	muxMode	Define the operating mode of the MUX channels in HS mode, see High Speed Channels and Masks macros.
uint8_t	mux0Sel	MUX 0 channel selection, valid range 0...15, see Low Power Channels and Masks macros. Refer to cy_stc_autanalog_sar_sta_t::intMuxChan for channel configurations
uint8_t	mux1Sel	MUX 1 channel selection, valid range 0...15, see Low Power Channels and Masks macros. Refer to cy_stc_autanalog_sar_sta_t::intMuxChan for channel configurations
bool	sampleTimeEn	Enable the sample time option, refer to Sample Time chapter. FALSE - ADC sampling is not delayed; TRUE - ADC sampling is delayed by the sampling time;
cy_en_autanalog_sar_sample_time_t	sampleTime	Sample timer selection. Select one of the four available sample timers, see cy_stc_autanalog_sar_sta_hs_t::hsSampleTime
bool	accEn	Enable the conversion averaging, refer to Averaging chapter. FALSE - averaging disabled; TRUE - averaging enabled;
cy_en_autanalog_sar_acc_cnt_t	accCount	The averaging count for the selected averaging mode, see cy_stc_autanalog_sar_sta_t::accMode.
cy_en_autanalog_sar_calibrate_t	calReq	A real-time calibration channel request. This request is the signal to the ADC to initiate a real-time calibration process during an ADC scan.
cy_en_autanalog_sar_next_act_t	nextAction	The ADC sequencer next state, refer to Sequencer and State Transition Table chapter.

◆ cy_stc_autanalog_sar_seq_tab_lp_t

struct cy_stc_autanalog_sar_seq_tab_lp_t

Data Fields
bool	chanEn	Enable the LP channel. FALSE - Disable ADC LP channel; TRUE - Enable ADC LP channel;
uint8_t	mux0Sel	MUX 0 channel selection, valid range 0...15. See Low Power Channels and Masks macros
bool	sampleTimeEn	Enable the sample time option, refer to Sample Time chapter. FALSE - ADC sampling is not delayed; TRUE - ADC sampling is delayed by the sampling time;
cy_en_autanalog_sar_sample_time_t	sampleTime	Sample timer selection. Select one of the four available sample timers, see cy_stc_autanalog_sar_sta_lp_t::lpSampleTime
bool	accEn	Enable the conversion averaging, refer to Averaging chapter. FALSE - averaging disabled; TRUE - averaging enabled;
cy_en_autanalog_sar_acc_cnt_t	accCount	The averaging count for the selected averaging mode, see cy_stc_autanalog_sar_sta_t::accMode.
cy_en_autanalog_sar_calibrate_t	calReq	A real-time calibration channel request. This request is the signal to the ADC to initiate a real-time calibration process during an ADC scan.
cy_en_autanalog_sar_next_act_t	nextAction	The ADC sequencer next state, refer to Sequencer and State Transition Table chapter.

◆ cy_stc_autanalog_sar_fir_cfg_t

struct cy_stc_autanalog_sar_fir_cfg_t

Data Fields
cy_en_autanalog_sar_fir_channel_t	chanSel	The logical channel selection for the FIR filter.
int16_t *	coeff	The array of FIR filter coefficients, the size of the array is defined by defined by cy_stc_autanalog_sar_fir_cfg_t::tapSel. Refer to FIR Filter chapter
uint8_t	tapSel	The tap value, actual value is TAP_SEL + 1, valid range 1...64.
uint8_t	shiftSel	FIR filter output scaling: shift the FIR filter output to the right by the specified number, valid range 0...16.
bool	waitTapInit	FIR filter output init delay: wait for a specified number of updates before outputting first valid data. FALSE - FIR generates a SAR_FIRx_DONE trigger after each update; TRUE - FIR waits for TAP_SEL + 1 updates before triggering;
cy_en_autanalog_sar_limit_t	firLimit	The status selector for the FIR filter output range.
cy_en_autanalog_fifo_sel_t	fifoSel	Define use of FIFO and select buffer if required, refer to FIFO (The buffer block to store collected data) chapter.

◆ cy_stc_autanalog_sar_t

struct cy_stc_autanalog_sar_t

Data Fields
cy_stc_autanalog_sar_sta_t *	sarStaCfg	The pointer to a static part of the ADC configuration.
uint8_t	hsSeqTabNum	The number of HS Sequencer Table structures, valid range 0...32.
cy_stc_autanalog_sar_seq_tab_hs_t *	hsSeqTabArr	Pointer to the array of HS Sequencer Table structures, the array length is specified by hsSeqTabNum.
uint8_t	lpSeqTabNum	The number of LP Sequencer Table structures, valid range 0...32.
cy_stc_autanalog_sar_seq_tab_lp_t *	lpSeqTabArr	Pointer to the array of HS Sequencer Table structures, the array length is specified by lpSeqTabNum.
uint8_t	firNum	Number of used FIR filters, valid range 0...2.
cy_stc_autanalog_sar_fir_cfg_t *	firCfg	Pointer to the array of FIR filter configuration structures, the array length is specified by firNum.
cy_stc_autanalog_fifo_cfg_t *	fifoCfg	Pointer to the FIFO configuration structure.

◆ cy_stc_autanalog_stt_sar_t

struct cy_stc_autanalog_stt_sar_t

Data Fields
bool	unlock	ADC Unlock: FALSE - Locked: Data from fields enable, trigger and entryState of this structure are NOT taken into account in the corresponding state of STT; TRUE - Unlocked: Data from fields enable, trigger and entryState of this structure are used in the STT corresponding state;
bool	enable	Enable the ADC.
bool	trigger	This field initiates the ADC operation per sequencer settings.
uint8_t	entryState	ADC Sequencer entry state, points to the item of the cy_stc_autanalog_sar_t::hsSeqTabArr or cy_stc_autanalog_sar_t::lpSeqTabArr depends on the current cy_stc_autanalog_stt_ac_t::lpMode setting, the valid range is 0...31.