Enumerated Types

General Description

Enumerations
enum	cy_en_autanalog_sar_input_t {   CY_AUTANALOG_SAR_INPUT_GPIO = 0U ,   CY_AUTANALOG_SAR_INPUT_MUX = 1U }
	The ADC input type, for more details, refer to the device Architecture Technical Reference Manual. More...
enum	cy_en_autanalog_sar_pin_hs_t {   CY_AUTANALOG_SAR_PIN_GPIO0 = 0UL ,   CY_AUTANALOG_SAR_PIN_GPIO1 = 1UL ,   CY_AUTANALOG_SAR_PIN_GPIO2 = 2UL ,   CY_AUTANALOG_SAR_PIN_GPIO3 = 3UL ,   CY_AUTANALOG_SAR_PIN_GPIO4 = 4UL ,   CY_AUTANALOG_SAR_PIN_GPIO5 = 5UL ,   CY_AUTANALOG_SAR_PIN_GPIO6 = 6UL ,   CY_AUTANALOG_SAR_PIN_GPIO7 = 7UL }
	The channel input assignment in ADC HS operating mode, for more details, refer to the device Architecture Technical Reference Manual. More...
enum	cy_en_autanalog_sar_pin_mux_t {   CY_AUTANALOG_SAR_PIN_MUX_CTB0_PIN1 = 0UL ,   CY_AUTANALOG_SAR_PIN_MUX_CTB0_PIN4 = 1UL ,   CY_AUTANALOG_SAR_PIN_MUX_CTB0_PIN6 = 2UL ,   CY_AUTANALOG_SAR_PIN_MUX_CTB0_PIN7 = 3UL ,   CY_AUTANALOG_SAR_PIN_MUX_CTB1_PIN1 = 4UL ,   CY_AUTANALOG_SAR_PIN_MUX_CTB1_PIN4 = 5UL ,   CY_AUTANALOG_SAR_PIN_MUX_CTB1_PIN6 = 6UL ,   CY_AUTANALOG_SAR_PIN_MUX_CTB1_PIN7 = 7UL ,   CY_AUTANALOG_SAR_PIN_MUX_CTB0_OA0_OUT = 8UL ,   CY_AUTANALOG_SAR_PIN_MUX_CTB0_OA1_OUT = 9UL ,   CY_AUTANALOG_SAR_PIN_MUX_CTB1_OA0_OUT = 10UL ,   CY_AUTANALOG_SAR_PIN_MUX_CTB1_OA1_OUT = 11UL ,   CY_AUTANALOG_SAR_PIN_MUX_DAC0 = 12UL ,   CY_AUTANALOG_SAR_PIN_MUX_DAC1 = 13UL ,   CY_AUTANALOG_SAR_PIN_MUX_TEMP_SENSOR = 14UL ,   CY_AUTANALOG_SAR_PIN_MUX_GPIO0 = 15UL ,   CY_AUTANALOG_SAR_PIN_MUX_GPIO1 = 16UL ,   CY_AUTANALOG_SAR_PIN_MUX_GPIO2 = 17UL ,   CY_AUTANALOG_SAR_PIN_MUX_GPIO3 = 18UL ,   CY_AUTANALOG_SAR_PIN_MUX_GPIO4 = 19UL ,   CY_AUTANALOG_SAR_PIN_MUX_GPIO5 = 20UL ,   CY_AUTANALOG_SAR_PIN_MUX_GPIO6 = 21UL ,   CY_AUTANALOG_SAR_PIN_MUX_GPIO7 = 22UL ,   CY_AUTANALOG_SAR_PIN_MUX_VSSA = 25UL }
	The channel input assignment in the ADC HS/LP operating mode, for more details, refer to the device Architecture Technical Reference Manual. More...
enum	cy_en_autanalog_sar_limit_t {   CY_AUTANALOG_SAR_LIMIT_STATUS_DISABLED = 0UL ,   CY_AUTANALOG_SAR_LIMIT_STATUS_STC0 = 1UL ,   CY_AUTANALOG_SAR_LIMIT_STATUS_STC1 = 2UL ,   CY_AUTANALOG_SAR_LIMIT_STATUS_STC2 = 3UL ,   CY_AUTANALOG_SAR_LIMIT_STATUS_STC3 = 4UL }
	The ADC range status selection, defines the selected range conditions for the ADC result. More...
enum	cy_en_autanalog_sar_cond_t {   CY_AUTANALOG_SAR_COND_BELOW = 0UL ,   CY_AUTANALOG_SAR_COND_INSIDE = 1UL ,   CY_AUTANALOG_SAR_COND_ABOVE = 2UL ,   CY_AUTANALOG_SAR_COND_OUTSIDE = 3UL }
	Defines the range detection conditions for the ADC result, refer to cy_stc_autanalog_sar_limit_t. More...
enum	cy_en_autanalog_sar_ch_coeff_t {   CY_AUTANALOG_SAR_CH_COEFF_DISABLED = 0UL ,   CY_AUTANALOG_SAR_CH_COEFF0 = 1UL ,   CY_AUTANALOG_SAR_CH_COEFF1 = 2UL ,   CY_AUTANALOG_SAR_CH_COEFF2 = 3UL ,   CY_AUTANALOG_SAR_CH_COEFF3 = 4UL ,   CY_AUTANALOG_SAR_CH_COEFF4 = 5UL ,   CY_AUTANALOG_SAR_CH_COEFF5 = 6UL ,   CY_AUTANALOG_SAR_CH_COEFF6 = 7UL ,   CY_AUTANALOG_SAR_CH_COEFF7 = 8UL }
	The ADC channel correction coefficient, for more details, refer to the device Architecture Technical Reference Manual. More...
enum	cy_en_autanalog_sar_vref_t {   CY_AUTANALOG_SAR_VREF_VDDA = 0UL ,   CY_AUTANALOG_SAR_VREF_EXT = 1UL ,   CY_AUTANALOG_SAR_VREF_VBGR = 2UL ,   CY_AUTANALOG_SAR_VREF_VDDA_BY_2 = 3UL ,   CY_AUTANALOG_SAR_VREF_PRB_OUT0 = 4UL ,   CY_AUTANALOG_SAR_VREF_PRB_OUT1 = 5UL }
	The ADC reference voltage, for more details, refer to the device Architecture Technical Reference Manual. More...
enum	cy_en_autanalog_sar_buf_pwr_t {   CY_AUTANALOG_SAR_BUF_PWR_OFF = 0UL ,   CY_AUTANALOG_SAR_BUF_PWR_ULTRA_LOW = 1UL ,   CY_AUTANALOG_SAR_BUF_PWR_ULTRA_LOW_RAIL = 2UL ,   CY_AUTANALOG_SAR_BUF_PWR_LOW_RAIL = 4UL ,   CY_AUTANALOG_SAR_BUF_PWR_MEDIUM_RAIL = 6UL ,   CY_AUTANALOG_SAR_BUF_PWR_HIGH_RAIL = 8UL ,   CY_AUTANALOG_SAR_BUF_PWR_ULTRA_HIGH_RAIL = 10UL }
	The power modes of the ADC buffers. More...
enum	cy_en_autanalog_sar_acc_mode_t {   CY_AUTANALOG_SAR_ACC_DISABLED = 0UL ,   CY_AUTANALOG_SAR_ACC_ACCUNDUMP = 1UL }
	Averaging mode applied to all channels in a scan with averaging enabled, for more details, refer to the device Architecture Technical Reference Manual. More...
enum	cy_en_autanalog_sar_acc_cnt_t {   CY_AUTANALOG_SAR_ACC_CNT2 = 0UL ,   CY_AUTANALOG_SAR_ACC_CNT4 = 1UL ,   CY_AUTANALOG_SAR_ACC_CNT8 = 2UL ,   CY_AUTANALOG_SAR_ACC_CNT16 = 3UL ,   CY_AUTANALOG_SAR_ACC_CNT32 = 4UL ,   CY_AUTANALOG_SAR_ACC_CNT64 = 5UL ,   CY_AUTANALOG_SAR_ACC_CNT128 = 6UL ,   CY_AUTANALOG_SAR_ACC_CNT256 = 7UL }
	The number of samples for averaging, for more details, refer to the device Architecture Technical Reference Manual. More...
enum	cy_en_autanalog_sar_sample_time_t {   CY_AUTANALOG_SAR_SAMPLE_TIME0 = 0U ,   CY_AUTANALOG_SAR_SAMPLE_TIME1 = 1U ,   CY_AUTANALOG_SAR_SAMPLE_TIME2 = 2U ,   CY_AUTANALOG_SAR_SAMPLE_TIME3 = 3U }
	The ADC sampling timer, for more details, refer to the device Architecture Technical Reference Manual. More...
enum	cy_en_autanalog_sar_calibrate_t {   CY_AUTANALOG_SAR_CAL_DISABLED = 0UL ,   CY_AUTANALOG_SAR_CAL_BOTH = 1UL ,   CY_AUTANALOG_SAR_CAL_OFFSET = 2UL ,   CY_AUTANALOG_SAR_CAL_LINEARITY = 3UL }
	The ADC calibration, for more details, refer to the device Architecture Technical Reference Manual. More...
enum	cy_en_autanalog_sar_next_act_t {   CY_AUTANALOG_SAR_NEXT_ACTION_STATE_STOP = 0UL ,   CY_AUTANALOG_SAR_NEXT_ACTION_GO_TO_ENTRY_ADDR = 1UL ,   CY_AUTANALOG_SAR_NEXT_ACTION_GO_TO_NEXT = 2UL }
	The Next State for the ADC sequencer while scanning, for more details, refer to the device Architecture Technical Reference Manual. More...
enum	cy_en_autanalog_sar_fir_channel_t {   CY_AUTANALOG_SAR_FIR_CH_DISABLED = 0UL ,   CY_AUTANALOG_SAR_FIR_CH_GPIO0 = 1UL ,   CY_AUTANALOG_SAR_FIR_CH_GPIO1 = 2UL ,   CY_AUTANALOG_SAR_FIR_CH_GPIO2 = 3UL ,   CY_AUTANALOG_SAR_FIR_CH_GPIO3 = 4UL ,   CY_AUTANALOG_SAR_FIR_CH_GPIO4 = 5UL ,   CY_AUTANALOG_SAR_FIR_CH_GPIO5 = 6UL ,   CY_AUTANALOG_SAR_FIR_CH_GPIO6 = 7UL ,   CY_AUTANALOG_SAR_FIR_CH_GPIO7 = 8UL ,   CY_AUTANALOG_SAR_FIR_CH_MUX0 = 9UL ,   CY_AUTANALOG_SAR_FIR_CH_MUX1 = 10UL ,   CY_AUTANALOG_SAR_FIR_CH_MUX2 = 11UL ,   CY_AUTANALOG_SAR_FIR_CH_MUX3 = 12UL ,   CY_AUTANALOG_SAR_FIR_CH_MUX4 = 13UL ,   CY_AUTANALOG_SAR_FIR_CH_MUX5 = 14UL ,   CY_AUTANALOG_SAR_FIR_CH_MUX6 = 15UL ,   CY_AUTANALOG_SAR_FIR_CH_MUX7 = 16UL ,   CY_AUTANALOG_SAR_FIR_CH_MUX8 = 17UL ,   CY_AUTANALOG_SAR_FIR_CH_MUX9 = 18UL ,   CY_AUTANALOG_SAR_FIR_CH_MUX10 = 19UL ,   CY_AUTANALOG_SAR_FIR_CH_MUX11 = 20UL ,   CY_AUTANALOG_SAR_FIR_CH_MUX12 = 21UL ,   CY_AUTANALOG_SAR_FIR_CH_MUX13 = 22UL ,   CY_AUTANALOG_SAR_FIR_CH_MUX14 = 23UL ,   CY_AUTANALOG_SAR_FIR_CH_MUX15 = 24UL }
	The FIR filter input channel selection, for more details, refer to the device Architecture Technical Reference Manual. More...

Enumeration Type Documentation

cy_en_autanalog_sar_input_t

enum cy_en_autanalog_sar_input_t

The ADC input type, for more details, refer to the device Architecture Technical Reference Manual.

Enumerator
CY_AUTANALOG_SAR_INPUT_GPIO	The GPIO channels.
CY_AUTANALOG_SAR_INPUT_MUX	The MUX channels.

cy_en_autanalog_sar_pin_hs_t

enum cy_en_autanalog_sar_pin_hs_t

The channel input assignment in ADC HS operating mode, for more details, refer to the device Architecture Technical Reference Manual.

Enumerator
CY_AUTANALOG_SAR_PIN_GPIO0	The GPIO pin 0.
CY_AUTANALOG_SAR_PIN_GPIO1	The GPIO pin 1.
CY_AUTANALOG_SAR_PIN_GPIO2	The GPIO pin 2.
CY_AUTANALOG_SAR_PIN_GPIO3	The GPIO pin 3.
CY_AUTANALOG_SAR_PIN_GPIO4	The GPIO pin 4.
CY_AUTANALOG_SAR_PIN_GPIO5	The GPIO pin 5.
CY_AUTANALOG_SAR_PIN_GPIO6	The GPIO pin 6.
CY_AUTANALOG_SAR_PIN_GPIO7	The GPIO pin 7.

cy_en_autanalog_sar_pin_mux_t

enum cy_en_autanalog_sar_pin_mux_t

The channel input assignment in the ADC HS/LP operating mode, for more details, refer to the device Architecture Technical Reference Manual.

Enumerator
CY_AUTANALOG_SAR_PIN_MUX_CTB0_PIN1	The CTB0 GPIO pin 1.
CY_AUTANALOG_SAR_PIN_MUX_CTB0_PIN4	The CTB0 GPIO pin 4.
CY_AUTANALOG_SAR_PIN_MUX_CTB0_PIN6	The CTB0 GPIO pin 6.
CY_AUTANALOG_SAR_PIN_MUX_CTB0_PIN7	The CTB0 GPIO pin 7.
CY_AUTANALOG_SAR_PIN_MUX_CTB1_PIN1	The CTB1 GPIO pin 1.
CY_AUTANALOG_SAR_PIN_MUX_CTB1_PIN4	The CTB1 GPIO pin 4.
CY_AUTANALOG_SAR_PIN_MUX_CTB1_PIN6	The CTB1 GPIO pin 6.
CY_AUTANALOG_SAR_PIN_MUX_CTB1_PIN7	The CTB1 GPIO pin 7.
CY_AUTANALOG_SAR_PIN_MUX_CTB0_OA0_OUT	The CTB0 OpAmp0 output.
CY_AUTANALOG_SAR_PIN_MUX_CTB0_OA1_OUT	The CTB0 OpAmp1 output.
CY_AUTANALOG_SAR_PIN_MUX_CTB1_OA0_OUT	The CTB1 OpAmp0 output.
CY_AUTANALOG_SAR_PIN_MUX_CTB1_OA1_OUT	The CTB1 OpAmp1 output.
CY_AUTANALOG_SAR_PIN_MUX_DAC0	The DAC0 output
CY_AUTANALOG_SAR_PIN_MUX_DAC1	The DAC1 output
CY_AUTANALOG_SAR_PIN_MUX_TEMP_SENSOR	Temperature sensor.
CY_AUTANALOG_SAR_PIN_MUX_GPIO0	The GPIO 0.
CY_AUTANALOG_SAR_PIN_MUX_GPIO1	The GPIO 1.
CY_AUTANALOG_SAR_PIN_MUX_GPIO2	The GPIO 2.
CY_AUTANALOG_SAR_PIN_MUX_GPIO3	The GPIO 3.
CY_AUTANALOG_SAR_PIN_MUX_GPIO4	The GPIO 4.
CY_AUTANALOG_SAR_PIN_MUX_GPIO5	The GPIO 5.
CY_AUTANALOG_SAR_PIN_MUX_GPIO6	The GPIO 6.
CY_AUTANALOG_SAR_PIN_MUX_GPIO7	The GPIO 7.
CY_AUTANALOG_SAR_PIN_MUX_VSSA	The ADC ground.

cy_en_autanalog_sar_limit_t

enum cy_en_autanalog_sar_limit_t

The ADC range status selection, defines the selected range conditions for the ADC result.

For more details, refer to the device Architecture Technical Reference Manual.

Enumerator
CY_AUTANALOG_SAR_LIMIT_STATUS_DISABLED	The limit status is not used.
CY_AUTANALOG_SAR_LIMIT_STATUS_STC0	The limit status configuration 0.
CY_AUTANALOG_SAR_LIMIT_STATUS_STC1	The limit status configuration 1.
CY_AUTANALOG_SAR_LIMIT_STATUS_STC2	The limit status configuration 2.
CY_AUTANALOG_SAR_LIMIT_STATUS_STC3	The limit status configuration 3.

cy_en_autanalog_sar_cond_t

enum cy_en_autanalog_sar_cond_t

Defines the range detection conditions for the ADC result, refer to cy_stc_autanalog_sar_limit_t.

For more details, refer to the device Architecture Technical Reference Manual.

Enumerator
CY_AUTANALOG_SAR_COND_BELOW	result < cy_stc_autanalog_sar_limit_t::low
CY_AUTANALOG_SAR_COND_INSIDE	cy_stc_autanalog_sar_limit_t::low <= result AND result < cy_stc_autanalog_sar_limit_t::high
CY_AUTANALOG_SAR_COND_ABOVE	result > cy_stc_autanalog_sar_limit_t::high
CY_AUTANALOG_SAR_COND_OUTSIDE	result < cy_stc_autanalog_sar_limit_t::low OR result >= cy_stc_autanalog_sar_limit_t::high

cy_en_autanalog_sar_ch_coeff_t

enum cy_en_autanalog_sar_ch_coeff_t

The ADC channel correction coefficient, for more details, refer to the device Architecture Technical Reference Manual.

Enumerator
CY_AUTANALOG_SAR_CH_COEFF_DISABLED	The channel correction coefficient not used.
CY_AUTANALOG_SAR_CH_COEFF0	The channel correction coefficient configuration 0.
CY_AUTANALOG_SAR_CH_COEFF1	The channel correction coefficient configuration 1.
CY_AUTANALOG_SAR_CH_COEFF2	The channel correction coefficient configuration 2.
CY_AUTANALOG_SAR_CH_COEFF3	The channel correction coefficient configuration 3.
CY_AUTANALOG_SAR_CH_COEFF4	The channel correction coefficient configuration 4.
CY_AUTANALOG_SAR_CH_COEFF5	The channel correction coefficient configuration 5.
CY_AUTANALOG_SAR_CH_COEFF6	The channel correction coefficient configuration 6.
CY_AUTANALOG_SAR_CH_COEFF7	The channel correction coefficient configuration 7.

cy_en_autanalog_sar_vref_t

enum cy_en_autanalog_sar_vref_t

The ADC reference voltage, for more details, refer to the device Architecture Technical Reference Manual.

Enumerator
CY_AUTANALOG_SAR_VREF_VDDA	The ADC reference is Vdda.
CY_AUTANALOG_SAR_VREF_EXT	The ADC reference is External. Note In HS mode, connect the bypass capacitor to this pin to hold the charge for the conversion if external VREF is not used. See the device datasheet for the capacitance value and exact location of this pin.
CY_AUTANALOG_SAR_VREF_VBGR	The ADC reference is VBGR.
CY_AUTANALOG_SAR_VREF_VDDA_BY_2	The ADC reference is Vdda/2.
CY_AUTANALOG_SAR_VREF_PRB_OUT0	The ADC reference is Vref0 from the PRB0.
CY_AUTANALOG_SAR_VREF_PRB_OUT1	The ADC reference is Vref1 from the PRB1.

cy_en_autanalog_sar_buf_pwr_t

enum cy_en_autanalog_sar_buf_pwr_t

The power modes of the ADC buffers.

Each power setting consumes different levels of the current and supports a different input range and gain bandwidth. The charge pump is used to increase the input range to the rails. For more details, refer to the device Architecture Technical Reference Manual.

Enumerator
CY_AUTANALOG_SAR_BUF_PWR_OFF	The power mode for the buffer is OFF, the buffer is disabled.
CY_AUTANALOG_SAR_BUF_PWR_ULTRA_LOW	The power mode for the buffer is ULTRA LOW, the charge pump is OFF. The buffer quiescent current is 15uA and the gain bandwidth is 30kHz;
CY_AUTANALOG_SAR_BUF_PWR_ULTRA_LOW_RAIL	The power mode for the buffer is ULTRA LOW, the charge pump is ON. The buffer quiescent current is 35uA and the gain bandwidth is 30kHz;
CY_AUTANALOG_SAR_BUF_PWR_LOW_RAIL	The power mode for the buffer is LOW, the charge pump is ON. The buffer quiescent current is 150uA and the gain bandwidth is 350kHz;
CY_AUTANALOG_SAR_BUF_PWR_MEDIUM_RAIL	The power mode for the buffer is MEDIUM, the charge pump is ON. The buffer quiescent current is 200uA and the gain bandwidth is 700kHz; Note This is the recommended operating mode for ADC channel buffers.
CY_AUTANALOG_SAR_BUF_PWR_HIGH_RAIL	The power mode for the buffer is HIGH, the charge pump is ON. The buffer quiescent current is 600uA and the gain bandwidth is 1.75MHz;
CY_AUTANALOG_SAR_BUF_PWR_ULTRA_HIGH_RAIL	The power mode for the buffer is ULTRA HIGH, the charge pump is ON. The buffer quiescent current is 800uA and the gain bandwidth is 2.8MHz;

cy_en_autanalog_sar_acc_mode_t

enum cy_en_autanalog_sar_acc_mode_t

Averaging mode applied to all channels in a scan with averaging enabled, for more details, refer to the device Architecture Technical Reference Manual.

Enumerator
CY_AUTANALOG_SAR_ACC_DISABLED	Average disabled.
CY_AUTANALOG_SAR_ACC_ACCUNDUMP	Average mode: Accumulate and Dump: channels are sampled and accumulated back-to-back.

cy_en_autanalog_sar_acc_cnt_t

enum cy_en_autanalog_sar_acc_cnt_t

The number of samples for averaging, for more details, refer to the device Architecture Technical Reference Manual.

Enumerator
CY_AUTANALOG_SAR_ACC_CNT2	Set samples averaged to 2.
CY_AUTANALOG_SAR_ACC_CNT4	Set samples averaged to 4.
CY_AUTANALOG_SAR_ACC_CNT8	Set samples averaged to 8.
CY_AUTANALOG_SAR_ACC_CNT16	Set samples averaged to 16.
CY_AUTANALOG_SAR_ACC_CNT32	Set samples averaged to 32.
CY_AUTANALOG_SAR_ACC_CNT64	Set samples averaged to 64.
CY_AUTANALOG_SAR_ACC_CNT128	Set samples averaged to 128.
CY_AUTANALOG_SAR_ACC_CNT256	Set samples averaged to 256.

cy_en_autanalog_sar_sample_time_t

enum cy_en_autanalog_sar_sample_time_t

The ADC sampling timer, for more details, refer to the device Architecture Technical Reference Manual.

Enumerator
CY_AUTANALOG_SAR_SAMPLE_TIME0	Sampling Timer 0.
CY_AUTANALOG_SAR_SAMPLE_TIME1	Sampling Timer 1.
CY_AUTANALOG_SAR_SAMPLE_TIME2	Sampling Timer 2.
CY_AUTANALOG_SAR_SAMPLE_TIME3	Sampling Timer 3.

cy_en_autanalog_sar_calibrate_t

enum cy_en_autanalog_sar_calibrate_t

The ADC calibration, for more details, refer to the device Architecture Technical Reference Manual.

Enumerator
CY_AUTANALOG_SAR_CAL_DISABLED	Calibration disabled.
CY_AUTANALOG_SAR_CAL_BOTH	Calibrate both Offset and Linearity.
CY_AUTANALOG_SAR_CAL_OFFSET	Calibrate Offset only.
CY_AUTANALOG_SAR_CAL_LINEARITY	Calibrate Linearity only.

cy_en_autanalog_sar_next_act_t

enum cy_en_autanalog_sar_next_act_t

The Next State for the ADC sequencer while scanning, for more details, refer to the device Architecture Technical Reference Manual.

Enumerator
CY_AUTANALOG_SAR_NEXT_ACTION_STATE_STOP	Stop, send SAR_EOS and SAR_DONE events and idle.
CY_AUTANALOG_SAR_NEXT_ACTION_GO_TO_ENTRY_ADDR	Continuous mode, send SAR_EOS event and return to start.
CY_AUTANALOG_SAR_NEXT_ACTION_GO_TO_NEXT	Continue to a next state in a given scan.

cy_en_autanalog_sar_fir_channel_t

enum cy_en_autanalog_sar_fir_channel_t

The FIR filter input channel selection, for more details, refer to the device Architecture Technical Reference Manual.

Enumerator
CY_AUTANALOG_SAR_FIR_CH_DISABLED	The FIR filter input is disabled.
CY_AUTANALOG_SAR_FIR_CH_GPIO0	The GPIO channel 0.
CY_AUTANALOG_SAR_FIR_CH_GPIO1	The GPIO channel 1.
CY_AUTANALOG_SAR_FIR_CH_GPIO2	The GPIO channel 2.
CY_AUTANALOG_SAR_FIR_CH_GPIO3	The GPIO channel 3.
CY_AUTANALOG_SAR_FIR_CH_GPIO4	The GPIO channel 4.
CY_AUTANALOG_SAR_FIR_CH_GPIO5	The GPIO channel 5.
CY_AUTANALOG_SAR_FIR_CH_GPIO6	The GPIO channel 6.
CY_AUTANALOG_SAR_FIR_CH_GPIO7	The GPIO channel 7.
CY_AUTANALOG_SAR_FIR_CH_MUX0	The MUX channel 0.
CY_AUTANALOG_SAR_FIR_CH_MUX1	The MUX channel 1.
CY_AUTANALOG_SAR_FIR_CH_MUX2	The MUX channel 2.
CY_AUTANALOG_SAR_FIR_CH_MUX3	The MUX channel 3.
CY_AUTANALOG_SAR_FIR_CH_MUX4	The MUX channel 4.
CY_AUTANALOG_SAR_FIR_CH_MUX5	The MUX channel 5.
CY_AUTANALOG_SAR_FIR_CH_MUX6	The MUX channel 6.
CY_AUTANALOG_SAR_FIR_CH_MUX7	The MUX channel 7.
CY_AUTANALOG_SAR_FIR_CH_MUX8	The MUX channel 8.
CY_AUTANALOG_SAR_FIR_CH_MUX9	The MUX channel 9.
CY_AUTANALOG_SAR_FIR_CH_MUX10	The MUX channel 10.
CY_AUTANALOG_SAR_FIR_CH_MUX11	The MUX channel 11.
CY_AUTANALOG_SAR_FIR_CH_MUX12	The MUX channel 12.
CY_AUTANALOG_SAR_FIR_CH_MUX13	The MUX channel 13.
CY_AUTANALOG_SAR_FIR_CH_MUX14	The MUX channel 14.
CY_AUTANALOG_SAR_FIR_CH_MUX15	The MUX channel 15.