API Reference | |
| High Speed Channels and Masks | |
| The ADC HS mode: can be ORed together and applied to the cy_stc_autanalog_sar_seq_tab_hs_t::chanEn. | |
| Low Power Channels and Masks | |
| The ADC LP mode. | |
| FIR filter Channels and Masks | |
Macros | |
| #define | CY_AUTANALOG_SAR_SEQUENCER_NUM (32UL) |
| The number of High Speed and Low Power ADC sequencers. More... | |
| #define | CY_AUTANALOG_SAR_SAMPLE_TIME_NUM (4UL) |
| Number of ADC input sampling timers. More... | |
| #define | CY_AUTANALOG_SAR_LIMIT_CFG_NUM (4UL) |
| The number of structures for configuring the limits of the ADC result. More... | |
| #define | CY_AUTANALOG_SAR_CH_CORR_COEFF_NUM (8UL) |
| The number of ADC channel correction coefficients. More... | |
| #define | CY_AUTANALOG_SAR_FIR_NUM (2UL) |
| The number of FIR filters. More... | |
| #define | CY_AUTANALOG_SAR_FIR_TAP_NUM (64UL) |
| The maximum number of taps in FIR filter configuration. More... | |
| #define CY_AUTANALOG_SAR_SEQUENCER_NUM (32UL) |
The number of High Speed and Low Power ADC sequencers.
For more details, refer to the device Architecture Technical Reference Manual.
| #define CY_AUTANALOG_SAR_SAMPLE_TIME_NUM (4UL) |
Number of ADC input sampling timers.
For more details, refer to the device Architecture Technical Reference Manual.
| #define CY_AUTANALOG_SAR_LIMIT_CFG_NUM (4UL) |
The number of structures for configuring the limits of the ADC result.
For more details, refer to the device Architecture Technical Reference Manual.
| #define CY_AUTANALOG_SAR_CH_CORR_COEFF_NUM (8UL) |
The number of ADC channel correction coefficients.
For more details, refer to the device Architecture Technical Reference Manual.
| #define CY_AUTANALOG_SAR_FIR_NUM (2UL) |
The number of FIR filters.
For more details, refer to the device Architecture Technical Reference Manual.
| #define CY_AUTANALOG_SAR_FIR_TAP_NUM (64UL) |
The maximum number of taps in FIR filter configuration.
For more details, refer to the device Architecture Technical Reference Manual.