General Description

Data Structures
struct	cy_stc_pll_config_t
	Structure containing information for configuration of a PLL. More...

struct	cy_stc_dpll_lp_config_t
	Structure containing information for configuration of a DPLL-LP. More...

struct	cy_stc_dpll_hp_config_t
	Structure containing information for configuration of a DPLL-HP. More...

struct	cy_stc_pll_manual_config_t
	Structure containing information for manual configuration of a PLL. More...

Enumerations
enum	cy_en_wait_mode_select_t { CY_SYSCLK_DPLL_HP_CLK4MHZ_1US_CNT_VAL = 0U, CY_SYSCLK_DPLL_HP_CLK10MHZ_1US_CNT_VAL = 1U, CY_SYSCLK_DPLL_HP_CLK15MHZ_1US_CNT_VAL = 2U, CY_SYSCLK_DPLL_HP_CLK20MHZ_1US_CNT_VAL = 3U, CY_SYSCLK_DPLL_HP_CLK30MHZ_1US_CNT_VAL = 4U, CY_SYSCLK_DPLL_HP_CLK40MHZ_1US_CNT_VAL = 5U, CY_SYSCLK_DPLL_HP_CLK45MHZ_1US_CNT_VAL = 6U, CY_SYSCLK_DPLL_HP_CLK50MHZ_1US_CNT_VAL = 7U }
	DPLL-HP wait mode selection enum. More...

Enumeration Type Documentation

DPLL-HP wait mode selection enum.

See CONFIG2 register, bits MODE_SEL.

Enumerator
CY_SYSCLK_DPLL_HP_CLK4MHZ_1US_CNT_VAL	clk_dig frequency = 4MHz
CY_SYSCLK_DPLL_HP_CLK10MHZ_1US_CNT_VAL	clk_dig frequency = 10MHz
CY_SYSCLK_DPLL_HP_CLK15MHZ_1US_CNT_VAL	clk_dig frequency = 15MHz
CY_SYSCLK_DPLL_HP_CLK20MHZ_1US_CNT_VAL	clk_dig frequency = 20MHz
CY_SYSCLK_DPLL_HP_CLK30MHZ_1US_CNT_VAL	clk_dig frequency = 30MHz
CY_SYSCLK_DPLL_HP_CLK40MHZ_1US_CNT_VAL	clk_dig frequency = 40MHz
CY_SYSCLK_DPLL_HP_CLK45MHZ_1US_CNT_VAL	clk_dig frequency = 45MHz
CY_SYSCLK_DPLL_HP_CLK50MHZ_1US_CNT_VAL	clk_dig frequency = 50MHz