cy_stc_dpll_hp_config_t Struct Reference

Description

Structure containing information for configuration of a DPLL-HP.

Note

This structure is available only for CAT1D devices.

Data Fields
uint8_t	nDiv
	CONFIG register, NDIV bits, Ratio between DCO frequency and reference frequency.
uint8_t	pDiv
	CONFIG register, PDIV bits, Pre-Divider for scaling the reference frequency.
uint8_t	kDiv
	CONFIG register, KDIV bits, Post-Divider.
cy_en_fll_pll_output_mode_t	outputMode
	CONFIG register, BYPASS_SEL bits.
bool	pllEn
	CONFIG register, ENABLE bits, Master Enable for PLL.
uint32_t	nDivFract
	CONFIG2 register, NDIV_FRACT bits, N-divider division factor.
cy_en_wait_mode_select_t	freqModeSel
	CONFIG2 register, MODE_SEL bits, Selects the waiting time for Power Initialization sequence.
uint8_t	ivrTrim
	CONFIG2 register, IVR_TRIM bits, Trim value for the Regulated Voltage.
bool	clkrSel
	CONFIG3 register, CLKR_SEL bit, Select re-timed reference clock.
bool	fdsmSel
	CONFIG3 register, FDSM_SEL bit, DSM clock division select, true - div_by_2, false - div_by_4.
uint8_t	alphaCoarse
	CONFIG4 register, LF_LC_ALPHA bits, Alpha value of the coarse filter.
uint8_t	betaCoarse
	CONFIG4 register, LF_LC_BETA bits, Beta value of the coarse filter.
uint8_t	flockThresh
	CONFIG4 register, FLOCK_EN_THRESH bits, PQDIFF threshold under which FINE Filtering gets enabled.
uint8_t	flockWait
	CONFIG4 register, FLOCK_WAITPER bits, Period over which flock_en_thresh must be met in order for FINE Filtering enabling.
uint8_t	flockLkThres
	CONFIG4 register, FLOCK_LK_THRESH bits, PQDIFF threshold under which DLL asserts Freq LOCK.
uint8_t	flockLkWait
	CONFIG4 register, FLOCK_LK_WAITPER bits, Period over which flock_en_thresh must be met in order for Freq Locking.
uint8_t	flockObs
	CONFIG4 register, FLOCK_OBSWIN bits, Period over which PQDIFF is computed/observed.
uint8_t	alphaExt
	CONFIG5 register, LF_ALPHA bits, External Alpha value.
uint8_t	betaExt
	CONFIG5 register, LF_BETA bits, External Beta value.
bool	lfEn
	CONFIG5 register, LF_SET_PARAMS bit, enable for external loop filter control (alpha and beta values)
uint16_t	dtCal
	CONFIG5 register, DUTY CAL circuit status.
uint16_t	tmodFreq
	TRIGMOD register, TRIMOD_FREQ bits, Triangular-Frequency Modulation: modulation frequency.
uint16_t	tmodGrad
	TRIGMOD register, TRIMOD_GRD bits, Triangular-Frequency Modulation: modulation gradient.
uint32_t	tmodRate
	TRIGMOD2 register, TRIMOD_RATE bits, Triangular-Frequency Modulation Rate.
bool	tmodEn
	TRIGMOD2 register, TRIMOD_EN bit, Triangular-Frequency Modulation enable.
bool	tmodStop
	TRIGMOD2 register, TRIMOD_STP bit, Triangular-Frequency Modulation stop.
bool	pllLocked
	STATUS register, LOCKED bits, PLL Lock Indicator.
bool	pllUnlock
	STATUS register, UNLOCK_OCCURRED bit, Sets whenever the PLL Lock bit goes low, and stays set until cleared by firmware.
bool	lockDetReset
	STATUS register, LOCKDET_RES bit, Restart lock detector.
bool	lockDetRstAck
	STATUS register, LOCKDET_RES_ACK bit, Acknowledgement for lock detection restart.
uint8_t	dcCalDelta
	DUTYCAL_CTRL register, DELTA bits, Margins for the duty cycle calibration error.
bool	dcRatioStatus
	DUTYCAL_CTRL register, RATIO_OK bit, Status of the duty calibration ratio.
bool	dcStatus
	DUTYCAL_CTRL register, OK bit, Status of the duty calibration.
uint16_t	dcTarget
	DUTYCAL_CTRL register, TARGET bits, Duty cycle target.
bool	dcEnRingOsc
	DUTYCAL_CTRL register, CTRL_RG_EN bit, Enables ring oscillator for duty cycle digitization.
bool	dcEn
	DUTYCAL_CTRL register, EN bit, Enables duty cycle calibration.