CAT2 Peripheral Driver Library
SysClk (System Clock)

General Description

The System Clock (SysClk) driver contains the API for configuring system and peripheral clocks.

The functions and other declarations used in this driver are in cy_sysclk.h. You can include cy_pdl.h to get access to all functions and declarations in the PDL.

Firmware uses the API to configure, enable, or disable a clock.

The clock system includes a variety of resources that can vary per device, including:

Consult the Technical Reference Manual for your device for details of the clock system.

Configuration Considerations

The availability of clock functions depend on the availability of the chip resources that support those functions. Consult the device TRM before attempting to use these functions.

Usually the default clock configuration is IMO (24 MHz) -> ClkHf (24 MHz) -> SysClk (24 MHz)

The example of ECO -> HFCLK clock initialization:

/* The parameters of the ECS-33B crystal which is soldered on the
* CY8CKIT-045S (PSOC 4500S) board:
#define ECO_FREQ (24000000UL) /* The frequency in Hz */
#define ECO_CLOAD (30UL) /* The load capacitance in pF */
#define ECO_ESR (40UL) /* The equivalent series resistance in Ohms */
#define ECO_DRV_LVL (200UL) /* The maximal drive level in uW */
/* Configure the ECO GPIOs for CY8CKIT-045S (PSOC 4500S) */
/* Configure the ECO */
/* insert error handling here */
/* Enable the ECO with a timeout of 10 milliseconds */
/* insert error handling here */
/* Set EXCO as HFCLK clock source (the PLL is bypassed by default if disabled) */
/* insert error handling here */
/* Now CPU is running from the precise 24MHz from ECO */

The example of ECO -> PLL -> HFCLK clock initialization (taking into account the previous code snippet):

/* The PLL input is connected to the ECO by default */
.inputFreq = ECO_FREQ,
.outputFreq = 28000000UL /* The desired PLL frequency is 28 MHz */
if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllConfigure(0UL, &pllConfig))
/* insert error handling here */
Cy_SysLib_SetWaitStates(pllConfig.outputFreq / 1000000UL); /* Update WaitStates before increasing the ClkHf frequency */
/* Enable the PLL with a timeout of 250 microseconds */
/* insert error handling here */
/* The ClkHf is already switched to the EXCO and the PLL bypass is AUTO by default, so now the CPU is running from the ECO->PLL chain */

Low power modes may limit the maximum clock frequency. Refer to the SysPm driver and the TRM for details.

More Information

Refer to the technical reference manual (TRM) and the device datasheet.


VersionChangesReason for Change
3.0 Removed the legacy deprecated interfaces. PDL major revision.
2.20 The implementation of the Cy_SysClk_ClkHfSetSource function is updated. Memory consumption optimization.
Update the paths to the code snippets. PDL structure update.
Minor documentation updates. Code snippets were updated. Documentation enhancement.
2.10 Added the Cy_SysClk_PeriphSetFrequency API function API improvement
Added API for the Clock Supervision Block (CSV), Programmable Delay Block (PGM_DELAY) and Interrupts features New features support for PSoC 4500S and 4100S Max devices
Minor documentation updates. Code snippets were updated. Documentation enhancement.
2.0 Added the Cy_SysClk_DeepSleepCallback and Cy_SysClk_RegisterCallback functions Power management performance enhancement, see Low Power Callback
The next functions are changed: Cy_SysClk_ExtClkSetFrequency and Cy_SysClk_ExtRefSetFrequency - now there are opportunities to set a zero frequency which means the clock signal is disabled Clock system management enhancement
The next API are changed: cy_en_sysclk_clkhf_src_t and cy_en_sysclk_pll_bypass_t, the backward compatibility of the Cy_SysClk_ClkHfSetSource and Cy_SysClk_PllBypass functions is preserved, however the deprecated interface items are strongly not recommended for new designs Clock switching management bugs fixes
The Cy_SysClk_PllConfigure is changed do that the PLL output frequency could never overcome 48MHz Documentation improvements, bug fixes
Updated the Cy_SysClk_PllGetFrequency() function - now it returns a more precise result Usability improvement
Updated the Cy_SysClk_PllSetSource() and Cy_SysClk_ClkPumpSetSource functions - now they check the source validness even it is already connected Usability improvement
Updated the Cy_SysClk_PllDisable() function Code optimization
Updated the Cy_SysClk_WcoEnable() function - now the WCO startup delay recommended by the TRM is supported Performance improvement
The external PLL reference clock (EXTREF) frequency maximum is reduced to 48MHz Bug fix
The external clock input (EXTCLK) frequency minimum is reduced to 0MHz Bug fix
The external crystal oscillator (ECO) frequency maximum is reduced to 33.33MHz Bug fix
Updated the WCO documentation, especially the Bypass feature, see Bypass mode Documentation improvement
Minor documentation updates Documentation enhancement
1.20 Fixed the Cy_SysClk_ImoLock function to properly lock IMO. Defect fix.
1.10 New feature is added: external reference signal for PLL.
New items: CY_SYSCLK_PLL_SRC_EXTREF, Cy_SysClk_ExtRefSetFrequency and Cy_SysClk_ExtRefGetFrequency
Updated functions: Cy_SysClk_PllSetSource and Cy_SysClk_PllGetFrequency.
Added support of PSoC 4500S device EXCO block.
The implementation of Cy_SysClk_ExtClkSetFrequency, Cy_SysClk_IloCompensate, Cy_SysClk_EcoConfigure, Cy_SysClk_PllSetSource, Cy_SysClk_PllConfigure, Cy_SysClk_ClkHfSetSource, Cy_SysClk_ClkHfGetSource and Cy_SysClk_ClkHfGetFrequency functions is updated. Bug fixing and code optimization.
1.0 Initial version

API Reference

 General Enumerated Types
 Internal Main Oscillator (IMO)
 The Internal Main Oscillator (IMO) is a primary clock source for the CPU core and most of the peripherals.
 External Clock Source (EXTCLK)
 The External Clock Source (EXTCLK) is a clock source routed into PSoC through a GPIO pin.
 External PLL Reference Clock Source (EXTREF)
 The External PLL Reference Clock Source (EXTREF) is a clock source routed into PSoC through a GPIO pin.
 External Crystal Oscillator (ECO)
 The External Crystal Oscillator (ECO) is a clock source that consists of an oscillator circuit that drives an external crystal through its dedicated ECO pins.
 Phase Locked Loop (PLL)
 The PLL is a clock generation circuit that can be used to produce a higher frequency clock from a reference clock.
 Internal Low-Speed Oscillator (ILO)
 The ILO operates with no external components and outputs a clock signal at roughly 40 kHz.
 Watch Crystal Oscillator (WCO)
 The WCO is a highly accurate 32.768 kHz clock source capable of operating in all power modes.
 High-Frequency Clock
 The high frequency clock HFCLK is a source for the system clock for CPU and the peripheral clock dividers.
 Peripherals Clock Dividers
 There are multiple peripheral clock dividers that, in effect, create multiple separate peripheral clocks:
 System Clock
 The system clock is the source clock for CPU core (Cortex-M0+ in PSoC 4).
 Pump Clock
 The pump clock is a clock source used to provide analog precision in low voltage applications.
 Clock Supervision Block (CSV)
 The clock supervision block uses a reference clock (IMO clock) to check that a monitored clock (clk_exco) is within an allowed frequency window.
 Programmable Delay Block (PGM_DELAY)
 The PGM_DELAY block is a 16-bit down counter clocked by IMO clock and being triggered by the CSV.
 This API is to manage a few interrupt sources within the EXCO block.
 Low Power Callback
 Entering and exiting low power modes require compatible clock configurations to be set before entering low power and restored upon wakeup and exit.