WDT (Watchdog Timer)

The Watchdog timer (WDT) has a 16-bit (or 32-bit resolution for PSOC4 HVMS/PA devices) free-running up-counter with programmable limit values. More...

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Detailed Description

The Watchdog timer (WDT) has a 16-bit (or 32-bit resolution for PSOC4 HVMS/PA devices) free-running up-counter with programmable limit values.

The functions and other declarations used in this driver are in cy_wdt.h. You can include cy_pdl.h to get access to all functions and declarations in the PDL.

The WDT can issue counter match interrupts, and a device reset if its interrupts are not handled. Use the Watchdog timer for two main purposes:

The First use case is recovering from a CPU or firmware failure. A timeout period is set up in the Watchdog timer, and if a timeout occurs, the device is reset (WRES).
The Second use case is to generate periodic interrupts.

You can use the WDT to generate periodic interrupts. However, the Internal Low-Speed Oscillator (ILO) (or Low-Frequency Clock for PSOC4 HVMS/PA devices) is the clock source for the WDT, so its accuracy should be considered. Use the ILO compensation (Cy_SysClk_IloCompensate()) technique to increase ILO accuracy or use Clock Calibration together with Clock Trim (IMO, PILO) technique to increase Low-Frequency Clock accuracy for PSOC4 HVMS/PA devices.
Other options may provide a more precise periodic interrupt. See WDC (Watchdog Counters) (using Watch Crystal Oscillator (WCO) as clock source) or SysTick (ARM System Timer) (in active power mode).

Note

The WDC (Watchdog Counters) and Watch Crystal Oscillator (WCO) not applicable for PSOC4 HVMS/PA.

A "reset cause" register exists, and the firmware should check this register at a start-up Cy_SysLib_GetResetReason(). An appropriate action can be taken if a WRES reset is detected.

The user's firmware periodically resets the timeout period (clears or "feeds" the watchdog) before a timeout occurs. If the firmware fails to do so, that is considered to be a CPU crash or a firmware failure, and the reason for a device reset. The WDT can generate an interrupt instead of a device reset. The Interrupt Service Routine (ISR) can handle the interrupt either as a periodic interrupt, or as an early indication of a firmware failure and respond accordingly. However, it is not recommended to use the WDT for periodic interrupt generation. The WDC (Watchdog Counters) can be used to generate periodic interrupts if such are presented in the device.

Functional Description

The WDT generates an interrupt when the count value in the counter equals the configured match value.

Note that the counter is not reset on a match. In such case the WDT reset period is: WDT_Reset_Period = ILO_Period * (2*2^(16-IgnoreBits) + MatchValue); When the counter reaches a match value, it generates an interrupt and then keeps counting up until it overflows and rolls back to zero and reaches the match value again, at which point another interrupt is generated.

To use a WDT to generate a periodic interrupt, the match value should be incremented in the ISR. As a result, the next WDT interrupt is generated when the counter reaches a new match value.

You can also reduce the entire WDT counter period by specifying the number of most significant bits that are ignored in the WDT counter. For example, if the Cy_WDT_SetIgnoreBits() function is called with parameter 3, the WDT counter becomes a 13-bit free-running up-counter.

PSOC4 HVMS/PA Functional Design Details

For PSOC4 HVMS/PA devices, the WDT can be configured to act on different counter limits where a reset is triggered if the watchdog is not serviced before the upper limit. In the window mode, a reset is triggered if the servicing occurs before the lower limit is reached. The warning limit triggers an interrupt to request servicing. Each of these actions can be activated independently. The WDT is enabled and specific registers are locked by default. An unlocking sequence is required to prevent accidental accesses. The WDT operates in active, sleep, and deepsleep modes. After a WDT reset the device returns to active mode.

PSOC4 HVMS/PA Basic WDT functional diagram

Register Locking

Note

Applicable to PSOC4 HVMS/PA only.

You can prevent accidental corruption of the WDT configuration by calling the Cy_WDT_Lock() function. When the WDT is locked, any writing to the WDT_*, CLK_ILO_CONFIG, CLK_SELECT.LFCLK_SEL, and CLK_TRIM_ILO_CTL registers is ignored. Call the Cy_WDT_Unlock() function to allow registers modification, mentioned above.

Note

The WDT lock state is not retained during system Deep Sleep. After the wakeup from system Deep Sleep the WDT is locked.

Power Modes

WDT can operate in all possible low power modes.

In CPU Active mode, an interrupt request from the WDT is sent to the CPU. In CPU Sleep, CPU Deep Sleep mode, the CPU subsystem is powered down, so the interrupt request from the WDT is sent directly to the WakeUp Interrupt Controller (WIC) which will then wake up the CPU. The CPU then acknowledges the interrupt request and executes the ISR.

Clock Source

The WDT is clocked by the ILO (or Low-Frequency Clock for PSOC4 HVMS/PA devices). The WDT must be disabled before disabling the ILO (or Low-Frequency Clock). Need to consider ILO (or Low-Frequency Clock) accuracy while configuring WDT intervals to make sure that unwanted device resets do not occur on some devices.

Refer to the device datasheet for more information on the oscillator accuracy.

Clearing WDT

The ILO (or Low-Frequency Clock) clock is asynchronous to the SysClk. Therefore it generally takes three ILO (or Low-Frequency Clock) cycles for WDT register changes to come into effect. It is important to remember that a WDT should be cleared at least four cycles (3 + 1 for sure) before a timeout occurs, especially when small match values / low-toggle bit numbers are used.

Warning

It may happen that a WDT reset can be generated faster than a device start-up. To prevent this, calculate the start-up time and WDT reset time. The WDT reset time should be always greater than device start-up time.

Reset Detection

Use the Cy_SysLib_GetResetReason() function to detect whether the WDT has triggered a device reset.

Interrupt Configuration

If the WDT is configured to generate an interrupt, pending interrupts must be cleared within the ISR (otherwise, the interrupt will be generated continuously). A pending interrupt to the WDT block must be cleared by calling the Cy_WDT_ClearInterrupt() function. The call to the function will clear the unhandled WDT interrupt counter.

Use the WDT ISR as a timer to trigger certain actions and to change a next WDT match or limit value.

Ensure that the interrupts from the WDT are passed to the CPU to avoid unregistered interrupts. Unregistered WDT interrupts result in a continuous device reset. To avoid this, call Cy_WDT_UnmaskInterrupt(). After that, call the WDT API functions for interrupt handling/clearing.

It is not recommended to reset the watchdog counter in the WDT interrupt service routine (ISR), if WDT is being used as a reset source to protect the system against crashes. If necessary, use the warning interrupt to set a flag in the ISR. Local processing loops can observe that flag and break out of their loop. This allows the main loop to reach the servicing code (and clear the flag for the next pass through the main loop).

Configuration Considerations

To start the WDT, make sure that ILO (or Low-Frequency Clock) is enabled. After the ILO (or Low-Frequency Clock) is enabled, ensure that the watchdog reset is disabled by calling the Cy_WDT_Disable() function. Set the WDT match value by calling Cy_WDT_SetMatch() with the required match value. If needed, set the ignore bits for reducing the WDT counter period by calling Cy_WDT_SetIgnoreBits() function. After the WDT configuration is set, call Cy_WDT_Enable().

Note

The watchdog counter is a free-running counter that cannot be disabled.

Enable a WDT if the power supply can produce sudden brownout events that may compromise the CPU functionality. This ensures that the system can recover after a brownout.

When the WDT is used to protect against system crashes, the WDT interrupt should be cleared by a portion of the code that is not directly associated with the WDT interrupt. Otherwise, it is possible that the main firmware loop has crashed or is in an endless loop, but the WDT interrupt vector continues to operate and service the WDT. The user should:

• Feed the watchdog by clearing the interrupt bit regularly in the main body of the firmware code.
• Guarantee that the interrupt is cleared at least once every WDT period.
• Use the WDT ISR only as a timer to trigger certain actions and to change the next match value.

Use case 1. Configure the WDT for periodic interrupt.

Set parameters of the WDT.

/* The number of WDT ticks for the 1s interrupt generation, 
* at the ILO clock frequency of 40 kHz. 
*/
#define WDT_TICKS_40000                         (40000U)
/* WDT ignore bits */
#define WDT_IGNORE_BITS_0                       (0U)

Create an interrupt config structure and interrupt handler.

/* Assign WDT interrupt number and priority */
#define WDT_INTR_NUM                            ((IRQn_Type) srss_interrupt_wdt_IRQn)
#define WDT_INTR_PRIORITY                       (3U)

/* Populate configuration structure */
cy_stc_sysint_t wdtIntrConfig =
{
    .intrSrc      = WDT_INTR_NUM,
    .intrPriority = WDT_INTR_PRIORITY,
};

/* Interrupt handler */
void WDT_Isr(void)
{
    /* To adjust the WDT interrupt period using the match value, update
    * that match value in every WDT interrupt by assigning a new match value. 
    * Calculate the new match value: 
    * */
    uint16_t setValue = (uint16_t) Cy_WDT_GetCount() + (uint16_t) WDT_TICKS_40000;

    /* Update match value */
    Cy_WDT_SetMatch(setValue);

    /* Clear WDT interrupt */
    Cy_WDT_ClearInterrupt();
}

Hook the interrupt service routine and enable interrupt than config the WDT.

void wdtConfig_useCase_1(void)
{
    /* Disable the system reset generation. After a device reset, reset by WDT is
    * enabled by default. 
    */
    Cy_WDT_Disable();

    /* Hook interrupt service routine and enable interrupt */
    (void) Cy_SysInt_Init(&wdtIntrConfig, &WDT_Isr);
    NVIC_EnableIRQ(WDT_INTR_NUM);

    /* Config WDT: set the match value - 40000 and ignore bits - 0.*/
    Cy_WDT_SetMatch(WDT_TICKS_40000);
    Cy_WDT_SetIgnoreBits(WDT_IGNORE_BITS_0);

    /* Clear the interrupt */
    Cy_WDT_ClearInterrupt();

    /* Unmask WDT interrupt */
    Cy_WDT_UnmaskInterrupt();
}

Note

Additionally, global interrupts should be enabled.

Before the WDT initialization, ensure that the WDT clock source is enabled. Refer to Internal Low-Speed Oscillator (ILO) of SysClk driver documentation.

Use case 2. Configure the WDT for the system reset generation after a configurable interval.

In this case, the WDT resets every third WDT event of the system(1.2287s at ILO 40kHz).

As part of this code, the snippet uses the formula from the Functional Description .

/* The number of WDT ticks */
#define WDT_TICKS_16383                         (16383U)
/* WDT ignore bits */
#define WDT_IGNORE_BITS_2                       (2U)

void wdtConfig_useCase_2(void)
{
    /* Disable the system reset generation. After a device reset, reset by WDT is
    * enabled by default. 
    */
    Cy_WDT_Disable();

    /* Config WDT: set the match value to 16383 because this value
    * is equivalent to a timer period with 2 ignore bits.
    * Set ignore bits to 2. Based on these parameters, 
    * the WDT_Reset_Period = 0,000025 * (2 * 2^14 + 16383) = 1.2287s.
    */
    Cy_WDT_SetMatch(WDT_TICKS_16383);
    Cy_WDT_SetIgnoreBits(WDT_IGNORE_BITS_2);

    /* Enables the watchdog timer reset generation. */
    Cy_WDT_Enable();
}

Use case 3. The WDT counter in interrupt mode.

Note

Applicable to PSOC4 HVMS/PA only.

The timing diagram below shows the behavior of the WDT counter in interrupt mode. LOWER and UPPER actions are disabled. An interrupt is issued each time the counter matches the WARN_LIMIT. The interrupt period is calculated by 2^32 x LFCLK clock cycles. The WDT counter could be cleared (serviced) in two ways:

• manually by calling Cy_WDT_SetService() function
• automatically by calling Cy_WDT_SetAutoService() function

WDT counter operation with WARN interrupt only

Set parameters of the WDT.

/* The number of WDT ticks for the 1s interrupt generation */
#if defined(CY_CFG_SYSCLK_PILO_ENABLED)
    /* Enabled ILO clock 40 kHz */
    #define WDT_TICKS   (CY_SYSCLK_ILO_FREQ)
#else
    /* Enabled PILO clock 32.768 kHz*/
    #define WDT_TICKS   (CY_SYSCLK_PILO_FREQ)
#endif

Create an interrupt config structure and interrupt handler.

/* Assign WDT interrupt number and priority */
#define WDT_INTR_NUM                            ((IRQn_Type) srss_wdt_irq_IRQn)
#define WDT_INTR_PRIORITY                       (3U)

/* Populate configuration structure */
cy_stc_sysint_t wdtIntrConfig =
{
    .intrSrc      = WDT_INTR_NUM,
    .intrPriority = WDT_INTR_PRIORITY,
};

/* Interrupt handler */
void WDT_Isr(void)
{
    /* Clear WDT interrupt.
    Clearing the interrupt does not reset the watchdog counter. */
    Cy_WDT_ClearInterrupt();
}

Hook the interrupt service routine and enable interrupt than config the WDT.

    /* The Watchdog timer should be unlocked before being disabled. */
    if(Cy_WDT_Locked())
    {
        Cy_WDT_Unlock();
    }
    /* Disable the WDT. After a device reset, WDT is enabled by default. */
    if(Cy_WDT_IsEnabled())
    {
        Cy_WDT_Disable();
        while(Cy_WDT_IsEnabled())
        {
            /* Do nothing. Wait until the WDT Disable takes effect.
            May take up to three clk_lf cycles to take effect. */
        }
    }

    /* Hook interrupt service routine and enable interrupt */
    cy_en_sysint_status_t sysintStatus = Cy_SysInt_Init(&wdtIntrConfig, WDT_Isr);
    if (CY_SYSINT_SUCCESS != sysintStatus)
    {
        /* Insert the error handling here */
        CY_ASSERT(0);
    }
    NVIC_EnableIRQ(WDT_INTR_NUM); /* Enable the interrupt. */

    /* Set LOWER_LIMIT to "0" and LOWER_ACTION to None */
    Cy_WDT_SetLowerLimit(CY_WDT_DEFAULT_LOWER_LIMIT);
    Cy_WDT_SetLowerAction(CY_WDT_LOW_UPPER_LIMIT_ACTION_NONE);

    Cy_WDT_SetWarnLimit(WDT_TICKS); /* 32 768 (~1 sec when clk_lf = 32KHz) */
    /* Set warn action to trigger an interrupt */
    Cy_WDT_SetWarnAction(CY_WDT_WARN_ACTION_INT);

    Cy_WDT_SetUpperLimit(3 * WDT_TICKS); /* 98 304 (~3 sec when clk_lf = 32KHz) */
    Cy_WDT_SetUpperAction(CY_WDT_LOW_UPPER_LIMIT_ACTION_NONE);

    /* Set automatically service when the count value reaches WARN_LIMIT.
    This allows creation of a periodic interrupt if this counter is not needed as a watchdog.
    This configuration is ignored when LOWER_ACTION or when UPPER_ACTION is set to trigger a reset. */
    Cy_WDT_SetAutoService(CY_WDT_ENABLE);

    Cy_WDT_Enable();

    /* Lock WDT configuration changes. */
    Cy_WDT_Lock();

    /* Clear the interrupt */
    Cy_WDT_ClearInterrupt();

    /* Unmask interrupts from the WDT, they are passed to CPU */
    Cy_WDT_UnmaskInterrupt();

Note

Additionally, global interrupts should be enabled.

Before the WDT initialization, ensure that the WDT clock source is enabled. Refer to Low-Frequency Clock of SysClk driver documentation.

Use case 4. Configure the WDT counter in window mode.

Note

Applicable to PSOC4 HVMS/PA only.

The timing diagram below shows the behavior of the WDT counter in window mode. The timing diagram shows all scenarios of the WDT operation while LOWER_ACTION, WARN_ACTION, and UPPER_ACTION are enabled.

• Counter is serviced between LOWER_LIMIT and WARN_LIMIT: This is the regular behavior of the WDT. No WARN interrupt is issued and no RESET is done.
• Counter is serviced between WARN_LIMIT and UPPER_LIMIT: The service is done late, a WARN interrupt is issued but no RESET is done.
• Counter is not serviced at all: WARN interrupt is issued but the SERVICE bit is not set. When the counter reaches the UPPER_LIMIT a reset is executed.
• Counter is serviced before the LOWER_LIMIT is reached: The counter is serviced too early; a reset is executed because the counter is cleared outside of the window.

WDT counter operation in window mode

Note

The timing diagram illustrates the different scenarios with or without servicing the watchdog counter. It does not consider the WDT configuration, especially after a reset.

More Information

For more information on the WDT peripheral, refer to the technical reference manual (TRM).

Changelog

Version	Changes	Reason for Change
1.10	Added support for PSOC4 HVMS/PA platform. Updated APIs to incorporate PSOC4 HVMS/PA platform configuration. Documentation enhancement. Provided code snippets.	New device support.
1.0.3	Updated code snippets.	Documentation enhancement.
1.0.2	Update the paths to the code snippets.	PDL structure update.
1.0.1	Code snippets added.	Documentation enhancement.
1.0	Initial version