Functions

Functions
cy_en_sysclk_status_t	Cy_SysClk_PeriphSetDivider (cy_en_sysclk_divider_types_t dividerType, uint32_t dividerNum, uint32_t dividerValue)
	Sets one of the programmable clock dividers. More...
uint32_t	Cy_SysClk_PeriphGetDivider (cy_en_sysclk_divider_types_t dividerType, uint32_t dividerNum)
	Returns the integer divider value for the specified divider. More...
cy_en_sysclk_status_t	Cy_SysClk_PeriphSetFracDivider (cy_en_sysclk_divider_types_t dividerType, uint32_t dividerNum, uint32_t dividerIntValue, uint32_t dividerFracValue)
	Sets one of the programmable clock dividers. More...
void	Cy_SysClk_PeriphGetFracDivider (cy_en_sysclk_divider_types_t dividerType, uint32_t dividerNum, uint32_t *dividerIntValue, uint32_t *dividerFracValue)
	Reports the integer and fractional parts of the divider. More...
cy_en_sysclk_status_t	Cy_SysClk_PeriphAssignDivider (en_clk_dst_t periphNum, cy_en_sysclk_divider_types_t dividerType, uint32_t dividerNum)
	Assigns a programmable divider to a selected IP block, such as a TCPWM or SCB. More...
cy_en_sysclk_status_t	Cy_SysClk_PeriphEnableDivider (cy_en_sysclk_divider_types_t dividerType, uint32_t dividerNum)
	Enables the selected divider. More...
cy_en_sysclk_status_t	Cy_SysClk_PeriphDisableDivider (cy_en_sysclk_divider_types_t dividerType, uint32_t dividerNum)
	Disables a selected divider. More...
cy_en_sysclk_status_t	Cy_SysClk_PeriphEnablePhaseAlignDivider (cy_en_sysclk_divider_types_t dividerType, uint32_t dividerNum, cy_en_sysclk_divider_types_t dividerTypePA, uint32_t dividerNumPA)
	First disables a selected divider (Cy_SysClk_PeriphDisableDivider), then aligns that divider to another programmable divider, and enables the selected divider. More...
bool	Cy_SysClk_PeriphDividerIsEnabled (cy_en_sysclk_divider_types_t dividerType, uint32_t dividerNum)
	Reports the enabled/disabled state of the selected divider. More...
uint32_t	Cy_SysClk_PeriphGetFrequency (cy_en_sysclk_divider_types_t dividerType, uint32_t dividerNum)
	Reports the frequency of the output of a given peripheral divider. More...
uint32_t	Cy_SysClk_PeriphSetFrequency (cy_en_sysclk_divider_types_t dividerType, uint32_t dividerNum, uint32_t frequency)
	Calculates the dividing factor for the desired frequency, applies it to the specified peripheral divider and reports the achieved frequency. More...
__STATIC_INLINE uint32_t	Cy_SysClk_PeriphGetAssignedDivider (en_clk_dst_t periphNum)
	Reports which clock divider is assigned to a selected IP block. More...

Detailed Description

Function Documentation

Cy_SysClk_PeriphSetDivider()

cy_en_sysclk_status_t Cy_SysClk_PeriphSetDivider	(	cy_en_sysclk_divider_types_t	dividerType,
		uint32_t	dividerNum,
		uint32_t	dividerValue
	)

Sets one of the programmable clock dividers.

This is only used for integer dividers. Use Cy_SysClk_PeriphSetFracDivider for setting factional dividers.

Precondition

If the specified clock divider is already enabled - it should be disabled prior to use this function by Cy_SysClk_PeriphDisableDivider.

Parameters

dividerType	specifies which type of divider to use; cy_en_sysclk_divider_types_t
dividerNum	the divider number.
dividerValue	divider value Causes integer division of (divider value + 1), or division by 1 to 256 (8-bit divider) or 1 to 65536 (16-bit divider).

Returns

cy_en_sysclk_status_t

Function Usage

    /* Scenario: 16-bit peripheral divider #2 needs to be incremented by 1. */

    uint32_t periDiv = Cy_SysClk_PeriphGetDivider(CY_SYSCLK_DIV_16_BIT, 2UL);
    if (CY_SYSCLK_SUCCESS != Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_16_BIT, 2UL, periDiv + 1UL))
    {
        /* Insert error handling */
    }

Cy_SysClk_PeriphGetDivider()

uint32_t Cy_SysClk_PeriphGetDivider	(	cy_en_sysclk_divider_types_t	dividerType,
		uint32_t	dividerNum
	)

Returns the integer divider value for the specified divider.

One works for integer dividers. Use Cy_SysClk_PeriphGetFracDivider to get the fractional divider value

Parameters

dividerType	specifies which type of divider to use; cy_en_sysclk_divider_types_t
dividerNum	specifies which divider of the selected type to configure

Returns

The divider value. The integer division done is by (divider value + 1), or division by 1 to 256 (8-bit divider) or 1 to 65536 (16-bit divider).

Function Usage

    /* Scenario: 16-bit peripheral divider #2 needs to be incremented by 1. */

    uint32_t periDiv = Cy_SysClk_PeriphGetDivider(CY_SYSCLK_DIV_16_BIT, 2UL);
    if (CY_SYSCLK_SUCCESS != Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_16_BIT, 2UL, periDiv + 1UL))
    {
        /* Insert error handling */
    }

Cy_SysClk_PeriphSetFracDivider()

cy_en_sysclk_status_t Cy_SysClk_PeriphSetFracDivider	(	cy_en_sysclk_divider_types_t	dividerType,
		uint32_t	dividerNum,
		uint32_t	dividerIntValue,
		uint32_t	dividerFracValue
	)

Sets one of the programmable clock dividers.

This function should only be used for fractional clock dividers.

Precondition

If the specified clock divider is already enabled - it should be disabled prior to use this function by Cy_SysClk_PeriphDisableDivider.

Parameters

dividerType	specifies which type of divider to use; cy_en_sysclk_divider_types_t
dividerNum	specifies which divider of the selected type to configure
dividerIntValue	the integer divider value The source of the divider is peri_clk, which is a divided version of HFCLK. The divider value causes integer division of (divider value + 1), or division by 1 to 65536 (16-bit divider) or 1 to 16777216 (24-bit divider).
dividerFracValue	the fraction part of the divider The fractional divider can be 1-32, thus it divides the clock by 1/32 for each count. To divide the clock by 11/32nds set this value to 11.

Returns

cy_en_sysclk_status_t

Function Usage

    /* Scenario: 16-bit fractional peripheral divider #0 needs to increment its
                 fractional value by 2. */

    uint32_t divIntVal, divFracVal;

    Cy_SysClk_PeriphGetFracDivider(CY_SYSCLK_DIV_16_5_BIT, 0UL, &divIntVal, &divFracVal);
    if (CY_SYSCLK_SUCCESS != Cy_SysClk_PeriphSetFracDivider(CY_SYSCLK_DIV_16_5_BIT, 0UL, divIntVal, divFracVal + 2UL))
    {
        /* Insert error handling */
    }

Cy_SysClk_PeriphGetFracDivider()

void Cy_SysClk_PeriphGetFracDivider	(	cy_en_sysclk_divider_types_t	dividerType,
		uint32_t	dividerNum,
		uint32_t *	dividerIntValue,
		uint32_t *	dividerFracValue
	)

Reports the integer and fractional parts of the divider.

Parameters

dividerType	specifies which type of divider to use; cy_en_sysclk_divider_types_t
dividerNum	specifies which divider of the selected type to configure
*dividerIntValue	pointer to return integer divider value
*dividerFracValue	pointer to return fractional divider value

Returns

None. Loads pointed-to variables.

Function Usage

    /* Scenario: 16-bit fractional peripheral divider #0 needs to increment its
                 fractional value by 2. */

    uint32_t divIntVal, divFracVal;

    Cy_SysClk_PeriphGetFracDivider(CY_SYSCLK_DIV_16_5_BIT, 0UL, &divIntVal, &divFracVal);
    if (CY_SYSCLK_SUCCESS != Cy_SysClk_PeriphSetFracDivider(CY_SYSCLK_DIV_16_5_BIT, 0UL, divIntVal, divFracVal + 2UL))
    {
        /* Insert error handling */
    }

Cy_SysClk_PeriphAssignDivider()

cy_en_sysclk_status_t Cy_SysClk_PeriphAssignDivider	(	en_clk_dst_t	periphNum,
		cy_en_sysclk_divider_types_t	dividerType,
		uint32_t	dividerNum
	)

Assigns a programmable divider to a selected IP block, such as a TCPWM or SCB.

Parameters

periphNum	specifies the peripheral block en_clk_dst_t.
dividerType	specifies which type of divider to use; cy_en_sysclk_divider_types_t
dividerNum	specifies which divider of the selected type to configure

Returns

cy_en_sysclk_status_t

Function Usage

    /* Scenario: There is a need to set a precise baud rate for SCB3-based UART. For example take the 16.5-bit divider #0 */
    /* Check if the divider is enabled */
    bool divEnabled = Cy_SysClk_PeriphDividerIsEnabled(CY_SYSCLK_DIV_16_5_BIT, 0UL);

    /* If enabled - let's disable it before the divider factor changing */
    if (divEnabled)
    {
        if (CY_SYSCLK_SUCCESS != Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_16_5_BIT, 0UL))
        {
            /* Insert error handling */
        }
    }

    /* Assume we need UART baud rate 115200 and oversampling ratio 8 */
    uint32_t achievedFreq = Cy_SysClk_PeriphSetFrequency(CY_SYSCLK_DIV_16_5_BIT, 0UL, 8UL * 115200UL);
    /* Now the achievedFreq contains the real achieved peripheral clock divider output frequency */

    /* Get the current assigned divider */
    uint32_t currDiv = Cy_SysClk_PeriphGetAssignedDivider(PCLK_SCB3_CLOCK);
    /* Make the desired divider value to compare */
    uint32_t fracDiv = _VAL2FLD(CY_SYSCLK_PERI_DIV_TYPE, CY_SYSCLK_DIV_16_5_BIT) | _VAL2FLD(CY_SYSCLK_PERI_DIV_NUM, 0UL);

    if(currDiv != fracDiv)
    {
        /* Assign 16-bit divider #3 to source TCPWM CNT0 clock */
        if (CY_SYSCLK_SUCCESS != Cy_SysClk_PeriphAssignDivider(PCLK_SCB3_CLOCK, CY_SYSCLK_DIV_16_5_BIT, 0UL))
        {
            /* Insert error handling */
        }
    }

    /* Restore the divider's enable/disable state */
    if (divEnabled)
    {
        if (CY_SYSCLK_SUCCESS != Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_16_5_BIT, 0UL))
        {
            /* Insert error handling */
        }
    }

Cy_SysClk_PeriphEnableDivider()

cy_en_sysclk_status_t Cy_SysClk_PeriphEnableDivider	(	cy_en_sysclk_divider_types_t	dividerType,
		uint32_t	dividerNum
	)

Enables the selected divider.

Parameters

dividerType	specifies which type of divider to use; cy_en_sysclk_divider_types_t
dividerNum	specifies which divider of the selected type to configure

Note

This function also sets the phase alignment bits such that the enabled divider is aligned to clk_peri. See Cy_SysClk_PeriphDisableDivider() for information on how to phase-align a divider after it is enabled.

Function Usage

    /* Scenario: TCPWM CNT0 clock needs to be sourced from 16-bit divider #1 with
                 a value of 140. This clock must be aligned to Peri clock. */

    /* Assign 16-bit divider #1 to source TCPWM CNT0 clock */
    if (CY_SYSCLK_SUCCESS != Cy_SysClk_PeriphAssignDivider(PCLK_TCPWM_CLOCKS0, CY_SYSCLK_DIV_16_BIT, 1UL))
    {
        /* Insert error handling */
    }

    /* Set the 16-bit divider #1 value to 140 (139 + 1) */
    if (CY_SYSCLK_SUCCESS != Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_16_BIT, 1UL, 139UL))
    {
        /* Insert error handling */
    }

    /* Enable the 16-bit divider #1 */
    if (CY_SYSCLK_SUCCESS != Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_16_BIT, 1UL))
    {
        /* Insert error handling */
    }

Cy_SysClk_PeriphDisableDivider()

cy_en_sysclk_status_t Cy_SysClk_PeriphDisableDivider	(	cy_en_sysclk_divider_types_t	dividerType,
		uint32_t	dividerNum
	)

Disables a selected divider.

Parameters

dividerType	specifies which type of divider to use; cy_en_sysclk_divider_types_t.
dividerNum	specifies which divider of the selected type to configure.

Function Usage

    /* Scenario: 16-bit divider #1 is no longer needed and can be disabled. */
    if (CY_SYSCLK_SUCCESS != Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_16_BIT, 1UL))
    {
        /* Insert error handling */
    }

Cy_SysClk_PeriphEnablePhaseAlignDivider()

cy_en_sysclk_status_t Cy_SysClk_PeriphEnablePhaseAlignDivider	(	cy_en_sysclk_divider_types_t	dividerType,
		uint32_t	dividerNum,
		cy_en_sysclk_divider_types_t	dividerTypePA,
		uint32_t	dividerNumPA
	)

First disables a selected divider (Cy_SysClk_PeriphDisableDivider), then aligns that divider to another programmable divider, and enables the selected divider.

The divider to align to must already be enabled in order to align a divider to it.

Parameters

dividerType	specifies which type of divider to use; cy_en_sysclk_divider_types_t.
dividerNum	specifies which divider of the selected type to configure.
dividerTypePA	type of divider to phase-align to; cy_en_sysclk_divider_types_t.
dividerNumPA	divider number of type specified to phase align to.

Note

To phase-align a divider to hfclk, set dividerTypePA to 3 and dividerNumPA to 63.

Function Usage

    /* Scenario: 16-bit divider #1 needs to be aligned to 16-bit divider #0. */

    /* Set the 16-bit divider #1 value to 125 (124 + 1) */
    if (CY_SYSCLK_SUCCESS != Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_16_BIT, 1UL, 124UL))
    {
        /* Insert error handling */
    }

    if (CY_SYSCLK_SUCCESS != Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_16_BIT, 1UL))
    {
        /* Insert error handling */
    }

    /* Set the 16-bit divider #0 value to 2000 (1999 + 1) */
    if (CY_SYSCLK_SUCCESS != Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_16_BIT, 0UL, 1999UL))
    {
        /* Insert error handling */
    }

    if (CY_SYSCLK_SUCCESS != Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_16_BIT, 0UL))
    {
        /* Insert error handling */
    }

    /* Align the 16-bit divider #1 to the 16-bit divider #0 */
    if (CY_SYSCLK_SUCCESS != Cy_SysClk_PeriphEnablePhaseAlignDivider(CY_SYSCLK_DIV_16_BIT, 1UL, CY_SYSCLK_DIV_16_BIT, 0UL))
    {
        /* Insert error handling */
    }

Cy_SysClk_PeriphDividerIsEnabled()

bool Cy_SysClk_PeriphDividerIsEnabled	(	cy_en_sysclk_divider_types_t	dividerType,
		uint32_t	dividerNum
	)

Reports the enabled/disabled state of the selected divider.

Parameters

dividerType	specifies which type of divider to use; cy_en_sysclk_divider_types_t.
dividerNum	specifies which divider of the selected type to configure.

Returns

The enabled/disabled state;
false = disabled
true = enabled

Function Usage

    /* Scenario: There is a need to set a precise baud rate for SCB3-based UART. For example take the 16.5-bit divider #0 */
    /* Check if the divider is enabled */
    bool divEnabled = Cy_SysClk_PeriphDividerIsEnabled(CY_SYSCLK_DIV_16_5_BIT, 0UL);

    /* If enabled - let's disable it before the divider factor changing */
    if (divEnabled)
    {
        if (CY_SYSCLK_SUCCESS != Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_16_5_BIT, 0UL))
        {
            /* Insert error handling */
        }
    }

    /* Assume we need UART baud rate 115200 and oversampling ratio 8 */
    uint32_t achievedFreq = Cy_SysClk_PeriphSetFrequency(CY_SYSCLK_DIV_16_5_BIT, 0UL, 8UL * 115200UL);
    /* Now the achievedFreq contains the real achieved peripheral clock divider output frequency */

    /* Get the current assigned divider */
    uint32_t currDiv = Cy_SysClk_PeriphGetAssignedDivider(PCLK_SCB3_CLOCK);
    /* Make the desired divider value to compare */
    uint32_t fracDiv = _VAL2FLD(CY_SYSCLK_PERI_DIV_TYPE, CY_SYSCLK_DIV_16_5_BIT) | _VAL2FLD(CY_SYSCLK_PERI_DIV_NUM, 0UL);

    if(currDiv != fracDiv)
    {
        /* Assign 16-bit divider #3 to source TCPWM CNT0 clock */
        if (CY_SYSCLK_SUCCESS != Cy_SysClk_PeriphAssignDivider(PCLK_SCB3_CLOCK, CY_SYSCLK_DIV_16_5_BIT, 0UL))
        {
            /* Insert error handling */
        }
    }

    /* Restore the divider's enable/disable state */
    if (divEnabled)
    {
        if (CY_SYSCLK_SUCCESS != Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_16_5_BIT, 0UL))
        {
            /* Insert error handling */
        }
    }

Cy_SysClk_PeriphGetFrequency()

uint32_t Cy_SysClk_PeriphGetFrequency	(	cy_en_sysclk_divider_types_t	dividerType,
		uint32_t	dividerNum
	)

Reports the frequency of the output of a given peripheral divider.

Parameters

dividerType	specifies which type of divider to use; cy_en_sysclk_divider_types_t
dividerNum	specifies which divider of the selected type to configure

Returns

The frequency, in Hz.

Function Usage

    /* Scenario: SCB0 needs to be clocked at HFCLK/3. Need to confirm that the
                 set frequency on the chosen peripheral divider is correct.
                 HFCLK and the clocks leading up it are configured. */

    /* Set the HF clock divider to 2 */
    Cy_SysClk_ClkHfSetDivider(CY_SYSCLK_DIV_2);

    /* Assign 16-bit divider #0 to source SCB0 clock */
    (void)Cy_SysClk_PeriphAssignDivider(PCLK_SCB0_CLOCK, CY_SYSCLK_DIV_16_BIT, 0UL);

    /* Set the 16-bit divider #0 value to 3 (2 + 1) */
    (void)Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_16_BIT, 0UL, 2UL);

    /* Enable the 16-bit divider #0 */
    (void)Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_16_BIT, 0UL);

    /* Calculate the frequency seen at the output of 16-bit divider #0 */
    uint32_t scbFreq = Cy_SysClk_PeriphGetFrequency(CY_SYSCLK_DIV_16_BIT, 0UL);

    if(scbFreq == 0UL)
    {
        /* Could not calculate the frequency. Check that the clock source
           is correct and/or verify by enabling the SCB0. */
    }
    else
    {
        /* Check that the frequency is as expected. */
    }

Cy_SysClk_PeriphSetFrequency()

uint32_t Cy_SysClk_PeriphSetFrequency	(	cy_en_sysclk_divider_types_t	dividerType,
		uint32_t	dividerNum,
		uint32_t	frequency
	)

Calculates the dividing factor for the desired frequency, applies it to the specified peripheral divider and reports the achieved frequency.

Precondition

This function reuses Cy_SysClk_PeriphSetDivider/Cy_SysClk_PeriphSetFracDivider, so if the clock divider is already enabled - it should be disabled prior to use this function by Cy_SysClk_PeriphDisableDivider.

Parameters

dividerType	specifies which type of divider to use cy_en_sysclk_divider_types_t
dividerNum	specifies which divider of the selected type to configure
frequency	specifies the desired frequency, in Hz.

Returns

The achieved frequency, in Hz.

Function Usage

    /* Scenario: There is a need to set a precise baud rate for SCB3-based UART. For example take the 16.5-bit divider #0 */
    /* Check if the divider is enabled */
    bool divEnabled = Cy_SysClk_PeriphDividerIsEnabled(CY_SYSCLK_DIV_16_5_BIT, 0UL);

    /* If enabled - let's disable it before the divider factor changing */
    if (divEnabled)
    {
        if (CY_SYSCLK_SUCCESS != Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_16_5_BIT, 0UL))
        {
            /* Insert error handling */
        }
    }

    /* Assume we need UART baud rate 115200 and oversampling ratio 8 */
    uint32_t achievedFreq = Cy_SysClk_PeriphSetFrequency(CY_SYSCLK_DIV_16_5_BIT, 0UL, 8UL * 115200UL);
    /* Now the achievedFreq contains the real achieved peripheral clock divider output frequency */

    /* Get the current assigned divider */
    uint32_t currDiv = Cy_SysClk_PeriphGetAssignedDivider(PCLK_SCB3_CLOCK);
    /* Make the desired divider value to compare */
    uint32_t fracDiv = _VAL2FLD(CY_SYSCLK_PERI_DIV_TYPE, CY_SYSCLK_DIV_16_5_BIT) | _VAL2FLD(CY_SYSCLK_PERI_DIV_NUM, 0UL);

    if(currDiv != fracDiv)
    {
        /* Assign 16-bit divider #3 to source TCPWM CNT0 clock */
        if (CY_SYSCLK_SUCCESS != Cy_SysClk_PeriphAssignDivider(PCLK_SCB3_CLOCK, CY_SYSCLK_DIV_16_5_BIT, 0UL))
        {
            /* Insert error handling */
        }
    }

    /* Restore the divider's enable/disable state */
    if (divEnabled)
    {
        if (CY_SYSCLK_SUCCESS != Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_16_5_BIT, 0UL))
        {
            /* Insert error handling */
        }
    }

Cy_SysClk_PeriphGetAssignedDivider()

__STATIC_INLINE uint32_t Cy_SysClk_PeriphGetAssignedDivider

(

en_clk_dst_t

periphNum

)

Reports which clock divider is assigned to a selected IP block.

Parameters

periphNum

specifies the peripheral block en_clk_dst_t.

Returns

The divider type and number, where bits [7:6] = type, bits[5:0] = divider number within that type

Function Usage

    /* Scenario: There is a need to set a precise baud rate for SCB3-based UART. For example take the 16.5-bit divider #0 */
    /* Check if the divider is enabled */
    bool divEnabled = Cy_SysClk_PeriphDividerIsEnabled(CY_SYSCLK_DIV_16_5_BIT, 0UL);

    /* If enabled - let's disable it before the divider factor changing */
    if (divEnabled)
    {
        if (CY_SYSCLK_SUCCESS != Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_16_5_BIT, 0UL))
        {
            /* Insert error handling */
        }
    }

    /* Assume we need UART baud rate 115200 and oversampling ratio 8 */
    uint32_t achievedFreq = Cy_SysClk_PeriphSetFrequency(CY_SYSCLK_DIV_16_5_BIT, 0UL, 8UL * 115200UL);
    /* Now the achievedFreq contains the real achieved peripheral clock divider output frequency */

    /* Get the current assigned divider */
    uint32_t currDiv = Cy_SysClk_PeriphGetAssignedDivider(PCLK_SCB3_CLOCK);
    /* Make the desired divider value to compare */
    uint32_t fracDiv = _VAL2FLD(CY_SYSCLK_PERI_DIV_TYPE, CY_SYSCLK_DIV_16_5_BIT) | _VAL2FLD(CY_SYSCLK_PERI_DIV_NUM, 0UL);

    if(currDiv != fracDiv)
    {
        /* Assign 16-bit divider #3 to source TCPWM CNT0 clock */
        if (CY_SYSCLK_SUCCESS != Cy_SysClk_PeriphAssignDivider(PCLK_SCB3_CLOCK, CY_SYSCLK_DIV_16_5_BIT, 0UL))
        {
            /* Insert error handling */
        }
    }

    /* Restore the divider's enable/disable state */
    if (divEnabled)
    {
        if (CY_SYSCLK_SUCCESS != Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_16_5_BIT, 0UL))
        {
            /* Insert error handling */
        }
    }