Functions
cy_en_sysclk_status_t	Cy_SysClk_PllSetSource (uint32_t pllNum, cy_en_sysclk_pll_src_t source)
	Selects the PLL reference clock of the selected HFCLK. More...

__STATIC_INLINE cy_en_sysclk_pll_src_t	Cy_SysClk_PllGetSource (uint32_t pllNum)
	Returns the clock source of the specified PLL. More...

cy_en_sysclk_status_t	Cy_SysClk_PllConfigure (uint32_t pllNum, const cy_stc_sysclk_pll_config_t *config)
	Configures a given PLL. More...

cy_en_sysclk_status_t	Cy_SysClk_PllManualConfigure (uint32_t pllNum, const cy_stc_sysclk_pll_manual_config_t *config)
	Manually configures a PLL based on user inputs. More...

cy_en_sysclk_status_t	Cy_SysClk_PllEnable (uint32_t pllNum, uint32_t timeoutUs)
	Enables the PLL. More...

void	Cy_SysClk_PllGetConfiguration (uint32_t pllNum, cy_stc_sysclk_pll_manual_config_t *config)
	Reports configuration settings for a PLL. More...

uint32_t	Cy_SysClk_PllGetFrequency (uint32_t pllNum)
	Reports the output frequency of the specified PLL. More...

__STATIC_INLINE bool	Cy_SysClk_PllIsEnabled (uint32_t pllNum)
	Reports whether or not the selected PLL is enabled. More...

__STATIC_INLINE bool	Cy_SysClk_PllIsLocked (uint32_t pllNum)
	Reports whether or not the selected PLL is locked. More...

void	Cy_SysClk_PllBypass (uint32_t pllNum, cy_en_sysclk_pll_bypass_t mode)
	Sets PLL bypass mode. More...

__STATIC_INLINE cy_en_sysclk_pll_bypass_t	Cy_SysClk_PllGetBypassState (uint32_t pllNum)
	Returns the PLL bypass state. More...

__STATIC_INLINE bool	Cy_SysClk_PllLostLock (uint32_t pllNum)
	Reports whether or not the selected PLL lost its lock since the last time this function was called. More...

__STATIC_INLINE void	Cy_SysClk_PllDisable (uint32_t pllNum)
	Disables the selected PLL. More...

Detailed Description

Function Documentation

◆ Cy_SysClk_PllSetSource()

cy_en_sysclk_status_t Cy_SysClk_PllSetSource	(	uint32_t	pllNum,
		cy_en_sysclk_pll_src_t	source
	)

Selects the PLL reference clock of the selected HFCLK.

Note: Not applicable for PSOC4 HVMS/PA.

Parameters

pllNum	the number of PLL instance, starting from 0. If there is only one PLL in device - the 0 is the only valid number.
source	cy_en_sysclk_pll_src_t

Returns: Error / status code cy_en_sysclk_status_t :
CY_SYSCLK_SUCCESS - the PLL reference clock source is selected
CY_SYSCLK_INVALID_STATE - the PLL reference clock source is not enabled
CY_SYSCLK_BAD_PARAM - some input parameter is invalid

Note: Call SystemCoreClockUpdate after this function calling if SYSCLK frequency is affected.; Call Cy_SysLib_SetWaitStates before this function calling if SYSCLK frequency is increasing.; Call Cy_SysLib_SetWaitStates after this function calling if SYSCLK frequency is decreasing.; In case of switching to the CY_SYSCLK_PLL_SRC_EXTREF the EXTREF frequency should be specified using Cy_SysClk_ExtRefSetFrequency.

Function Usage: /* Scenario: there is a need to switch the source clock for already working PLL from IMO to ECO */
cy_stc_sysclk_pll_config_t pllConfig =
{
.inputFreq = Cy_SysClk_EcoGetFrequency(), /* Put the ECO frequency at the PLL input */
.outputFreq = Cy_SysClk_PllGetFrequency(0UL) /* Set the same frequency as it is currently */
};
if (CY_SYSCLK_SUCCESS != Cy_SysClk_ClkHfSetSource(CY_SYSCLK_CLKHF_IN_IMO)) /* First switch HfClk to a stable source */
{
/* Insert error handling */
}
Cy_SysClk_PllBypass(0U, CY_SYSCLK_PLL_BYP_AUTO); /* Ensure the Bypass is correct */
Cy_SysClk_PllDisable(0UL); /* Disable the PLL prior to the next manipulations */
if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllConfigure(0UL, &pllConfig)) /* Reconfigure for new input frequency */
{
/* Insert error handling */
}
if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllSetSource(0UL, CY_SYSCLK_PLL_SRC_ECO)) /* Set the correct clock source */
{
/* Insert error handling */
}
if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllEnable(0UL, 250UL)) /* Finally enable the PLL with new settings and clock source */
{
/* Insert error handling */
}
if (CY_SYSCLK_SUCCESS != Cy_SysClk_ClkHfSetSource(CY_SYSCLK_CLKHF_IN_EXCO)) /* Now switch HfClk to the PLL */
{
/* Insert error handling */
}

◆ Cy_SysClk_PllGetSource()

__STATIC_INLINE cy_en_sysclk_pll_src_t Cy_SysClk_PllGetSource ( uint32_t pllNum )

Returns the clock source of the specified PLL.

Note: Not applicable for PSOC4 HVMS/PA.

Parameters

pllNum the number of PLL instance, starting from 0. If there is only one PLL in device - the 0 is the only valid number. For other pllNum values the default CY_SYSCLK_PLL_SRC_ECO value is returned.

Returns: cy_en_sysclk_pll_src_t :
CY_SYSCLK_PLL_SRC_ECO - PLL runs from ECO.
CY_SYSCLK_PLL_SRC_EXTREF - PLL runs from the external reference.
CY_SYSCLK_PLL_SRC_IMO - PLL runs from IMO.

Function Usage: /* Scenario: PLL needs to source HFCLK, which must operate at 24 MHz.
The ECO sources the PLL at 4 MHz. Startup time is not an issue
and manual configuration of the PLL is not needed. */
cy_stc_sysclk_pll_config_t pllConfig =
{
/*.inputFreq =*/ 4000000UL, /* PLL input: 4 MHz ECO */
/*.outputFreq =*/ 24000000UL /* PLL output: 24 MHz */
};
if (CY_SYSCLK_PLL_SRC_ECO != Cy_SysClk_PllGetSource(0UL))
{
/* Set the PLL source to be the ECO. */
if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllSetSource(0UL, CY_SYSCLK_PLL_SRC_ECO))
{
/* Insert error handling */
}
}
/* Configure PLL0 with the settings in pllConfig struct */
if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllConfigure(0UL, &pllConfig))
{
/* Insert error handling */
}
/* Enable the PLL0 with a timeout of 250 microseconds */
if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllEnable(0UL, 250UL))
{
/* Insert error handling */
}

◆ Cy_SysClk_PllConfigure()

cy_en_sysclk_status_t Cy_SysClk_PllConfigure	(	uint32_t	pllNum,
		const cy_stc_sysclk_pll_config_t *	config
	)

Configures a given PLL.

The configuration formula used is:
Fout = Fin * P / (Q + 1) / (1 << OUT)
where:
Fout is the real PLL output frequency
Fin is the frequency of the input clock source
P is the feedback divider. Its value is in bitfield FEEDBACK_DIV.
Q is the reference divider. Its value is in bitfield REFERENCE_DIV.
OUT is the output divider. Its value is in bitfield OUTPUT_DIV.

Parameters

pllNum	the number of PLL instance, starting from 0. If there is only one PLL in device - the 0 is the only valid number.
config	The pointer to a configuration structure cy_stc_sysclk_pll_config_t

Returns: Error / status code cy_en_sysclk_status_t :
CY_SYSCLK_SUCCESS - PLL successfully configured
CY_SYSCLK_INVALID_STATE - PLL not configured because it is already enabled
CY_SYSCLK_BAD_PARAM - One or more invalid parameters.

Note: In case of returning CY_SYSCLK_BAD_PARAM the function does not write anything into the configuration register, so either the previous correct configuration or the default configuration remains in the register.; Call this function after changing the PLL input frequency, for example if Cy_SysClk_ImoSetFrequency() or Cy_SysClk_PllSetSource() is called.; Do not call this function when the PLL is enabled. If it is called, then this function returns immediately with an error return value and no register updates.; Call SystemCoreClockUpdate after this function calling if it affects the HFCLK frequency.; Call Cy_SysLib_SetWaitStates before calling this function if the PLL is the source of HFCLK and the PLL frequency is increasing.; Call Cy_SysLib_SetWaitStates after calling this function if the PLL is the source of HFCLK and the PLL frequency is decreasing.; Due to the integer nature of the P, Q and OUT dividers, the real PLL output frequency could slightly differ from the desired value (specified by the cy_stc_sysclk_pll_config_t::outputFreq). So please check the real PLL output frequency using Cy_SysClk_PllGetFrequency.; Not applicable for PSOC4 HVMS/PA.

Function Usage: /* Scenario: PLL needs to source HFCLK, which must operate at 24 MHz.
The ECO sources the PLL at 4 MHz. Startup time is not an issue
and manual configuration of the PLL is not needed. */
cy_stc_sysclk_pll_config_t pllConfig =
{
/*.inputFreq =*/ 4000000UL, /* PLL input: 4 MHz ECO */
/*.outputFreq =*/ 24000000UL /* PLL output: 24 MHz */
};
if (CY_SYSCLK_PLL_SRC_ECO != Cy_SysClk_PllGetSource(0UL))
{
/* Set the PLL source to be the ECO. */
if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllSetSource(0UL, CY_SYSCLK_PLL_SRC_ECO))
{
/* Insert error handling */
}
}
/* Configure PLL0 with the settings in pllConfig struct */
if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllConfigure(0UL, &pllConfig))
{
/* Insert error handling */
}
/* Enable the PLL0 with a timeout of 250 microseconds */
if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllEnable(0UL, 250UL))
{
/* Insert error handling */
}

◆ Cy_SysClk_PllManualConfigure()

cy_en_sysclk_status_t Cy_SysClk_PllManualConfigure	(	uint32_t	pllNum,
		const cy_stc_sysclk_pll_manual_config_t *	config
	)

Manually configures a PLL based on user inputs.

Parameters

pllNum	the number of PLL instance, starting from 0. If there is only one PLL in device - the 0 is the only valid number.
config	cy_stc_sysclk_pll_manual_config_t

Returns: Error / status code cy_en_sysclk_status_t :
CY_SYSCLK_SUCCESS - PLL successfully configured
CY_SYSCLK_INVALID_STATE - PLL not configured because it is already enabled
CY_SYSCLK_BAD_PARAM - One or more invalid parameters.

Note: In case of returning CY_SYSCLK_BAD_PARAM the function does not write anything into the configuration register, so either the previous correct configuration or the default configuration remains in the register.; Call this function after changing the PLL input frequency, for example if Cy_SysClk_ImoSetFrequency() or Cy_SysClk_PllSetSource() is called.; Do not call this function when the PLL is enabled. If it is called, then this function returns immediately with an error return value and no register updates.; Call SystemCoreClockUpdate after this function calling if it affects the HFCLK frequency.; Call Cy_SysLib_SetWaitStates before calling this function if the PLL is the source of HFCLK and the PLL frequency is increasing.; Call Cy_SysLib_SetWaitStates after calling this function if the PLL is the source of HFCLK and the PLL frequency is decreasing.; Not applicable for PSOC4 HVMS/PA.

Function Usage: /* Scenario: PLL needs to be manually reconfigured:
* the reference divider should be changed to 10.
* ECO is enabled.
*/
cy_stc_sysclk_pll_manual_config_t pllConfig;
if (Cy_SysClk_PllIsEnabled(0UL))
{
Cy_SysClk_PllBypass(0UL, CY_SYSCLK_PLL_BYP_ECO); /* Bypass the PLL */
Cy_SysClk_PllDisable(0UL);
}
Cy_SysClk_PllGetConfiguration(0UL, &pllConfig);
/* Refer to the TRM for the full set of equations used to calculate the PLL settings */
pllConfig.referenceDiv = 10U;
/* Configure PLL0 with the settings in pllConfig structure */
if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllManualConfigure(0UL, &pllConfig))
{
/* Insert error handling */
}
/* Call PllEnable with zero timeout */
(void) Cy_SysClk_PllEnable(0UL, 0UL); /* Ignore the status - it always is success in case of zero timeout */
/* Check the status of the lock */
while (Cy_SysClk_PllIsLocked(0UL))
{
/* Perform other actions while the PLL is locking */
}
Cy_SysClk_PllBypass(0UL, CY_SYSCLK_PLL_BYP_AUTO); /* Set auto-bypass mode */
uint32_t pllFreq = Cy_SysClk_PllGetFrequency(0UL);

◆ Cy_SysClk_PllEnable()

cy_en_sysclk_status_t Cy_SysClk_PllEnable	(	uint32_t	pllNum,
		uint32_t	timeoutUs
	)

Enables the PLL.

The PLL should be configured before calling this function.

Parameters

pllNum	the number of PLL instance, starting from 0. If there is only one PLL in device - the 0 is the only valid number.
timeoutUs	amount of time in microseconds to wait for the PLL to lock. If the lock doesn't occur, PLL is stopped. To avoid waiting for lock, set this to 0 and manually check for lock using Cy_SysClk_PllIsLocked.

Returns: Error / status code cy_en_sysclk_status_t :
CY_SYSCLK_SUCCESS - PLL successfully enabled
CY_SYSCLK_TIMEOUT - Timeout waiting for PLL lock
CY_SYSCLK_BAD_PARAM - invalid clock path number

Note: Call SystemCoreClockUpdate after this function calling if it affects the HFCLK frequency.; Call Cy_SysLib_SetWaitStates before calling this function if the PLL is the source of HFCLK and the HFCLK frequency is increasing.; Call Cy_SysLib_SetWaitStates after calling this function if the PLL is the source of HFCLK and the HFCLK frequency is decreasing.; Not applicable for PSOC4 HVMS/PA.

Function Usage: /* Scenario: PLL needs to source HFCLK, which must operate at 24 MHz.
The ECO sources the PLL at 4 MHz. Startup time is not an issue
and manual configuration of the PLL is not needed. */
cy_stc_sysclk_pll_config_t pllConfig =
{
/*.inputFreq =*/ 4000000UL, /* PLL input: 4 MHz ECO */
/*.outputFreq =*/ 24000000UL /* PLL output: 24 MHz */
};
if (CY_SYSCLK_PLL_SRC_ECO != Cy_SysClk_PllGetSource(0UL))
{
/* Set the PLL source to be the ECO. */
if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllSetSource(0UL, CY_SYSCLK_PLL_SRC_ECO))
{
/* Insert error handling */
}
}
/* Configure PLL0 with the settings in pllConfig struct */
if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllConfigure(0UL, &pllConfig))
{
/* Insert error handling */
}
/* Enable the PLL0 with a timeout of 250 microseconds */
if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllEnable(0UL, 250UL))
{
/* Insert error handling */
}

◆ Cy_SysClk_PllGetConfiguration()

void Cy_SysClk_PllGetConfiguration	(	uint32_t	pllNum,
		cy_stc_sysclk_pll_manual_config_t *	config
	)

Reports configuration settings for a PLL.

Parameters

pllNum	the number of PLL instance, starting from 0. If there is only one PLL in device - the 0 is the only valid number.
config	cy_stc_sysclk_pll_manual_config_t

Note: Not applicable for PSOC4 HVMS/PA.

Function Usage: /* Scenario: PLL needs to be manually reconfigured:
* the reference divider should be changed to 10.
* ECO is enabled.
*/
cy_stc_sysclk_pll_manual_config_t pllConfig;
if (Cy_SysClk_PllIsEnabled(0UL))
{
Cy_SysClk_PllBypass(0UL, CY_SYSCLK_PLL_BYP_ECO); /* Bypass the PLL */
Cy_SysClk_PllDisable(0UL);
}
Cy_SysClk_PllGetConfiguration(0UL, &pllConfig);
/* Refer to the TRM for the full set of equations used to calculate the PLL settings */
pllConfig.referenceDiv = 10U;
/* Configure PLL0 with the settings in pllConfig structure */
if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllManualConfigure(0UL, &pllConfig))
{
/* Insert error handling */
}
/* Call PllEnable with zero timeout */
(void) Cy_SysClk_PllEnable(0UL, 0UL); /* Ignore the status - it always is success in case of zero timeout */
/* Check the status of the lock */
while (Cy_SysClk_PllIsLocked(0UL))
{
/* Perform other actions while the PLL is locking */
}
Cy_SysClk_PllBypass(0UL, CY_SYSCLK_PLL_BYP_AUTO); /* Set auto-bypass mode */
uint32_t pllFreq = Cy_SysClk_PllGetFrequency(0UL);

◆ Cy_SysClk_PllGetFrequency()

uint32_t Cy_SysClk_PllGetFrequency ( uint32_t pllNum )

Reports the output frequency of the specified PLL.

Parameters

pllNum the number of PLL instance, starting from 0. If there is only one PLL in device - the 0 is the only valid number.

Returns: The frequency, in Hz.

Note: Not applicable for PSOC4 HVMS/PA.

Function Usage: /* Scenario: PLL needs to be manually reconfigured:
* the reference divider should be changed to 10.
* ECO is enabled.
*/
cy_stc_sysclk_pll_manual_config_t pllConfig;
if (Cy_SysClk_PllIsEnabled(0UL))
{
Cy_SysClk_PllBypass(0UL, CY_SYSCLK_PLL_BYP_ECO); /* Bypass the PLL */
Cy_SysClk_PllDisable(0UL);
}
Cy_SysClk_PllGetConfiguration(0UL, &pllConfig);
/* Refer to the TRM for the full set of equations used to calculate the PLL settings */
pllConfig.referenceDiv = 10U;
/* Configure PLL0 with the settings in pllConfig structure */
if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllManualConfigure(0UL, &pllConfig))
{
/* Insert error handling */
}
/* Call PllEnable with zero timeout */
(void) Cy_SysClk_PllEnable(0UL, 0UL); /* Ignore the status - it always is success in case of zero timeout */
/* Check the status of the lock */
while (Cy_SysClk_PllIsLocked(0UL))
{
/* Perform other actions while the PLL is locking */
}
Cy_SysClk_PllBypass(0UL, CY_SYSCLK_PLL_BYP_AUTO); /* Set auto-bypass mode */
uint32_t pllFreq = Cy_SysClk_PllGetFrequency(0UL);

◆ Cy_SysClk_PllIsEnabled()

__STATIC_INLINE bool Cy_SysClk_PllIsEnabled ( uint32_t pllNum )

Reports whether or not the selected PLL is enabled.

Parameters

pllNum the number of PLL instance, starting from 0. If there is only one PLL in device - the 0 is the only valid number. For other pllNum values the false (disabled) is returned.

Returns: false = disabled
true = enabled

Note: Not applicable for PSOC4 HVMS/PA.

Function Usage: /* Scenario: PLL needs to be manually reconfigured:
* the reference divider should be changed to 10.
* ECO is enabled.
*/
cy_stc_sysclk_pll_manual_config_t pllConfig;
if (Cy_SysClk_PllIsEnabled(0UL))
{
Cy_SysClk_PllBypass(0UL, CY_SYSCLK_PLL_BYP_ECO); /* Bypass the PLL */
Cy_SysClk_PllDisable(0UL);
}
Cy_SysClk_PllGetConfiguration(0UL, &pllConfig);
/* Refer to the TRM for the full set of equations used to calculate the PLL settings */
pllConfig.referenceDiv = 10U;
/* Configure PLL0 with the settings in pllConfig structure */
if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllManualConfigure(0UL, &pllConfig))
{
/* Insert error handling */
}
/* Call PllEnable with zero timeout */
(void) Cy_SysClk_PllEnable(0UL, 0UL); /* Ignore the status - it always is success in case of zero timeout */
/* Check the status of the lock */
while (Cy_SysClk_PllIsLocked(0UL))
{
/* Perform other actions while the PLL is locking */
}
Cy_SysClk_PllBypass(0UL, CY_SYSCLK_PLL_BYP_AUTO); /* Set auto-bypass mode */
uint32_t pllFreq = Cy_SysClk_PllGetFrequency(0UL);

◆ Cy_SysClk_PllIsLocked()

__STATIC_INLINE bool Cy_SysClk_PllIsLocked ( uint32_t pllNum )

Reports whether or not the selected PLL is locked.

Parameters

pllNum the number of PLL instance, starting from 0. If there is only one PLL in device - the 0 is the only valid number. For other pllNum values the false (unlocked) is returned.

Returns: false = not locked
true = locked

Note: Not applicable for PSOC4 HVMS/PA.

Function Usage: /* Scenario: PLL needs to be manually reconfigured:
* the reference divider should be changed to 10.
* ECO is enabled.
*/
cy_stc_sysclk_pll_manual_config_t pllConfig;
if (Cy_SysClk_PllIsEnabled(0UL))
{
Cy_SysClk_PllBypass(0UL, CY_SYSCLK_PLL_BYP_ECO); /* Bypass the PLL */
Cy_SysClk_PllDisable(0UL);
}
Cy_SysClk_PllGetConfiguration(0UL, &pllConfig);
/* Refer to the TRM for the full set of equations used to calculate the PLL settings */
pllConfig.referenceDiv = 10U;
/* Configure PLL0 with the settings in pllConfig structure */
if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllManualConfigure(0UL, &pllConfig))
{
/* Insert error handling */
}
/* Call PllEnable with zero timeout */
(void) Cy_SysClk_PllEnable(0UL, 0UL); /* Ignore the status - it always is success in case of zero timeout */
/* Check the status of the lock */
while (Cy_SysClk_PllIsLocked(0UL))
{
/* Perform other actions while the PLL is locking */
}
Cy_SysClk_PllBypass(0UL, CY_SYSCLK_PLL_BYP_AUTO); /* Set auto-bypass mode */
uint32_t pllFreq = Cy_SysClk_PllGetFrequency(0UL);

◆ Cy_SysClk_PllBypass()

void Cy_SysClk_PllBypass	(	uint32_t	pllNum,
		cy_en_sysclk_pll_bypass_t	mode
	)

Sets PLL bypass mode.

Parameters

pllNum	the number of PLL instance, starting from 0. If there is only one PLL in device - the 0 is the only valid number.
mode	the bypass mode cy_en_sysclk_pll_bypass_t.

Note: Call SystemCoreClockUpdate after this function calling if it affects the HFCLK frequency.; Call Cy_SysLib_SetWaitStates before calling this function if the PLL is the source of HFCLK and the HFCLK frequency is increasing.; Call Cy_SysLib_SetWaitStates after calling this function if the PLL is the source of HFCLK and the HFCLK frequency is decreasing.; Not applicable for PSOC4 HVMS/PA.

Function Usage: /* Scenario: HFCLK needs to be switched to the ECO (if ECO is enabled, of course) */
if (Cy_SysClk_EcoIsEnabled() && (CY_SYSCLK_ECO_STABLE == Cy_SysClk_EcoGetStatus())) /* If ECO enabled and stabilized */
{
if (CY_SYSCLK_PLL_BYP_ECO != Cy_SysClk_PllGetBypassState(0U))
{
Cy_SysClk_PllBypass(0U, CY_SYSCLK_PLL_BYP_ECO); /* First make multiplexing inside the EXCO block */
}
sysclkStatus = Cy_SysClk_ClkHfSetSource(CY_SYSCLK_CLKHF_IN_EXCO);
if (CY_SYSCLK_SUCCESS != sysclkStatus)
{
/* Insert error handling */
}
}

◆ Cy_SysClk_PllGetBypassState()

__STATIC_INLINE cy_en_sysclk_pll_bypass_t Cy_SysClk_PllGetBypassState ( uint32_t pllNum )

Returns the PLL bypass state.

Parameters

pllNum the number of PLL instance, starting from 0. If there is only one PLL in device - the 0 is the only valid number.

Returns: The bypass state cy_en_sysclk_pll_bypass_t :
CY_SYSCLK_PLL_BYP_AUTO - ECO when PLL is not locked, and PLL output when locked.
CY_SYSCLK_PLL_BYP_ECO - ECO regardless of PLL lock/enable status.
CY_SYSCLK_PLL_BYP_PLL - PLL Output regardless of lock status.

Note: Not applicable for PSOC4 HVMS/PA.

Function Usage: /* Scenario: HFCLK needs to be switched to the ECO (if ECO is enabled, of course) */
if (Cy_SysClk_EcoIsEnabled() && (CY_SYSCLK_ECO_STABLE == Cy_SysClk_EcoGetStatus())) /* If ECO enabled and stabilized */
{
if (CY_SYSCLK_PLL_BYP_ECO != Cy_SysClk_PllGetBypassState(0U))
{
Cy_SysClk_PllBypass(0U, CY_SYSCLK_PLL_BYP_ECO); /* First make multiplexing inside the EXCO block */
}
sysclkStatus = Cy_SysClk_ClkHfSetSource(CY_SYSCLK_CLKHF_IN_EXCO);
if (CY_SYSCLK_SUCCESS != sysclkStatus)
{
/* Insert error handling */
}
}

◆ Cy_SysClk_PllLostLock()

__STATIC_INLINE bool Cy_SysClk_PllLostLock ( uint32_t pllNum )

Reports whether or not the selected PLL lost its lock since the last time this function was called.

Clears the lost lock indicator.

Parameters

pllNum the number of PLL instance, starting from 0. If there is only one PLL in device - the 0 is the only valid number. For other pllNum values the false (did not lose lock) is returned.

Returns: false = did not lose lock
true = lost lock

Note: Not applicable for PSOC4 HVMS/PA.

Function Usage: /* Scenario: Suspicious change in PLL source clock frequency was encountered
in the application. Check if the PLL0 have lost the lock. */
if (Cy_SysClk_PllLostLock(0UL))
{
/* Review the design work flow and eliminate the PLL source clock
* sudden change during PLL work (unless it is done intended or unavoidable).
*/
}

◆ Cy_SysClk_PllDisable()

__STATIC_INLINE void Cy_SysClk_PllDisable ( uint32_t pllNum )

Disables the selected PLL.

Parameters

pllNum the number of PLL instance, starting from 0. If there is only one PLL in device - the 0 is the only valid number.

Note: Call SystemCoreClockUpdate after this function calling if it affects the HFCLK frequency.; Call Cy_SysLib_SetWaitStates before calling this function if the PLL is the source of HFCLK and the HFCLK frequency is increasing.; Call Cy_SysLib_SetWaitStates after calling this function if the PLL is the source of HFCLK and the HFCLK frequency is decreasing.; Not applicable for PSOC4 HVMS/PA.

Function Usage: /* Scenario: PLL needs to be manually reconfigured:
* the reference divider should be changed to 10.
* ECO is enabled.
*/
cy_stc_sysclk_pll_manual_config_t pllConfig;
if (Cy_SysClk_PllIsEnabled(0UL))
{
Cy_SysClk_PllBypass(0UL, CY_SYSCLK_PLL_BYP_ECO); /* Bypass the PLL */
Cy_SysClk_PllDisable(0UL);
}
Cy_SysClk_PllGetConfiguration(0UL, &pllConfig);
/* Refer to the TRM for the full set of equations used to calculate the PLL settings */
pllConfig.referenceDiv = 10U;
/* Configure PLL0 with the settings in pllConfig structure */
if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllManualConfigure(0UL, &pllConfig))
{
/* Insert error handling */
}
/* Call PllEnable with zero timeout */
(void) Cy_SysClk_PllEnable(0UL, 0UL); /* Ignore the status - it always is success in case of zero timeout */
/* Check the status of the lock */
while (Cy_SysClk_PllIsLocked(0UL))
{
/* Perform other actions while the PLL is locking */
}
Cy_SysClk_PllBypass(0UL, CY_SYSCLK_PLL_BYP_AUTO); /* Set auto-bypass mode */
uint32_t pllFreq = Cy_SysClk_PllGetFrequency(0UL);

Functions

Detailed Description

Function Documentation

◆ Cy_SysClk_PllSetSource()

◆ Cy_SysClk_PllGetSource()

◆ Cy_SysClk_PllConfigure()

◆ Cy_SysClk_PllManualConfigure()

◆ Cy_SysClk_PllEnable()

◆ Cy_SysClk_PllGetConfiguration()

◆ Cy_SysClk_PllGetFrequency()

◆ Cy_SysClk_PllIsEnabled()

◆ Cy_SysClk_PllIsLocked()

◆ Cy_SysClk_PllBypass()

◆ Cy_SysClk_PllGetBypassState()

◆ Cy_SysClk_PllLostLock()

◆ Cy_SysClk_PllDisable()