SRAM Functions

Functions
void	Cy_ISOUART_NodeConfigSramRowAttr (ISOUART_Type *base, uint32_t index, uint8_t trigIntId, bool isInvalid, bool isReadOnly)
	Configure iso UART SRAM attributes. More...
void	Cy_ISOUART_HostSetSramSize (ISOUART_Type *base, uint32_t lowSramSize, uint32_t highSramSize)
	Set SRAM size for data reception. More...
volatile uint32_t *	Cy_ISOUART_HostGetSramBaseAddr (ISOUART_Type *base, cy_en_isouart_interface_side_t iSide)
	Get iso UART SRAM base address of the specified interface. More...
uint16_t	Cy_ISOUART_ReadSramRow16 (ISOUART_Type *base, uint32_t index)
	Read a 16-bit data field from the specified iso UART SRAM row. More...
uint32_t	Cy_ISOUART_ReadSramRow32 (ISOUART_Type *base, uint32_t index)
	Read a 32-bit data from two consecutive iso UART SRAM rows. More...
void	Cy_ISOUART_WriteSramRow16 (ISOUART_Type *base, uint32_t index, uint16_t data)
	Write a 16-bit value to the data field of the specified iso UART SRAM row. More...
void	Cy_ISOUART_WriteSramRow32 (ISOUART_Type *base, uint32_t index, uint32_t data)
	Write a 32-bit data to two consecutive iso UART SRAM rows. More...
void	Cy_ISOUART_HostReadSramRaw (ISOUART_Type *base, cy_en_isouart_interface_side_t iSide, uint32_t packetNum, cy_stc_isouart_raw_frame_t *frame)
	Reads RAW data frames from the iso UART SRAM of specified interface. More...
uint16_t	Cy_ISOUART_HostReadSramUnpack (ISOUART_Type *base, cy_en_isouart_interface_side_t iSide, uint32_t packetNum)
	Reads UNPACKED data from the iso UART SRAM of specified interface. More...
__STATIC_INLINE void	Cy_ISOUART_EnableEcc (ISOUART_Type *base)
	Enable ECC for iso UART SRAM. More...
__STATIC_INLINE void	Cy_ISOUART_DisableEcc (ISOUART_Type *base)
	Disable ECC for iso UART SRAM. More...
void	Cy_ISOUART_EnableEccInjection (ISOUART_Type *base, uint32_t index, uint32_t parity)
	Enable ECC error injection for iso UART SRAM. More...
void	Cy_ISOUART_DisableEccInjection (ISOUART_Type *base)
	Disable ECC error injection for iso UART SRAM. More...
void	Cy_ISOUART_GetEccStatus (const ISOUART_Type *base, cy_stc_isouart_ecc_status_t *status)
	Get ECC status of iso UART SRAM. More...

Detailed Description

Function Documentation

Cy_ISOUART_NodeConfigSramRowAttr()

void Cy_ISOUART_NodeConfigSramRowAttr	(	ISOUART_Type *	base,
		uint32_t	index,
		uint8_t	trigIntId,
		bool	isInvalid,
		bool	isReadOnly
	)

Configure iso UART SRAM attributes.

Parameters

base	The base address for the iso UART.
index	Index of iso UART SRAM row. The valid range is 0...127.
trigIntId	ID of trigger and interrupt struct to be tied to this SRAM row. The valid range is 0...17.
isInvalid	Specifies whether the row is invalid or not. If TRUE, the specified index is marked as invalid. Any access to the invalid row by the host via iso UART will be reported as address error.
isReadOnly	Specifies whether the row is read only or not. If TRUE, the specified index is marked as read only. A write access to the read only row by the host via iso UART will be reported as access error.

Note

This function is valid for Node.
As an exception, this function may also be used by a Host configured in internal loopback mode to simulate Node behavior for testing purposes.

Function Usage

    /* Scenario: Configure the iso UART Node interrupt trigger structure and SRAM row attributes.
     * This setup enables Primary Access interrupt on write operations to SRAM address 0.
     * The interrupt handler (IntrHandler) will process the triggered interrupt.
     */

    /* Use trigger structure ID 1 to configure */
    const uint8_t intrTrigStructId = 1U;

    /* Configure interrupt trigger structure */
    Cy_ISOUART_NodeConfigTriggerInt(ISOUART,
                                intrTrigStructId,          /* Trigger structure ID */
                                CY_ISOUART_EVENT_NONE,     /* Trigger source */
                                CY_ISOUART_EVENT_WRITE,    /* Primary interrupt source */
                                CY_ISOUART_EVENT_NONE);    /* Secondary interrupt source */

    /* Configure SRAM row attributes for address 0 */
    Cy_ISOUART_NodeConfigSramRowAttr(ISOUART,
                                    SRAM_ADDRESS,       /* SRAM address */
                                    intrTrigStructId,   /* Trigger structure ID */
                                    false,              /* Invalid address disabled */
                                    false);             /* Read protection disabled */

Cy_ISOUART_HostSetSramSize()

void Cy_ISOUART_HostSetSramSize	(	ISOUART_Type *	base,
		uint32_t	lowSramSize,
		uint32_t	highSramSize
	)

Set SRAM size for data reception.

The required SRAM size depends on the read command types (read, broadcast read, multi read). This function is intended to be used for re-allocating SRAM size suitable for the read command being sent.

Parameters

base	The base address for the iso UART.
lowSramSize	SRAM size in low side. The valid range is 0..127. In RAW mode, this parameter must be divisible by 3.
highSramSize	SRAM size in high side. The valid range is 0..127. In RAW mode, this parameter must be divisible by 3.

Note

This function is valid only for Host. The sum of lowSramSize and highSramSize must not exceed total SRAM size. The SRAM size shall only be changed when iso UART is disabled or both interfaces are in Slave mode.

Function Usage

    /* Scenario: Perform read operation from specific node in Master-on-Top topology.
     * This demonstrates SRAM size configuration, reading data from node, and unpacked data retrieval.
     * This example uses polling to wait for command completion instead of interrupt-driven approach.
     */
    const uint32_t address = 0UL;   /* SRAM address to read from. */

    /* Disable iso UART block. */
    Cy_ISOUART_Disable(ISOUART);

    /* For the proper handling, set the interface SRAM size to the expected size by the transaction.
     * NOTE: The SRAM size shall only be changed when iso UART is disabled or both interfaces are in Slave mode.
     * e.g. for unpack mode, normal read command = 1
     * e.g. for raw mode, normal read command = 3
     * e.g. for unpack mode, multi read command = 1 x number of multi read
     * e.g. for unpack mode, BC read command = 1 x number of nodes in the chain
     */
    Cy_ISOUART_HostSetSramSize(ISOUART, 1UL, 0UL); /* Set the Low side 1 row, High side 0 row. */

    /* Enable iso UART to operate. */
    Cy_ISOUART_Enable(ISOUART);

    /* Perform Read operation. */
    Cy_ISOUART_HostSendReadCommand(ISOUART, blockId, nodeId, address);
    /* Wait for Read command completion by polling SRAM_FULL interrupt status
     * (interface side depends on topology) instead of using interrupt service routine.
     */
    uint32_t intrStatus = 0UL;
    do
    {
        intrStatus = Cy_ISOUART_GetInterruptStatus(ISOUART);
    } while (0UL == (intrStatus & CY_ISOUART_INTR_MASTER_LOW_SRAM_FULL));

    /* Clear interrupt flags. */
    Cy_ISOUART_ClearInterrupt(ISOUART, intrStatus);

    /* Read data from low interface SRAM. */
    uint16_t readData = Cy_ISOUART_HostReadSramUnpack(ISOUART, CY_ISOUART_IF_LOW, 0UL);
    /* Process the read data */

Cy_ISOUART_HostGetSramBaseAddr()

volatile uint32_t* Cy_ISOUART_HostGetSramBaseAddr	(	ISOUART_Type *	base,
		cy_en_isouart_interface_side_t	iSide
	)

Get iso UART SRAM base address of the specified interface.

This is a helper function for combination with DMA.

Parameters

base	The base address for the iso UART.
iSide	Interface side. See cy_en_isouart_interface_side_t.

Returns

Pointer to the start address of the iso UART SRAM for the specified interface side.

Note

This function is valid only for Host.

Function Usage

    /* Scenario: Get SRAM base address for the required interface to configure DMA transfers.
    * This API provides the starting address of SRAM for specified interface (High or Low)
    * which can be used as source or destination address in DMA descriptors.
    */
    #define CHANN_NUM   (0UL)

    /* Get SRAM base address for Low interface */
    volatile uint32_t *sramBaseAddr = Cy_ISOUART_HostGetSramBaseAddr(ISOUART, CY_ISOUART_IF_LOW);

    /* Configure DMA descriptor with obtained SRAM base address */
    Cy_DMAC_Descriptor_SetSrcAddress(DMAC, CHANN_NUM, CY_DMAC_DESCRIPTOR_PING, sramBaseAddr);

Cy_ISOUART_ReadSramRow16()

uint16_t Cy_ISOUART_ReadSramRow16	(	ISOUART_Type *	base,
		uint32_t	index
	)

Read a 16-bit data field from the specified iso UART SRAM row.

Parameters

base	The base address for the iso UART.
index	Index of iso UART SRAM row. The valid range is 0...127.

Returns

16-bit value read from the iso UART SRAM row.

Note

This function is valid for both Host and Node.

Function Usage

/* Scenario: Handle iso UART Node interrupts including Wake-up and Primary Access events.
 * This handler processes write operations to SRAM address 0 and wakeup signals from Host.
 */
void IntrHandler(void)
{
    uint32_t intrStatus = Cy_ISOUART_GetInterruptStatusMasked(ISOUART);
    Cy_ISOUART_ClearInterrupt(ISOUART, intrStatus);

    /* Check for Wake-up interrupt on both interfaces. */
    if (0UL != (intrStatus & (CY_ISOUART_INTR_WAKE_HIGH | CY_ISOUART_INTR_WAKE_LOW)))
    {
        /* Handle Wake-up interrupt. */
    }

    /* Check for Primary Access interrupt. */
    if (0UL != (intrStatus & CY_ISOUART_INTR_REG_ACCESS_P))
    {
        /* Get the interrupt address and event type. */
        uint8_t intrAddress = Cy_ISOUART_NodeGetIntrAddrPrim(ISOUART);
        cy_en_isouart_event_t intrEvent = Cy_ISOUART_NodeGetIntrEventPrim(ISOUART);

        /* Check if write command was sent to the expected SRAM address. */
        if ((SRAM_ADDRESS == intrAddress) && (CY_ISOUART_EVENT_WRITE == intrEvent))
        {
            /* Read the received data from SRAM. */
            receivedData = Cy_ISOUART_ReadSramRow16(ISOUART, intrAddress);
            /* Process received data. */
        }
    }
}

Cy_ISOUART_ReadSramRow32()

uint32_t Cy_ISOUART_ReadSramRow32	(	ISOUART_Type *	base,
		uint32_t	index
	)

Read a 32-bit data from two consecutive iso UART SRAM rows.

The output 32-bit data is configured as follows:

• Bits [15:0] contain the data from the even index (index).
• Bits [31:16] contain the data from the odd index (index + 1).

  Parameters

  base	The base address for the iso UART.
  index	Index of iso UART SRAM row (must be even). The valid range is 0...126, and this parameter must be an even value.

  Returns

  32-bit value read from two consecutive iso UART SRAM rows.

  Note

  This function is valid for both Host and Node.

Cy_ISOUART_WriteSramRow16()

void Cy_ISOUART_WriteSramRow16	(	ISOUART_Type *	base,
		uint32_t	index,
		uint16_t	data
	)

Write a 16-bit value to the data field of the specified iso UART SRAM row.

Parameters

base	The base address for the iso UART.
index	Index of iso UART SRAM row. The valid range is 0...127.
data	16-bit value to be written to the SRAM row.

Note

This function is valid for both Host and Node.

Cy_ISOUART_WriteSramRow32()

void Cy_ISOUART_WriteSramRow32	(	ISOUART_Type *	base,
		uint32_t	index,
		uint32_t	data
	)

Write a 32-bit data to two consecutive iso UART SRAM rows.

The input 32-bit data should be configured as follows:

• Bits [15:0] should contain the data for the even index.
• Bits [31:16] should contain the data for the odd index.

  Parameters

  base	The base address for the iso UART.
  index	Index of iso UART SRAM row (must be even). The valid range is 0...126, and this parameter must be an even value.
  data	32-bit value to be written to two consecutive SRAM rows.

  Note

  This function is valid for both Host and Node.

Cy_ISOUART_HostReadSramRaw()

void Cy_ISOUART_HostReadSramRaw	(	ISOUART_Type *	base,
		cy_en_isouart_interface_side_t	iSide,
		uint32_t	packetNum,
		cy_stc_isouart_raw_frame_t *	frame
	)

Reads RAW data frames from the iso UART SRAM of specified interface.

Parameters

base	The base address for the iso UART.
iSide	Interface side to be read. See cy_en_isouart_interface_side_t.
packetNum	Packet number to be read. Valid range is [0, (allocated SRAM size for iSide / 3) - 1].
frame	Pointer to the structure for storing RAW frame data. See cy_stc_isouart_raw_frame_t.

Note

This function is valid only when:

• The interface is initialized as Host mode.
• The receiver mode is configured as CY_ISOUART_RECEIVER_MODE_RAW.

Cy_ISOUART_HostReadSramUnpack()

uint16_t Cy_ISOUART_HostReadSramUnpack	(	ISOUART_Type *	base,
		cy_en_isouart_interface_side_t	iSide,
		uint32_t	packetNum
	)

Reads UNPACKED data from the iso UART SRAM of specified interface.

Parameters

base	The base address for the iso UART.
iSide	Interface side to be read. See cy_en_isouart_interface_side_t.
packetNum	Packet number to be read. Valid range is [0, allocated SRAM size for iSide - 1].

Returns

Unpacked data (16-bit value).

Note

This function is valid only when:

• The interface is initialized as Host mode.
• The receiver mode is configured as CY_ISOUART_RECEIVER_MODE_UNPACKED.

Function Usage

    /* Scenario: Perform read operation from specific node in Master-on-Top topology.
     * This demonstrates SRAM size configuration, reading data from node, and unpacked data retrieval.
     * This example uses polling to wait for command completion instead of interrupt-driven approach.
     */
    const uint32_t address = 0UL;   /* SRAM address to read from. */

    /* Disable iso UART block. */
    Cy_ISOUART_Disable(ISOUART);

    /* For the proper handling, set the interface SRAM size to the expected size by the transaction.
     * NOTE: The SRAM size shall only be changed when iso UART is disabled or both interfaces are in Slave mode.
     * e.g. for unpack mode, normal read command = 1
     * e.g. for raw mode, normal read command = 3
     * e.g. for unpack mode, multi read command = 1 x number of multi read
     * e.g. for unpack mode, BC read command = 1 x number of nodes in the chain
     */
    Cy_ISOUART_HostSetSramSize(ISOUART, 1UL, 0UL); /* Set the Low side 1 row, High side 0 row. */

    /* Enable iso UART to operate. */
    Cy_ISOUART_Enable(ISOUART);

    /* Perform Read operation. */
    Cy_ISOUART_HostSendReadCommand(ISOUART, blockId, nodeId, address);
    /* Wait for Read command completion by polling SRAM_FULL interrupt status
     * (interface side depends on topology) instead of using interrupt service routine.
     */
    uint32_t intrStatus = 0UL;
    do
    {
        intrStatus = Cy_ISOUART_GetInterruptStatus(ISOUART);
    } while (0UL == (intrStatus & CY_ISOUART_INTR_MASTER_LOW_SRAM_FULL));

    /* Clear interrupt flags. */
    Cy_ISOUART_ClearInterrupt(ISOUART, intrStatus);

    /* Read data from low interface SRAM. */
    uint16_t readData = Cy_ISOUART_HostReadSramUnpack(ISOUART, CY_ISOUART_IF_LOW, 0UL);
    /* Process the read data */

Cy_ISOUART_EnableEcc()

__STATIC_INLINE void Cy_ISOUART_EnableEcc

(

ISOUART_Type *

base

)

Enable ECC for iso UART SRAM.

Parameters

base	The base address for the iso UART.

Note

This function is valid for both Host and Node.

Cy_ISOUART_DisableEcc()

__STATIC_INLINE void Cy_ISOUART_DisableEcc

(

ISOUART_Type *

base

)

Disable ECC for iso UART SRAM.

Parameters

base	The base address for the iso UART.

Note

This function is valid for both Host and Node.

Cy_ISOUART_EnableEccInjection()

void Cy_ISOUART_EnableEccInjection	(	ISOUART_Type *	base,
		uint32_t	index,
		uint32_t	parity
	)

Enable ECC error injection for iso UART SRAM.

Parameters

base	The base address for the iso UART.
index	Index of iso UART SRAM row where an error will be injected. The valid range is 0...127.
parity	ECC parity to use for ECC error injection at SRAM index. The valid range is 0...127. During the ECC error injection is enabled, when the SRAM[index] is written, ECC parity is forced to be updated with this value instead of the value calculated by HW.

Note

This function is valid for both Host and Node.
During the ECC error injection is enabled, access to the SRAM[index] will never cause bus error on uncorrectable ECC error or address error. Reporting to FAULT structure is valid even if the ECC error injection is enabled. The ECC error injection mechanism actually updates the SRAM parity, so the inserted ECC error will still cause the error after the ECC error injection is disabled. It's recommended to re-initialize the SRAM[index] with 32 bits write after disabling the ECC error injection to reset the ECC parity with correct value.

Cy_ISOUART_DisableEccInjection()

void Cy_ISOUART_DisableEccInjection

(

ISOUART_Type *

base

)

Disable ECC error injection for iso UART SRAM.

Parameters

base	The base address for the iso UART.

Note

This function is valid for both Host and Node.

Cy_ISOUART_GetEccStatus()

void Cy_ISOUART_GetEccStatus	(	const ISOUART_Type *	base,
		cy_stc_isouart_ecc_status_t *	status
	)

Get ECC status of iso UART SRAM.

Parameters

base	The base address for the iso UART.
status	Pointer to a status structure to be filled. See cy_stc_isouart_ecc_status_t.

Note

This function is valid for both Host and Node.