Host Functions

Functions
void	Cy_ISOUART_HostInit (ISOUART_Type *base, const cy_stc_isouart_host_config_t *config)
	Full Init of the iso UART in host mode. More...
void	Cy_ISOUART_HostEnableWakeSequence (ISOUART_Type *base, uint32_t wakeCmdDelay)
	Enables the transmission of wake sequence. More...
__STATIC_INLINE uint8_t	Cy_ISOUART_HostReadLowInterface (const ISOUART_Type *base)
	Reads the latest frame data from the Low interface. More...
__STATIC_INLINE uint8_t	Cy_ISOUART_HostReadHighInterface (const ISOUART_Type *base)
	Reads the latest frame data from the High interface. More...
void	Cy_ISOUART_HostSendWriteCommand (ISOUART_Type *base, uint32_t blockId, uint32_t nodeId, uint32_t address, uint16_t data)
	Sends a write command frame (sequenced mode) to a node. More...
void	Cy_ISOUART_HostSendReadCommand (ISOUART_Type *base, uint32_t blockId, uint32_t nodeId, uint32_t address)
	Sends a read command frame (sequenced mode) to a node. More...
void	Cy_ISOUART_HostSendManualCommand (ISOUART_Type *base, uint8_t data)
	Sends a single 8-bit frame in manual mode. More...
bool	Cy_ISOUART_HostVerifyCRC (uint8_t frameData)
	Verifies the CRC contained in a write response byte. More...

Detailed Description

Function Documentation

Cy_ISOUART_HostInit()

void Cy_ISOUART_HostInit	(	ISOUART_Type *	base,
		const cy_stc_isouart_host_config_t *	config
	)

Full Init of the iso UART in host mode.

Parameters

base	The base address for the iso UART.
config	Configuration options for the iso UART in host mode. See cy_stc_isouart_host_config_t.

Note

This function is valid only for Host.

Warning

This function depends on the SysClk frequency and requires re-initialization if it changes to avoid frame errors. Ensure that CSV events (if enabled) are handled properly and trigger re-initialization if the SysClk source switches to the backup source.

Function Usage

    /* Populate Host configuration structure */
    const cy_stc_isouart_host_config_t hostConfig =
    {
        .topology               = CY_ISOUART_MOT,                       /* Master-on-Top topology. */
        .hostBitrate            = CY_ISOUART_HOST_BITRATE_2_1MBPS,      /* 2.1 Mbps data rate. */
        .receiverMode           = CY_ISOUART_RECEIVER_MODE_UNPACKED,    /* Unpacked receive mode. */
        .crcPolicy              = CY_ISOUART_CRC8_SAE_J1850,            /* CRC8 SAE J1850 polynomial. */
        .enableBlockId          = true,                                 /* Enable Block ID feature. */
        .useWriteDoneTrig       = false,                                /* No trigger on write complete. */
        .useLowSramFullTrig     = false,                                /* No trigger when low SRAM full. */
        .useHighSramFullTrig    = false,                                /* No trigger when high SRAM full. */
        .enableMultiReadBC      = false,                                /* Disable broadcast multi-read. */
        .enableInternalLoopback = false,                                /* Disable internal loopback. */
    };

    /* Configure iso UART Host to operate */
    Cy_ISOUART_HostInit(ISOUART, &hostConfig);

Cy_ISOUART_HostEnableWakeSequence()

void Cy_ISOUART_HostEnableWakeSequence	(	ISOUART_Type *	base,
		uint32_t	wakeCmdDelay
	)

Enables the transmission of wake sequence.

The registered wake sequence will be sent prior to next command transmission.

Parameters

base	The base address for the iso UART.
wakeCmdDelay	Amount of delay between wake sequence and command frame. Each count corresponds to 1/(iso UART IP input clock [Hz]) seconds. Valid range is [0x2EE0 ... 0x3FFC]. The appropriate delay value is specific to the node hardware - refer to the target node IC datasheet for the required delay specification.

Note

This function is valid only for Host.

Function Usage

    /* Scenario: Perform node enumeration in Master-on-Top topology.
     * This process assigns a unique ID to a node and configures it as the final node in the chain.
     * This example uses polling to wait for command completion instead of interrupt-driven approach.
     */
    const uint32_t blockId = 0UL;   /* Applied block ID (Applicable if block ID is enabled). */
    const uint32_t nodeId  = 1UL;   /* Applied ID to the node, must start from 0 and sequential. */
    const bool isFinalNode = true;  /* Specify the node is the last node in the chain, this config affects broadcast command. */

    /* For the 1st command, enable the wakeup sequence to awake nodes in the chain.
     * This request is one-shot, no need to send a wakeup sequence other than the 1st command.
     * The wakeup delay depends on the nodes in the chain, the delay allows nodes to set up themselves to react to commands.
     */
    Cy_ISOUART_HostEnableWakeSequence(ISOUART, 0x2EE0UL);

    /* Prepare node configuration data. */
    const uint16_t configData = (nodeId | (blockId << 6UL) | (isFinalNode << 11UL));

    /* Send the configuration command into the bus.
     * Node ID in the enumeration command must be 0.
     * Prior to the command frame, the requested wakeup sequence will be sent.
     */
    Cy_ISOUART_HostSendWriteCommand(ISOUART, blockId, 0UL, CY_ISOUART_ADDR_CONFIG, configData);

    /* Wait for Write command completion by polling FRAME_RECEIVED interrupt status
     * (interface side depends on topology) instead of using interrupt service routine.
     */
    uint32_t intrStatus = 0UL;
    do
    {
        intrStatus = Cy_ISOUART_GetInterruptStatusMasked(ISOUART);
    } while (0UL == (intrStatus & CY_ISOUART_INTR_MASTER_LOW_FRAME_RECEIVED));

    /* Clear interrupt flags. */
    Cy_ISOUART_ClearInterrupt(ISOUART, intrStatus);

    /* Read the write response from low interface (because of MOT topology)
     * and verify the CRC of the write response.
     */
    uint8_t regVal_low = Cy_ISOUART_HostReadLowInterface(ISOUART);
    bool ret_low = Cy_ISOUART_HostVerifyCRC(regVal_low);

    if (false == ret_low)
    {
        /* Handle the incorrect CRC data in the write response. */
    }

Cy_ISOUART_HostReadLowInterface()

__STATIC_INLINE uint8_t Cy_ISOUART_HostReadLowInterface

(

const ISOUART_Type *

base

)

Reads the latest frame data from the Low interface.

Parameters

base	The base address for the iso UART.

Returns

The latest frame data from the Low interface.

Note

This function is valid only for Host.

Function Usage

    /* Scenario: Perform write operation to specific node in Master-on-Top topology.
     * This demonstrates sending data to node SRAM and verifying write response with CRC check.
     * This example uses polling to wait for command completion instead of interrupt-driven approach.
     */
    /* Write command parameters */
    const uint32_t address   = 0UL;         /* SRAM address to write to. */
    const uint32_t writeData = 0x1234UL;    /* Data to write. */

    /* Send Write command in sequenced mode. */
    Cy_ISOUART_HostSendWriteCommand(ISOUART, blockId, nodeId, address, writeData);

    /* Wait for Write command completion by polling FRAME_RECEIVED interrupt status
     * (interface side depends on topology) instead of using interrupt service routine.
     */
    uint32_t intrStatus = 0UL;
    do
    {
        intrStatus = Cy_ISOUART_GetInterruptStatus(ISOUART);
    } while (0UL == (intrStatus & CY_ISOUART_INTR_MASTER_LOW_FRAME_RECEIVED));

    /* Clear interrupt flags. */
    Cy_ISOUART_ClearInterrupt(ISOUART, intrStatus);

    /* Read the write response from low interface (because of MOT topology)
     * and verify the CRC of the write response.
     */
    uint8_t regVal_low = Cy_ISOUART_HostReadLowInterface(ISOUART);
    bool ret_low = Cy_ISOUART_HostVerifyCRC(regVal_low);

    if (false == ret_low)
    {
        /* Handle incorrect CRC data in write response. */
    }

Cy_ISOUART_HostReadHighInterface()

__STATIC_INLINE uint8_t Cy_ISOUART_HostReadHighInterface

(

const ISOUART_Type *

base

)

Reads the latest frame data from the High interface.

Parameters

base	The base address for the iso UART.

Returns

The latest frame data from the High interface.

Note

This function is valid only for Host.

Cy_ISOUART_HostSendWriteCommand()

void Cy_ISOUART_HostSendWriteCommand	(	ISOUART_Type *	base,
		uint32_t	blockId,
		uint32_t	nodeId,
		uint32_t	address,
		uint16_t	data
	)

Sends a write command frame (sequenced mode) to a node.

If a wake sequence was previously enabled with Cy_ISOUART_HostEnableWakeSequence(), the wake sequence is transmitted automatically before this frame.

Parameters

base	The base address for the iso UART.
blockId	Block ID placed in the frame when block ID feature is enabled. Valid range: 0..6 (ignored if block ID is disabled).
nodeId	Target node ID. 0 : Enumeration 1..30 : Normal node IDs 63 : Broadcast
address	Target register / SRAM address. Valid range: 0..127.
data	16-bit payload to be written.

Note

• Clears the internal wake sequence pending flag after transmission.
• This function is valid only for Host.

Function Usage

    /* Scenario: Perform write operation to specific node in Master-on-Top topology.
     * This demonstrates sending data to node SRAM and verifying write response with CRC check.
     * This example uses polling to wait for command completion instead of interrupt-driven approach.
     */
    /* Write command parameters */
    const uint32_t address   = 0UL;         /* SRAM address to write to. */
    const uint32_t writeData = 0x1234UL;    /* Data to write. */

    /* Send Write command in sequenced mode. */
    Cy_ISOUART_HostSendWriteCommand(ISOUART, blockId, nodeId, address, writeData);

    /* Wait for Write command completion by polling FRAME_RECEIVED interrupt status
     * (interface side depends on topology) instead of using interrupt service routine.
     */
    uint32_t intrStatus = 0UL;
    do
    {
        intrStatus = Cy_ISOUART_GetInterruptStatus(ISOUART);
    } while (0UL == (intrStatus & CY_ISOUART_INTR_MASTER_LOW_FRAME_RECEIVED));

    /* Clear interrupt flags. */
    Cy_ISOUART_ClearInterrupt(ISOUART, intrStatus);

    /* Read the write response from low interface (because of MOT topology)
     * and verify the CRC of the write response.
     */
    uint8_t regVal_low = Cy_ISOUART_HostReadLowInterface(ISOUART);
    bool ret_low = Cy_ISOUART_HostVerifyCRC(regVal_low);

    if (false == ret_low)
    {
        /* Handle incorrect CRC data in write response. */
    }

Cy_ISOUART_HostSendReadCommand()

void Cy_ISOUART_HostSendReadCommand	(	ISOUART_Type *	base,
		uint32_t	blockId,
		uint32_t	nodeId,
		uint32_t	address
	)

Sends a read command frame (sequenced mode) to a node.

If a wake sequence was previously enabled with Cy_ISOUART_HostEnableWakeSequence(), the wake sequence is transmitted automatically before this frame.

Parameters

base	The base address for the iso UART.
blockId	Block ID placed in the frame when the block ID feature is enabled. Valid range: 0..6 (ignored if the feature is disabled).
nodeId	Target node ID. 0 : Enumeration 1..30 : Normal node IDs 63 : Broadcast
address	Target register / SRAM address. Valid range: 0..127.

Note

• Clears the internal wake sequence pending flag after transmission.
• This function is valid only for Host.

Function Usage

    /* Scenario: Perform read operation from specific node in Master-on-Top topology.
     * This demonstrates SRAM size configuration, reading data from node, and unpacked data retrieval.
     * This example uses polling to wait for command completion instead of interrupt-driven approach.
     */
    const uint32_t address = 0UL;   /* SRAM address to read from. */

    /* Disable iso UART block. */
    Cy_ISOUART_Disable(ISOUART);

    /* For the proper handling, set the interface SRAM size to the expected size by the transaction.
     * NOTE: The SRAM size shall only be changed when iso UART is disabled or both interfaces are in Slave mode.
     * e.g. for unpack mode, normal read command = 1
     * e.g. for raw mode, normal read command = 3
     * e.g. for unpack mode, multi read command = 1 x number of multi read
     * e.g. for unpack mode, BC read command = 1 x number of nodes in the chain
     */
    Cy_ISOUART_HostSetSramSize(ISOUART, 1UL, 0UL); /* Set the Low side 1 row, High side 0 row. */

    /* Enable iso UART to operate. */
    Cy_ISOUART_Enable(ISOUART);

    /* Perform Read operation. */
    Cy_ISOUART_HostSendReadCommand(ISOUART, blockId, nodeId, address);
    /* Wait for Read command completion by polling SRAM_FULL interrupt status
     * (interface side depends on topology) instead of using interrupt service routine.
     */
    uint32_t intrStatus = 0UL;
    do
    {
        intrStatus = Cy_ISOUART_GetInterruptStatus(ISOUART);
    } while (0UL == (intrStatus & CY_ISOUART_INTR_MASTER_LOW_SRAM_FULL));

    /* Clear interrupt flags. */
    Cy_ISOUART_ClearInterrupt(ISOUART, intrStatus);

    /* Read data from low interface SRAM. */
    uint16_t readData = Cy_ISOUART_HostReadSramUnpack(ISOUART, CY_ISOUART_IF_LOW, 0UL);
    /* Process the read data */

Cy_ISOUART_HostSendManualCommand()

void Cy_ISOUART_HostSendManualCommand	(	ISOUART_Type *	base,
		uint8_t	data
	)

Sends a single 8-bit frame in manual mode.

If a wake sequence was previously enabled with Cy_ISOUART_HostEnableWakeSequence(), the wake sequence is transmitted automatically before this frame.

Parameters

base	The base address for the iso UART.
data	1 byte frame to transmit.

Note

• Clears the internal wake sequence pending flag after transmission.
• This function is valid only for Host.

Cy_ISOUART_HostVerifyCRC()

bool Cy_ISOUART_HostVerifyCRC

(

uint8_t

frameData

)

Verifies the CRC contained in a write response byte.

Compares the lower 3 bits (CRC) of the supplied write response byte against the expected CRC looked up using the upper 5 bits as index. The response can be obtained via Cy_ISOUART_HostReadLowInterface() or Cy_ISOUART_HostReadHighInterface(). An interrupt after the write command completion indicates the reply is available.

Parameters

frameData

Write response frame byte (bits[7:3] = payload, bits[2:0] = CRC).

Returns

true - CRC matches the expected value (response byte is valid). false - CRC mismatch (response byte is invalid).

Note

This function is valid only for Host.

Function Usage

    /* Scenario: Perform write operation to specific node in Master-on-Top topology.
     * This demonstrates sending data to node SRAM and verifying write response with CRC check.
     * This example uses polling to wait for command completion instead of interrupt-driven approach.
     */
    /* Write command parameters */
    const uint32_t address   = 0UL;         /* SRAM address to write to. */
    const uint32_t writeData = 0x1234UL;    /* Data to write. */

    /* Send Write command in sequenced mode. */
    Cy_ISOUART_HostSendWriteCommand(ISOUART, blockId, nodeId, address, writeData);

    /* Wait for Write command completion by polling FRAME_RECEIVED interrupt status
     * (interface side depends on topology) instead of using interrupt service routine.
     */
    uint32_t intrStatus = 0UL;
    do
    {
        intrStatus = Cy_ISOUART_GetInterruptStatus(ISOUART);
    } while (0UL == (intrStatus & CY_ISOUART_INTR_MASTER_LOW_FRAME_RECEIVED));

    /* Clear interrupt flags. */
    Cy_ISOUART_ClearInterrupt(ISOUART, intrStatus);

    /* Read the write response from low interface (because of MOT topology)
     * and verify the CRC of the write response.
     */
    uint8_t regVal_low = Cy_ISOUART_HostReadLowInterface(ISOUART);
    bool ret_low = Cy_ISOUART_HostVerifyCRC(regVal_low);

    if (false == ret_low)
    {
        /* Handle incorrect CRC data in write response. */
    }