Triggering Type.
Enumerator | |
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CY_DMAC_SINGLE_ELEMENT | A single trigger initiates a single data element transfer. |
CY_DMAC_SINGLE_DESCR | A single trigger initiates a single descriptor transfer. |
CY_DMAC_DESCR_LIST | A single trigger initiates a descriptor list transfer. This option relies on cy_stc_dmac_descriptor_config_t::flipping to be set to 'true', such that the cy_stc_dmac_channel_config_t::descriptor field is flipped/inverted and the successive descriptor is used. |
enum cy_en_dmac_status_t |
The descriptor response codes.
The first two codes NO_ERROR and DONE are the result of normal behavior, the other codes are the result of erroneous behavior.
Enumerator | |
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CY_DMAC_NO_ERROR | No error. Setting this response does NOT set the interrupt cause bit. The descriptor validness status is not affected. The channel enable state is not affected. The channel current descriptor status is not updated. This response is used for an unused or not completed descriptor. |
CY_DMAC_DONE | The descriptor is done (without errors). Setting this response sets the interrupt bit if cy_stc_dmac_descriptor_config_t::interrupt is true. The descriptor is invalidated if cy_stc_dmac_descriptor_config_t::cpltState is true. The channel enable state is not affected. The channel current descriptor status is updated if cy_stc_dmac_descriptor_config_t::flipping is true. |
CY_DMAC_SRC_BUS_ERROR | A bus error while loading data from the source location. Setting this response sets the correspondent interrupt bit. The descriptor is invalidated. The channel is disabled. The channel current descriptor status is not updated (it identifies the descriptor that caused the error). |
CY_DMAC_DST_BUS_ERROR | A bus error while storing data to the destination location. Setting this response sets the correspondent interrupt bit. The descriptor is invalidated. The channel is disabled. The channel current descriptor status is not updated (it identifies the descriptor that caused the error). |
CY_DMAC_SRC_MISAL | Misalignment of the source address. This occurs on a source 16-bit bus transfer that is not 2-byte aligned or on a 32-bit bus transfer that is not 4-byte aligned. Setting this response sets the correspondent interrupt bit. The descriptor is invalidated. The channel is disabled. The channel current descriptor status is not updated (it identifies the descriptor that caused the error). |
CY_DMAC_DST_MISAL | Misalignment of the destination address. This occurs on a destination 16-bit bus transfer that is not 2-byte aligned or on a 32-bit bus transfer that is not 4-byte aligned. Setting this response sets the correspondent interrupt bit. The descriptor is invalidated. The channel is disabled. The channel current descriptor status is not updated (it identifies the descriptor that caused the error). |
CY_DMAC_INVALID_DESCR | The invalid descriptor. This occurs when an activated channel has an invalidated/disabled descriptor (either by HW or FW). The channel is disabled. The channel current descriptor status is not updated (it identifies the descriptor that caused the error). |