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CAT2 Peripheral Driver Library
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CAT2 Peripheral Driver Library
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Macros | |
| #define | CY_ISOUART_INTR_WAKE_HIGH (ISOUART_INTR_WAKE_HIGH_Msk) |
| Wakeup Event on High Interface. | |
| #define | CY_ISOUART_INTR_WAKE_LOW (ISOUART_INTR_WAKE_LOW_Msk) |
| Wakeup Event on Low Interface. | |
| #define | CY_ISOUART_INTR_WDOG_CNT_TIMEOUT (ISOUART_INTR_WDOG_CNT_TIMEOUT_Msk) |
| Timeout of the watchdog counter, indicating that the interface is going to sleep mode. | |
| #define | CY_ISOUART_INTR_EMM (ISOUART_INTR_EMM_Msk) |
| The Emergency signal was transmitted by another part in the chain. | |
| #define | CY_ISOUART_INTR_REQUEST (ISOUART_INTR_REQUEST_Msk) |
| The host completed a request, with clean CRC (whether or not it was addressed to us) | |
| #define | CY_ISOUART_INTR_REQUEST_MATCH (ISOUART_INTR_REQUEST_MATCH_Msk) |
| The host completed a request, with device ID matching ours, with clean CRC. | |
| #define | CY_ISOUART_INTR_BC_WRITE (ISOUART_INTR_BC_WRITE_Msk) |
| The host completed a BC_WRITE request. | |
| #define | CY_ISOUART_INTR_BC_READ (ISOUART_INTR_BC_READ_Msk) |
| The host completed a BC_READ request. | |
| #define | CY_ISOUART_INTR_FRAME_ERR (ISOUART_INTR_FRAME_ERR_Msk) |
| Framing communication error. | |
| #define | CY_ISOUART_INTR_CRC_ERR (ISOUART_INTR_CRC_ERR_Msk) |
| CRC error. | |
| #define | CY_ISOUART_INTR_REG_ACCESS_P (ISOUART_INTR_REG_ACCESS_P_Msk) |
| Primary register specific access interrupt. | |
| #define | CY_ISOUART_INTR_REG_ACCESS_S (ISOUART_INTR_REG_ACCESS_S_Msk) |
| Secondary register specific access interrupt. | |
| #define | CY_ISOUART_INTR_UVD (ISOUART_INTR_UVD_Msk) |
| Under Voltage Detection. | |
| #define | CY_ISOUART_INTR_ECC_ERR (ISOUART_INTR_ECC_ERR_Msk) |
| ECC Error. | |
| #define | CY_ISOUART_INTR_WRITE_COMPLETE (ISOUART_INTR_WRITE_COMPLETE_Msk) |
| A master transaction completed. | |
| #define | CY_ISOUART_INTR_MASTER_LOW_FRAME_RECEIVED (ISOUART_INTR_MASTER_LOW_FRAME_RECEIVED_Msk) |
| A frame was received at the LOW interface while not in SLAVE mode (Master mode only) | |
| #define | CY_ISOUART_INTR_MASTER_HIGH_FRAME_RECEIVED (ISOUART_INTR_MASTER_HIGH_FRAME_RECEIVED_Msk) |
| A frame was received at the HIGH interface while not in SLAVE mode (Master mode only) | |
| #define | CY_ISOUART_INTR_MASTER_LOW_SRAM_FULL (ISOUART_INTR_MASTER_LOW_SRAM_FULL_Msk) |
| The LOW interface filled the allocated local SRAM (Master mode only) | |
| #define | CY_ISOUART_INTR_MASTER_HIGH_SRAM_FULL (ISOUART_INTR_MASTER_HIGH_SRAM_FULL_Msk) |
| The HIGH interface filled the allocated local SRAM (Master mode only) | |
| #define | CY_ISOUART_INTR_MASTER_INTERNAL_ERROR (ISOUART_INTR_MASTER_INTERNAL_ERROR_Msk) |
| An internal error such as configuration problem occurred (Master mode only) | |
| #define | CY_ISOUART_INTR_MASTER_CRC_ERROR (ISOUART_INTR_MASTER_CRC_ERROR_Msk) |
| A CRC value from slave didn't match expected value (Master mode only) | |
| #define | CY_ISOUART_INTR_MASTER_SLAVE_STATUS_ERROR (ISOUART_INTR_MASTER_SLAVE_STATUS_ERROR_Msk) |
| The slave returned a reply frame with status error bit set (Master mode only) | |
| #define | CY_ISOUART_INTR_MASTER_SLAVE_ACCESS_ERROR (ISOUART_INTR_MASTER_SLAVE_ACCESS_ERROR_Msk) |
| The slave returned a reply frame with access error bit set (Master mode only) | |
| #define | CY_ISOUART_INTR_MASTER_SLAVE_ADDRESS_ERROR (ISOUART_INTR_MASTER_SLAVE_ADDRESS_ERROR_Msk) |
| The slave returned a reply frame with address error bit set (Master mode only) | |
| #define | CY_ISOUART_INTR_MASTER_ALL |
| Master-specific interrupt masks combined. More... | |
| #define | CY_ISOUART_INTR_MASK_ALL |
| Combined iso UART interrupt mask. More... | |
| #define CY_ISOUART_INTR_MASTER_ALL |
Master-specific interrupt masks combined.
| #define CY_ISOUART_INTR_MASK_ALL |
Combined iso UART interrupt mask.