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#define | CY_CPU_CORTEX_M0P (__CORTEX_M == 0) |
| CM0+ core CPU Code.
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#define | CY_CPU_CORTEX_M4 (__CORTEX_M == 4) |
| CM4 core CPU Code.
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#define | CY_ARM_FAULT_DEBUG_DISABLED (0U) |
| The macro to disable the Fault Handler.
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#define | CY_ARM_FAULT_DEBUG_ENABLED (1U) |
| The macro to enable the Fault Handler.
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#define | CY_ARM_FAULT_DEBUG (CY_ARM_FAULT_DEBUG_ENABLED) |
| The macro defines if the Fault Handler is enabled. More...
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#define | CY_SYSLIB_DRV_VERSION_MAJOR 2 |
| The driver major version.
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#define | CY_SYSLIB_DRV_VERSION_MINOR 60 |
| The driver minor version.
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#define | CY_MAX_FILE_NAME_SIZE (24U) |
| The max size of the file name which stores the ASSERT location.
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#define | CY_R0_Pos (0U) |
| The position of the R0 content in a fault structure.
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#define | CY_R1_Pos (1U) |
| The position of the R1 content in a fault structure.
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#define | CY_R2_Pos (2U) |
| The position of the R2 content in a fault structure.
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#define | CY_R3_Pos (3U) |
| The position of the R3 content in a fault structure.
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#define | CY_R12_Pos (4U) |
| The position of the R12 content in a fault structure.
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#define | CY_LR_Pos (5U) |
| The position of the LR content in a fault structure.
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#define | CY_PC_Pos (6U) |
| The position of the PC content in a fault structure.
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#define | CY_PSR_Pos (7U) |
| The position of the PSR content in a fault structure.
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#define | CY_DELAY_MS_OVERFLOW (0x8000U) |
| Defines a 32-kHz clock delay.
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#define | CY_IPC_DATA_FOR_CM4_SOFT_RESET (0x1B000002UL) |
| Bit[31:24] Opcode = 0x1B (SoftReset) Bit[7:1] Type = 1 (Only CM4 reset)
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